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Patent # Description
US-1,016,2556 Multi-partitioning of memories
Various embodiments comprise devices and methods to manage multiple memory types and reconfigure partitions in a memory device as directed by a host. In one...
US-1,016,2526 Logical address history management in memory device
Some embodiments include apparatuses and methods including memory cells and a control unit to store information in a portion of the memory cells and to generate...
US-1,016,2406 Systems and methods for frequency mode detection and implementation
The systems and methods provided herein identify a command acquisition mode from a plurality of command acquisition modes of a command interface of a memory...
US-1,016,2377 Apparatuses and methods for providing reference voltages
A reference voltage generator is disclosed that may provide a plurality of reference voltages. A reference voltage generator may include a voltage divider, a...
US-1,016,2005 Scan chain operations
A number of embodiments include an apparatus comprising a memory array including a first memory bank and a second memory bank and a serializer/de-serializer...
US-1,015,8071 Semiconductor devices, memory devices, and related methods
Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the...
US-1,015,7965 Cross-point memory and methods for fabrication of same
The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same....
US-1,015,7933 Integrated structures including material containing silicon, nitrogen, and at least one of carbon, oxygen,...
Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive...
US-1,015,7926 Memory cells and memory arrays
Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors....
US-1,015,7913 Methods of forming an array comprising pairs of vertically opposed capacitors and arrays comprising pairs of...
A method of forming an array comprising pairs of vertically opposed capacitors comprises forming an upwardly-open conductive lining in individual capacitor...
US-1,015,7841 Construction of integrated circuitry and a method of forming an elevationally-extending conductor laterally...
A method includes forming insulative material along the opposing sides of a conductive via and a conductive line in a vertical cross-section comprising forming...
US-1,015,7830 3D interconnect multi-die inductors with through-substrate via cores
A semiconductor device having a first die and a second die is provided. The first die of the device includes a first surface and a through-substrate via (TSV)...
US-1,015,7788 Self-aligned interconnection for integrated circuits
Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one...
US-1,015,7769 Semiconductor devices including a diode structure over a conductive strap and methods of forming such...
Semiconductor devices including at least one diode over a conductive strap. The semiconductor device may include at least one conductive strap over an insulator...
US-1,015,7743 Methods of patterning a target layer
A method of forming patterns includes the steps of providing a substrate on which a target layer and a hard mask layer are formed; forming a plurality of first...
US-1,015,7673 Resistive random access memory having multi-cell memory bits
Some embodiments include methods of storing and retrieving data for an RRAM array. The array is subdivided into a plurality of memory bits, with each memory bit...
US-1,015,7670 Apparatuses including memory cells and methods of operation of same
Disclosed herein is a memory cell including a memory element and a selector device. The memory cell may be programmed with a programming pulse having a first...
US-1,015,7669 Method of storing and retrieving information for a resistive random access memory (RRAM) with multi-memory...
Some embodiments include methods of storing and retrieving data for an RRAM array. The array is subdivided into a plurality of memory bits, with each memory bit...
US-1,015,7667 Mixed cross point memory
Methods, systems, and devices for multi-deck memory arrays are described. A multi-deck memory device may include a memory array with a cell having a...
US-1,015,7661 Mitigating line-to-line capacitive coupling in a memory die
Methods, systems, and devices for mitigating line-to-line capacitive coupling in a memory die are described. A device may include multiple drivers configured to...
US-1,015,7650 Program operations in memory
The present disclosure includes apparatuses and methods related to program operations in memory. An example apparatus can perform a program operation on an...
US-1,015,7648 Data output for high frequency domain
A system includes memory banks that store data and a data path coupled to the memory banks that transfers the data. The system also includes a latch that gates...
US-1,015,7647 Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters
Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating...
US-1,015,7644 Methods and apparatus for generation of voltages
Methods of operating a voltage generation circuit, and apparatus configured to perform such methods, include applying a clock signal to an input of a voltage...
US-1,015,7643 Active boundary quilt architecture memory
Methods, systems, and apparatus that increase available memory or storage using active boundary areas in quilt architecture are described. A memory array may...
US-1,015,7208 Methods and apparatuses for reducing power consumption in a pattern recognition processor
Apparatuses and methods are provided for reducing power consumption in a pattern-recognition processor. A power control circuit may be coupled to a block of...
US-1,015,7165 Methods and devices for reducing array size and complexity in automata processors
A method includes calculating a first position encoded pattern based on a first data pattern, and using an automata processor to compare the first position...
US-1,015,7126 Swap operations in memory
Examples of the present disclosure provide apparatuses and methods related to performing swap operations in a memory. An example apparatus might include a first...
US-1,015,7019 Apparatuses and methods for data transfer from sensing circuitry to a controller
The present disclosure describes data transfer in a memory device from sensing circuitry to controller. An example apparatus includes a controller coupled to a...
US-1,015,6990 Data storage management
A method of managing a plurality of storage devices. The method comprises at a first device connected to the plurality of storage devices via a switch,...
US-1,015,6893 Wiring with external terminal
Apparatuses in data input/output circuits of a semiconductor device are described. An example apparatus includes an output driver and a pre-output driver. The...
US-1,015,3922 Analog multiplexing scheme for decision feedback equalizers
A device includes a voltage generator that generates a reference signal, a multi-level bias generator coupled to the voltage generator to receive the reference...
US-1,015,3775 Phase interpolator
Apparatuses and methods for phase interpolators are provided. An example apparatus comprises a phase interpolator and a controller coupled to the phase...
US-1,015,3433 Methods of forming memory cells
Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed...
US-1,015,3431 Resistive memory having confined filament formation
Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon...
US-1,015,3428 Structures incorporating and methods of forming metal lines including carbon
Disclosed technology relates generally to integrated circuits, and more particularly, to structures incorporating and methods of forming metal lines including...
US-1,015,3381 Memory cells having an access gate and a control gate and dielectric stacks above and below the access gate
In an example, a memory cell may have an access gate, a control gate coupled to the access gate, a first dielectric stack below an upper surface of a...
US-1,015,3348 Memory configurations
In an example, a memory may have a group of series-coupled memory cells, where a memory cell of the series-coupled memory cells has an access gate, a control...
US-1,015,3299 Vertical ferroelectric field effect transistor constructions, constructions comprising a pair of vertical...
A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating...
US-1,015,3298 Integrated structures and methods of forming vertically-stacked memory cells
Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within...
US-1,015,3281 Memory cells and memory arrays
Some embodiments include a memory cell having first and second transistors and first and second capacitors. The first capacitor is vertically displaced relative...
US-1,015,3254 Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing...
A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second ...
US-1,015,3251 Apparatuses and methods for scalable memory
Apparatuses and methods are provided for scalable memory. An example apparatus comprises a logic component, a plurality of memory components adjacent to and...
US-1,015,3221 Face down dual sided chip scale memory package
A semiconductor die that includes a first die located on a first side of an interposer and a second die located on a second side of the interposer. Active sides...
US-1,015,3200 Methods of forming a nanostructured polymer material including block copolymer materials
Methods for fabricating sub-lithographic, nanoscale microstructures utilizing self-assembling block copolymers, and films and devices formed from these methods...
US-1,015,3197 Methods of forming one or more covered voids in a semiconductor substrate
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
US-1,015,3196 Arrays of cross-point memory structures
Some embodiments include a memory array having a first set of lines extending along a first direction, and a second set of lines over the first set of lines and...
US-1,015,3195 Semiconductor constructions comprising dielectric material
Some embodiments include a semiconductor construction which has one or more openings extending into a substrate. The openings are at least partially filled with...
US-1,015,3194 Array of gated devices and methods of forming an array of gated devices
An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid...
US-1,015,3190 Devices, systems and methods for electrostatic force enhanced semiconductor bonding
Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for enhancing wafer bonding...
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