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Patent # Description
US-9,780,115 Three dimensional memory and methods of forming the same
Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the...
US-9,780,110 Memory having memory cell string and coupling components
Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the...
US-9,780,107 Methods of forming integrated circuit devices
Methods of forming integrated circuit devices containing memory cells over a first region of a semiconductor substrate and gate structures over a second region...
US-9,780,103 Methods of forming integrated structures
Some embodiments include an integrated structure having semiconductor material within a region between two parallel surfaces. The semiconductor material has...
US-9,780,102 Memory cell pillar including source junction plug
Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the...
US-9,780,079 Semiconductor die assembly and methods of forming thermal paths
Semiconductor die assemblies and methods of forming the same are described herein. As an example, a semiconductor die assembly may include a thermally...
US-9,780,052 Collars for under-bump metal structures and associated systems and methods
The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and...
US-9,780,029 Semiconductor constructions having conductive lines which merge with one another
Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the...
US-9,779,839 Methods for providing redundancy in a memory array comprising mapping portions of data associated with a...
Methods for providing redundancy in a memory include mapping a portion of first data associated with an address of the memory determined to indicate a defective...
US-9,779,829 Erasing memory segments in a memory block of memory cells using select gate control line voltages
A method includes applying erase voltages to data lines and source lines of a memory block of memory cells in a non-volatile NAND architecture memory device...
US-9,779,828 Inferring threshold voltage distributions associated with memory cells via interpolation
Apparatuses and methods for inferring threshold voltage distributions associated with memory cells via interpolation are described herein. An example includes...
US-9,779,826 Memory devices for reading memory cells of different memory planes
Memory devices may include digital-to-analog converters configured to convert digital values to analog read voltages and to apply the analog read voltages to...
US-9,779,822 Memory devices and methods of their operation during a programming operation
Methods of operating a memory device during a programming operation, and memory devices so configured, including increasing a voltage applied to a selected...
US-9,779,821 Fast programming memory device
In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one...
US-9,779,819 Connecting memory cells to a data line sequentially while applying a program voltage to the memory cells
In an example, a programming method includes applying a program voltage to a selected access line commonly connected to a first memory cell of a first string of...
US-9,779,817 Boosting channels of memory cells to reduce program disturb
A method for programming a non-volatile memory device includes concurrently boosting channels of memory cells in a selected memory string and an unselected...
US-9,779,816 Apparatus and methods including source gates
Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor...
US-9,779,806 Resistive memory sensing methods and devices
Resistive memory sensing methods and devices are described. One such method includes performing a voltage based multiple pass sensing operation on a group of...
US-9,779,805 Phase change memory device
A phase change memory device with memory cells (2) formed by a phase change memory element (3) and a selection switch (4). A reference cell (2a) formed by an...
US-9,779,800 Timing control circuit shared by a plurality of banks
Apparatuses and methods for providing activation timings of sense amplifiers in a semiconductor device are described. An example apparatus includes: a first...
US-9,779,796 Redundancy array column decoder for memory
Methods, systems, and apparatuses for redundancy in a memory array are described. A memory array may include some memory cells that are redundant to other...
US-9,779,791 Apparatuses and methods involving accessing distributed sub-blocks of memory cells
Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in...
US-9,779,789 Comparison operations in memory
The present disclosure includes apparatuses and methods related to performing comparison operations in memory. An example apparatus can include a first group of...
US-9,779,784 Apparatuses and methods for performing logical operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an...
US-9,779,138 Methods and systems for autonomous memory searching
Methods and systems operate to receive a plurality of search requests for searching a database in a memory system. The search requests can be stored in a FIFO...
US-9,779,057 Autonomous memory architecture
An autonomous memory device in a distributed memory sub-system can receive a database downloaded from a host controller. The autonomous memory device can pass...
US-9,779,039 Impedance adjustment in a memory device
Methods and apparatus for impedance adjustment operations in memory devices are disclosed. One such method includes adjusting an impedance of a particular...
US-9,779,025 Cache architecture for comparing data
The present disclosure includes apparatuses and methods for a cache architecture. An example apparatus that includes a cache architecture according to the...
US-9,779,019 Data storage layout
Examples of the present disclosure provide apparatuses and methods for determining a data storage layout. An example apparatus comprising a first address space...
US-9,778,903 Apparatuses and methods for timing domain crossing
Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain,...
US-9,778,875 Multi-partitioning of memories
Various embodiments comprise devices to manage multiple memory types and reconfigure partitions in a memory device as directed by a host. In one embodiment, the...
US-9,778,874 Data deduplication
The present disclosure includes devices and methods for data deduplication. One such method includes receiving a write command, transforming data associated...
US-9,778,846 Sequential memory access operations
Methods of operating a memory include performing a memory access operation, obtaining an address corresponding to a subsequent memory access operation prior to...
US-9,778,723 Apparatuses and methods for exiting low power states in memory devices
According to one embodiment, an apparatus is disclosed. The apparatus includes a memory device having a device identification, The apparatus further includes a...
US-9,778,416 Method and structure providing a front-end-of-line and a back-end-of-line coupled waveguides
An integrated structure and method of formation provide a lower level waveguide having a core of a first material and a higher level waveguide having a core of...
US-9,778,284 Semiconductor probe, testing device and testing method for testing quantum battery
A testing device and method of a quantum battery by a semiconductor probe capable of evaluating electric characteristics of a charge layer in the middle of a...
US-9,773,977 Phase change memory cells
A phase change memory cell has first and second electrodes having phase change material there-between. The phase change memory cell is devoid of heater material...
US-9,773,807 Conductive components and memory assemblies
Some embodiments include a memory assembly having memory cells proximate a conductive source. Channel material extends along the memory cells and is...
US-9,772,969 Detection circuit for mixed asynchronous and synchronous memory operation
A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit...
US-9,768,760 Synchronized semiconductor device with phase adjustment circuit
According to one embodiment, a synchronous semiconductor device is disclosed According to this embodiment, the synchronous semiconductor device includes a pulse...
US-9,768,378 Cross-point memory and methods for fabrication of same
The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same....
US-9,768,377 Magnetic cell structures, and methods of fabrication
A magnetic cell structure comprises a seed material including tantalum, platinum, and ruthenium. The seed material comprises a platinum portion overlying a...
US-9,768,376 Magnetic memory cells, semiconductor devices, and methods of operation
A magnetic cell core includes at least one stressor structure proximate to a magnetic region (e.g., a free region or a fixed region). The magnetic region may be...
US-9,768,366 Solid state optoelectronic device with preformed metal support substrate
A wafer-level process for manufacturing solid state lighting ("SSL") devices using large-diameter preformed metal substrates is disclosed. A light emitting...
US-9,768,330 Method and optoelectronic structure providing polysilicon photonic devices with different optical properties in...
Method and structural embodiments are described which provide an integrated structure using polysilicon material having different optical properties in...
US-9,768,271 Methods, devices, and systems related to forming semiconductor power devices with a handle substrate
Methods of manufacturing device assemblies, as well as associated semiconductor assemblies, devices, systems are disclosed herein. In one embodiment, a method...
US-9,768,194 Methods of forming memory arrays
A method of forming a memory array includes filling a circular hole that is lined with a charge trapping layer with a conductor, forming a first slot and a...
US-9,768,181 Ferroelectric memory and methods of forming the same
Ferroelectric memory and methods of forming the same are provided. An example memory cell can include a buried recessed access device (BRAD) formed in a...
US-9,768,177 Method of forming conductive material of a buried transistor gate line and method of forming a buried...
A method of forming conductive material of a buried transistor gate line includes adhering a precursor comprising tungsten and chlorine to material within a...
US-9,768,175 Semiconductor devices comprising gate structure sidewalls having different angles
The present disclosure provides a semiconductor device including a substrate, a first active region, a second active region, and a gate structure. The first...
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