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Patent # Description
US-9,613,978 Methods of forming semiconductor constructions
Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically...
US-9,613,973 Memory having a continuous channel
The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack...
US-9,613,943 Semiconductor device having output buffers and voltage path coupled to output buffers
An apparatus includes first and second data pads arranged adjacently to each other in a first direction without an intervention of a pad therebetween, first and...
US-9,613,902 Connections for memory electrode lines
Subject matter disclosed herein may relate to word line electrodes and/or digit line electrodes in a cross-point array memory device. One or more word line...
US-9,613,864 Low capacitance interconnect structures and associated systems and methods
Semiconductor device interconnect structures having low capacitance and associated systems and methods are disclosed herein. In one embodiment, a method of...
US-9,613,706 Programming and/or erasing a memory device in response to its program and/or erase history
A method includes sending a number of program/erase cycles from a memory of control logic of a memory device to a counter of the control logic, where the number...
US-9,613,695 Methods, devices and systems using over-reset state in a memory cell
Memory cells, devices and methods are disclosed, including those that involve applying a waveform to a resistive memory cell to program the memory cell to an...
US-9,613,676 Writing to cross-point non-volatile memory
Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a...
US-9,613,214 Self-measuring nonvolatile memory devices with remediation capabilities and associated systems and methods
Several embodiments of systems incorporating nonvolatile memory devices are disclosed herein. In one embodiment, a system can include a central processor (CPU)...
US-9,612,972 Apparatuses and methods for pre-fetching and write-back for a segmented cache memory
Apparatuses and methods for a cache memory are described. In an example method, a transaction history associated with a cache block is referenced, and requested...
US-9,612,954 Recovery for non-volatile memory after power loss
Non-volatile memory array can be recovered after a power loss. In one example, pages of a memory array are scanned to find a first free page after the power...
US-9,612,903 Updating reliability data with a variable node and check nodes
The present disclosure includes apparatuses and methods related to updating reliability data. A number of methods can include receiving, at a variable node,...
US-9,612,775 Solid state drive controller
A memory device may comprise circuitry to adjust between latency and throughput in transferring information through a memory port, wherein the circuitry may be...
US-9,612,750 Autonomous memory subsystem architecture
An autonomous sub-system receives a database downloaded from a host controller. A controller monitors bus traffic and/or allocated resources in the subsystem...
US-9,612,605 Voltage regulator with current feedback
Generally discussed herein are apparatuses and methods for a voltage regulator with a current feedback loop. One such apparatus may include an amplifier, a...
US-9,612,413 Method and apparatus providing a coupled photonic structure
Described embodiments include optical connections for electronic-photonic devices, such as optical waveguides and photonic detectors for receiving optical waves...
US-9,610,593 Device for positioning nanoparticles
The present invention is generally directed to a system for controlling placement of nanoparticles, and methods of using same. In one illustrative embodiment,...
US-9,609,600 Wireless communication system with enhanced power management
A method is provided for a wireless communication device containing at least a main processor for data processing, and a transmitter and a receiver for wireless...
US-9,608,630 Reference voltage circuits and on-die termination circuits, methods for updating the same, and methods for...
Devices and methods for operating devices are provided, such as those that include a memory device having a reference voltage (Vref) circuit that has...
US-9,608,197 Memory cells, methods of fabrication, and semiconductor devices
A magnetic cell includes an attracter material proximate to a magnetic region (e.g., a free region). The attracter material is formulated to have a higher...
US-9,608,185 Ohmic contacts for semiconductor structures
A composition and method for formation of ohmic contacts on a semiconductor structure are provided. The composition includes a TiAl.sub.xN.sub.y material at...
US-9,608,119 Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices...
Methods for fabricating semiconductor-metal-on-insulator (SMOI) structures include forming an acceptor wafer including an insulator material on a first...
US-9,608,000 Devices and methods including an etch stop protection material
Protective dielectrics are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory may include a protective dielectric...
US-9,607,930 Disabling electrical connections using pass-through 3D interconnects and associated systems and methods
Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are...
US-9,607,705 Apparatuses and methods for charging a global access line prior to accessing a memory
Apparatuses and methods for charging a global access line prior to accessing a memory are described. An example apparatus may include a memory array of a...
US-9,607,692 Threshold voltage distribution determination
Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to...
US-9,607,691 Memory cell architecture for multilevel cell programming
Methods, systems, and devices for operating and forming a multilevel memory cell and array are described. A multilevel memory cell includes two or more binary...
US-9,607,677 Apparatuses for resetting an address counter during refresh operations
An example apparatus includes an address counter configured to provide refresh addresses to a refresh circuit, wherein the address counter includes a plurality...
US-9,607,668 Systems, circuits, and methods for charge sharing
Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage...
US-9,607,665 Providing power availability information to memory
The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a...
US-9,606,885 Chained bus method
Memory devices and methods are described and shown that are capable of being configured in a chain. In one configuration, a single data input port and a single...
US-9,606,807 Direct communication with a processor internal to a memory device
Devices, systems, and methods of communicating information directly to a sequencer or a buffer in a memory device are provided. In some embodiments,...
US-9,602,436 Switching device
A switching device comprising a plurality of ingress ports and a plurality of egress ports. The switching device is arranged to receive data packets through...
US-9,602,080 Phase interpolators and push-pull buffers
Interpolator systems are described utilizing one or more push-pull buffers to generate output clock signals that may be provided as inputs to a phase...
US-9,601,675 Vertical solid-state transducers having backside terminals and associated systems and methods
Vertical solid-state transducers ("SSTs") having backside contacts are disclosed herein. An SST in accordance with a particular embodiment can include a...
US-9,601,658 Solid state lighting devices without converter materials and associated methods of manufacturing
Solid state lighting devices that can produce white light without a phosphor are disclosed herein. In one embodiment, a solid state lighting device includes a...
US-9,601,447 Semiconductor device including plural semiconductor chips stacked on substrate
A semiconductor chip at least includes a row of first electrode pad group, which includes at least one first independent electrode pad and multiple first common...
US-9,601,384 Method of forming a semiconductor device comprising first and second nitride layers
A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well...
US-9,601,374 Semiconductor die assembly
A semiconductor die assembly having a solderball wirebonded to a substrate. As an example, the semiconductor die assembly may include the solderball attached to...
US-9,601,183 Apparatuses and methods for controlling wordlines and sense amplifiers
Apparatuses and methods for controlling word lines and sense amplifiers in a semiconductor device are described. An example apparatus includes: a sub word line...
US-9,601,182 Frequency synthesis for memory input-output operations
A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components...
US-9,601,170 Apparatuses and methods for adjusting a delay of a command signal path
Apparatuses and methods related to adjusting a delay of a command signal path are disclosed. An example apparatus includes: a command input buffer that receives...
US-9,601,168 Memory bank signal coupling buffer and method
A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments...
US-9,601,166 Data shift by elements of a vector in memory
Examples of the present disclosure provide apparatuses and methods for performing shift operations in a memory. An example method comprises performing a shift...
US-9,600,414 Concurrent memory operations
Subject matter disclosed herein relates to performing concurrent memory operations.
US-9,600,191 Systems and methods for reordering packet transmissions in a scalable memory system protocol
A memory device includes a plurality of memory components that stores data and a processor communicatively coupled to the plurality of memory components. The...
US-9,599,844 Inspection apparatus
An inspection apparatus capable of reducing the effect of noises is provided. An inspection apparatus according to the present invention includes a work table...
US-9,595,672 Memory elements using self-aligned phase change material layers and methods of manufacturing same
A memory element and method of forming the same. The memory element includes a first electrode within a via in a first dielectric material. An insulating...
US-9,595,667 Three dimensional memory array architecture
Three dimension memory arrays and methods of forming the same are provided. An example three dimension memory array can include a stack comprising a plurality...
US-9,595,664 STT-MRAM cell structures
A magnetic cell structure including a nonmagnetic bridge, and methods of fabricating the structure are provided. The magnetic cell structure includes a free...
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