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Patent # Description
US-1,021,7569 Devices comprising a capacitor and support material that laterally supports the capacitor
A device includes a capacitor that has first and second electrodes having a capacitor insulator there-between. The first electrode is elongated and extends...
US-1,021,7525 Memory apparatus with post package repair
Apparatuses for memory repair for a memory device are described. An example apparatus includes: a non-volatile storage element that stores information; a...
US-1,021,7524 Autorecovery after manufacturing/system integration
Methods of managing systems comprising a processor and a memory device external to the processor, including exposing the memory device to temperature levels...
US-1,021,7499 Modified decode for corner turn
Examples of the present disclosure provide apparatuses and methods for performing a corner turn using a modified decode. An example apparatus can comprise an...
US-1,021,6438 Methods and related devices for operating a memory array
Methods of operating memory arrays, as well as the memory arrays, are described. In various embodiments, a method includes determining a pattern to be written...
US-1,021,6213 Methods and apparatuses including a process, voltage, and temperature independent current generator circuit
Apparatuses, methods, and current generators that generate current are described. An example apparatus includes a current source configured to provide a...
US-1,021,5921 Method and structure providing optical isolation of a waveguide on a silicon-on-insulator substrate
Disclosed are a method and structure providing a silicon-on-insulator substrate on which photonic devices are formed and in which a core material of a waveguide...
US-1,021,5801 Contact inspection device having a probe head and rotation restricting portions
A contact inspection device includes: plural probes each having a first end to be brought into contact with a test object; a probe substrate including contact...
US-1,021,5500 Semiconductor device assembly with vapor chamber
Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one...
US-1,021,1832 Input buffer circuit
An example apparatus according to an embodiment of the disclosure includes first and second voltage terminals, and first, second, and third circuit nodes. A...
US-1,021,1725 Electronic device with a charging mechanism
An electronic device includes: a clock booster including a doubler capacitor, the clock booster configured to precharge the doubler capacitor and provide a...
US-1,021,1724 Electronic device with an output voltage booster mechanism
An electronic device includes: a clock booster configured to generate a boosted intermediate voltage greater than a source voltage, wherein the clock booster...
US-1,021,1114 Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
Microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a packaged microelectronic device can include an...
US-1,021,0940 Memory read apparatus and methods
Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential,...
US-1,021,0928 Apparatuses including current compliance circuits and methods
Apparatus, devices, systems, and methods are described that include variable state material data storage. Example devices include current compliance circuits...
US-1,021,0922 Apparatus and methods for refreshing memory cells of a semiconductor device
Apparatuses and methods for refreshing memory cells of a semiconductor device are described. An example apparatus includes: a memory cell array including a...
US-1,021,0918 Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase...
Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal are disclosed. An example apparatus...
US-1,021,0911 Apparatuses and methods for performing logical operations using sensing circuitry in a memory device
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an...
US-1,020,9449 Photonics grating coupler and method of manufacture
A structure for coupling an optical signal between an integrated circuit photonic structure and an external optical fiber is disclosed as in a method of...
US-1,020,5451 Methods and apparatuses for dynamic step size for impedance calibration of a semiconductor device
Methods and apparatuses are provided for dynamic step size for impedance calibration of a semiconductor device. An example apparatus includes a resistor, and a...
US-1,020,4667 Methods of determining host clock frequency for run time optimization of memory and memory devices employing...
A memory device is provided. The memory device includes one or more memories and a connector operably coupled to the one or more memories and configured to...
US-1,020,4666 Input buffer circuit
Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes: a first amplifier that provides first and...
US-1,020,4663 Methods and apparatuses for compensating for source voltage
Apparatuses and methods for compensating for source voltage are described. An example apparatus includes a source cooled to a memory cell and a read-write...
US-1,020,3885 Memory device including mixed non-volatile memory cell types
Some embodiments include apparatuses, and methods of forming and operating the apparatuses. Some of the apparatuses include a conductive line, non-volatile...
US-1,020,2583 Arrays of memory cells individually comprising a capacitor and an elevationally-extending transistor, methods...
A method of forming a tier of an array of memory cells within an array area, the memory cells individually comprising a capacitor and an elevationally-extending...
US-1,019,9363 Semiconductor memory device including output buffer
A semiconductor module includes a module substrate, a line pattern provided to the module substrate, first and second semiconductor chips on the module...
US-1,019,9356 Semiconductor device assembles with electrically functional heat transfer structures
Semiconductor device assemblies having stacked semiconductor dies and electrically functional heat transfer structures (HTSs) are disclosed herein. In one...
US-1,019,9299 Semiconductor mold compound transfer system and associated methods
Mold compound transfer systems and methods for making mold compound transfer systems are disclosed herein. A method configured in accordance with a particular...
US-1,019,9111 Memory devices with read level calibration
Several embodiments of memory devices and systems with read level calibration are disclosed herein. In one embodiment, a memory device includes a controller...
US-1,019,9097 Apparatuses and methods for sensing a phase-change test cell and determining changes to the test cell...
A phase change memory array may include at least one cell used to determine whether the array has been altered by thermal exposure over time. The cell may be...
US-1,019,9088 Apparatuses and methods for cache invalidate
The present disclosure includes apparatuses and methods for cache invalidate. An example apparatus comprises a bit vector capable memory device and a channel...
US-1,019,9086 Semiconductor device having a reduced footprint of wires connecting a DLL circuit with an input/output buffer
An apparatus includes a clock terminal configured to receive an external clock signal, a clock generator configured to generate an internal clock signal in...
US-1,019,9081 Apparatuses and methods for providing bias signals in a semiconductor device
Apparatuses and methods for providing bias signals in a semiconductor device are described. As example apparatus includes a power supply line configured to...
US-1,019,8371 Apparatuses and methods for transferring data from memory on a data path
Apparatuses and methods for transferring data from memory on a data path are described. An example apparatus includes: one or more data terminals; a plurality...
US-1,019,8195 Wear leveling
In an example, a portion of a memory array may be selected to be wear leveled based on how often the portion is or is to be accessed. The portion may be wear...
US-1,019,8052 Systems, methods and devices for limiting current consumption upon power-up
Embodiments are described including those for controlling peak current consumption of a multi-chip memory package during power-up. In one embodiment, each...
US-1,019,3711 Timing based arbitration methods and apparatuses for calibrating impedances of a semiconductor device
Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips....
US-1,019,3577 Stopping criteria for layered iterative error correction
The present disclosure includes apparatuses and methods related to stopping criteria for layered iterative error correction. A number of methods can include...
US-1,019,3558 Clock signal and supply voltage variation tracking
Embodiments disclosed herein provide an apparatus comprising a clock generation circuit configured to generate a first signal for a first time period and a...
US-1,019,3334 Apparatuses and method for over-voltage event protection
Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. An example...
US-1,019,3064 Memory cells including dielectric materials, memory devices including the memory cells, and methods of forming same
A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold...
US-1,019,2873 Memory cell, an array of memory cells individually comprising a capacitor and a transistor with the array...
A method of forming an array of capacitors and access transistors there-above comprises forming access transistor trenches partially into insulative material....
US-1,019,2852 Interconnect structure with redundant electrical connectors and associated systems and methods
Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die...
US-1,019,2843 Methods of making semiconductor device modules with increased yield
Methods of making semiconductor device modules may involve forming holes in a sacrificial material and placing an electrically conductive material in the holes....
US-1,019,2608 Apparatuses and methods for detection refresh starvation of a memory
Apparatuses and methods for detecting refresh starvation at a memory. An example apparatus may include a plurality of memory cells, and a control circuit...
US-1,019,2606 Charge extraction from ferroelectric memory cell using sense capacitors
A ferroelectric capacitor of a memory cell may be in electronic communication with a sense capacitor through a digit line. The digit line may be virtually...
US-1,019,2605 Memory cells and semiconductor devices including ferroelectric materials
Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric...
US-1,019,2596 Apparatuses including multiple read modes and methods for same
Apparatuses and methods including multiple read modes for reading data from a memory are described. An example apparatus includes a memory including a first...
US-1,019,2591 Memory devices having special mode access
Memory devices are provided that include special operating modes accessible upon receipt of a particular message from a host. One device includes a memory...
US-1,019,1843 Unaligned data coalescing
The present disclosure includes methods and systems for coalescing unaligned data. One method includes receiving a first write command associated with a first...
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