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Patent # Description
US-9,595,334 Apparatus and methods of operating memory for exact and inexact searching of feature vectors
Apparatus and methods of operating a memory include storing a value of an attribute of a feature vector to a pair of memory cells by programming each of the...
US-9,595,303 Methods and apparatuses for compensating for source voltage
Apparatuses and methods for compensating for source voltage is described. An example apparatus includes a source coupled to a memory cell and a read-write...
US-9,594,676 Configuring and reconfiguring blocks of memory cells to store user data and ECC data
A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure a first block of memory cells in a...
US-9,593,431 Electroplating systems
Electroplating systems that include a plurality of electrodes, a power supply operably coupled to the plurality of electrodes, a platen for bearing a substrate...
US-9,593,297 Compositions for removing residues and related methods
Compositions for removing residues from a semiconductor structure. The compositions comprise water, a base, a polydentate chelator, a degasser, and a fluorine...
US-9,590,606 Semiconductor device having duty correction circuit
Disclosed herein is a device includes a duty correction circuit adjusting a duty ratio of a first clock signal based on a duty control signal to generate a...
US-9,590,066 Transistors, memory cells and semiconductor constructions
Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within...
US-9,590,014 Resistance variable memory cell structures and methods
Resistance variable memory cell structures and methods are described herein. A number of embodiments include a first resistance variable memory cell comprising...
US-9,590,012 Self-aligned cross-point phase change memory-switch array
Subject matter disclosed herein relates to a memory device, and more particularly to a self-aligned cross-point phase change memory-switch array and methods of...
US-9,589,978 Memory devices with stairs in a staircase coupled to tiers of memory cells and to pass transistors directly...
In an example, a memory device includes a staircase comprising a flight of stairs and a plurality of pass transistors directly under the staircase. The stairs...
US-9,589,962 Array of conductive vias, methods of forming a memory array, and methods of forming conductive vias
A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions...
US-9,589,933 Methods of processing wafer-level assemblies to reduce warpage, and related assemblies
Wafer-level methods of processing semiconductor devices may involve forming grooves partially through a molding material, the molding material located in...
US-9,589,659 Pre-compensation of memory threshold voltage
Methods of operating a memory include storing a first target data state of multiple possible data states of a first memory cell to be programmed in a target...
US-9,589,644 Reducing programming disturbance in memory devices
Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a...
US-9,589,618 Unidirectional spin torque transfer magnetic memory cell structure
Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices...
US-9,589,607 Apparatuses and methods for performing logical operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an...
US-9,589,602 Comparison operations in memory
The present disclosure includes apparatuses and methods related to performing comparison operations in memory. An example apparatus can include a first group of...
US-9,588,697 Host controller
The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes...
US-9,585,206 Multi-junction solid state transducer devices for direct AC power and associated systems and methods
Multi-junction solid-state transducer (SST) devices and associated systems and methods are disclosed herein. In several embodiments, for example, an SST system...
US-9,584,140 Apparatuses, methods, and circuits including a delay circuit
Apparatuses, methods, and delay circuits for delaying signals are described. An example apparatus includes a fine delay circuit configured to provide an output...
US-9,583,857 Electrical contactor and electrical connecting apparatus
An object of the present invention is to provide an electrical contactor highly resistant to deformation capable of achieving satisfactory performance of...
US-9,583,476 Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing...
A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second ...
US-9,583,419 Semiconductor constructions having through-substrate interconnects
Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor...
US-9,583,381 Methods for forming semiconductor devices and semiconductor device structures
Methods of forming semiconductor devices and features in semiconductor device structures include conducting an anti-spacer process to remove portions of a first...
US-9,583,334 Gallium lanthanide oxide films
Electronic apparatus and methods of forming the electronic apparatus include a gallium lanthanide oxide film for use in a variety of electronic systems. The...
US-9,583,195 Systems, methods and devices for a memory having a buried select line
Memory cells and methods for programming and erasing a memory cell by utilizing a buried select line are described. A voltage potential may be generated between...
US-9,583,163 Loop structure for operations in memory
Examples of the present disclosure provide apparatuses and methods related to performing a loop structure for operations performed in memory. An example...
US-9,583,160 Apparatuses including multiple read modes and methods for same
Apparatuses and methods including multiple read modes for reading data from a memory are described. An example apparatus includes a memory including a first...
US-9,583,157 Memory device power managers and methods
Memory devices and methods are described that include a stack of memory dies and an attached logic die. Method and devices described provide for power...
US-9,583,154 Methods and apparatuses including a string of memory cells having a first select transistor coupled to a second...
Generally discussed herein are apparatuses and methods. One such apparatus includes a data line, a first memory cell and a first select transistor. The first...
US-9,582,362 Setting a default read signal based on error correction
The present disclosure includes apparatuses and methods related to setting a default read signal based on error correction. A number of methods can include...
US-9,582,191 Memory block quality identification in a memory
Methods of operating electronic systems having a memory include reading indications of memory block quality from a plurality of memory blocks of the memory in...
US-9,579,825 Methods and systems for imaging and cutting semiconductor wafers and other semiconductor workpieces
Methods and systems for imaging and cutting semiconductor wafers and other microelectronic device substrates are disclosed herein. In one embodiment, a system...
US-9,578,266 Image sensor defect identification using optical flare
Embodiments described herein may operate to compare an illuminance corresponding to a signal from an image sensor array (ISA) element in a production imaging...
US-9,577,854 Apparatuses and methods for asymmetric bi-directional signaling incorporating multi-level encoding
Apparatuses and methods for asymmetric bi-directional signaling incorporating multi-level encoding are disclosed. An example apparatus may include first and...
US-9,577,673 Error correction methods and apparatuses using first and second decoders
Apparatuses and methods for error correcting data are provided. A first error correction code (ECC) decoder is configured to decode a first codeword to provide...
US-9,577,611 Controlling clock input buffers
An integrated circuit may have a clock input pin coupled to a buffer (24). The buffer may supply a clock signal (28) to an integrated circuit chip such as the...
US-9,577,188 Semiconductor constructions and methods of forming memory cells
Some embodiments include semiconductor constructions having stacks containing electrically conductive material over dielectric material. Programmable material...
US-9,577,186 Non-volatile resistive oxide memory cells and methods of forming non-volatile resistive oxide memory cells
A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. The...
US-9,577,168 Solid state lighting device with different illumination parameters at different regions of an emitter array
Solid state lighting (SSL) devices and methods of manufacturing such devices. One embodiment of an SSL device comprises a support and an emitter array having a...
US-9,577,092 Apparatuses having a vertical memory cell
Methods, apparatuses, and systems for providing a body connection to a vertical access device. The vertical access device may include a digit line extending...
US-9,577,058 Devices, systems, and methods related to removing parasitic conduction in semiconductor devices
Semiconductor devices and methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes...
US-9,577,010 Cross-point memory and methods for fabrication of same
The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same....
US-9,576,943 Apparatuses and methods of communicating differential serial signals including charge injection
Apparatuses and methods are disclosed, including an apparatus that includes a differential driver with charge injection pre-emphasis. One such apparatus...
US-9,576,904 Semiconductor devices comprising interconnect structures and methods of fabrication
Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of...
US-9,576,805 Fortification of charge-storing material in high-K dielectric environments and resulting apparatuses
Memories, systems, and methods for forming memory cells are disclosed. One such memory cell includes a charge storage node that includes nanodots over a tunnel...
US-9,576,674 Memory cell sensing
This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first memory cell coupled to a first data line,...
US-9,576,667 Apparatuses and methods for non-volatile memory programming schemes
Apparatuses and methods for a non-volatile memory scheme are described herein. An example apparatus may include a memory block including a plurality of...
US-9,576,662 Phase change memory in a dual inline memory module
Subject matter disclosed herein relates to management of a memory device.
US-9,576,659 Apparatuses and methods including memory access in cross point memory
Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch...
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