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Resistive random access memory
A resistive random access memory may include a memory array and a periphery around the memory array. Decoders in the periphery may be coupled to address lines...
Memory cells, integrated devices, and methods of forming memory cells
Some embodiments include integrated devices, such as memory cells. The devices may include chalcogenide material, an electrically conductive material over the...
Microfeature workpieces having interconnects and conductive backplanes,
and associated systems and methods
Microfeature workpieces having interconnects and conductive backplanes and associated systems and methods are disclosed herein. One such device includes a...
Repair of memory devices using volatile and non-volatile memory
Apparatus and methods for hybrid post package repair are disclosed. One such apparatus may include a package including memory cells and volatile memory. The...
Apparatuses and methods for providing set and reset voltages at the same
Apparatuses and methods are described, such as those involving driver circuits that are configured to provide reset and set voltages to different variable state...
Apparatuses and methods of reading memory cells
A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (V.sub.TH) region between a first state...
Apparatus having dice to perorm refresh operations
Some embodiments include an apparatus that comprise an interface chip having an oscillator to produce an original clock signal, a first memory chip having first...
Apparatuses and methods to delay memory commands and clock signals
An example delay circuit may include a delay block configured to receive a command signal and/or a bank address signal, a first clock signal, and a second clock...
Apparatuses and methods for shifting data during a masked write to a
Apparatuses and methods are provided that include a multiplexer configured to generate a plurality of sums of a plurality of data words, wherein the plurality...
Device having multiple switching buffers for data paths controlled based
on IO configuration modes
A device includes a first data terminal, a second data terminal, a first switching buffer coupled between a data node and the first data terminal and a second...
Self-measuring nonvolatile memory device systems and methods
One embodiment describes a computing system that includes a boot device. The boot device includes nonvolatile memory that stores startup routine instructions...
Controller to manage NAND memories
Various embodiments disclose a controller to manage memory devices. In an exemplary method, signals are exchanged with a host processor to allow the host...
Photonic device structure and method of manufacture
Disclosed method and apparatus embodiments provide a photonic device with optical isolation from a supporting substrate. A generally rectangular cavity in cross...
Electrical test probe
An electrical test probe according to an embodiment includes a probe main body portion having a connection end to a circuit of a probe base plate and made of a...
Apparatuses including scalable drivers and methods
Apparatuses and methods are described that include a plurality of drivers corresponding to a single via. A number of drivers can be selected to operate...
Multi-bit ferroelectric memory device and methods of forming the same
Multi-bit ferroelectric memory devices and methods of forming the same are provided. One example method of forming a multi-bit ferroelectric memory device can...
Stack of horizontally extending and vertically overlapping features,
methods of forming circuitry components,...
A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion...
Methods of forming contacts for a semiconductor device structure, and
related methods of forming a...
A method of forming contacts for a semiconductor device structure comprises forming contact holes extending into neighboring semiconductive pillars and into a...
Interconnect structures with intermetallic palladium joints and associated
systems and methods
Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes...
Memory device having a different source line coupled to each of a
plurality of layers of memory cell arrays
A sensing voltage may be applied to a particular memory cell that is in a particular layer of a plurality of layers of memory cells. While the sensing voltage...
Command signal management in integrated circuit devices
Methods of operating integrated circuit devices include logically combining an output signal indicating whether an operation is being performed with the logic...
Apparatuses and methods for providing data from a buffer
Apparatuses and methods for providing data from a buffer are disclosed herein. An example apparatus may include an array, a buffer, and a memory control unit....
Persistent content in nonvolatile memory
Applications may request persistent storage in nonvolatile memory. The persistent storage is maintained across power events and application instantiations....
Preserving data integrity in a memory system
A method includes detecting that a first device in a memory array has degraded, the first device storing a portion of a data record, wherein the data record is...
Semiconductor device including oscillator
According to the present invention, a ring oscillator coupled to an output node operable to output a clock signal including a first logic level generated by a...
Methods of forming memory device constructions, methods of forming memory
cells, and methods of forming...
Memory device constructions include a first column line extending parallel to a second column line, the first column line being above the second column line; a...
Semiconductor memory device and method for biasing same
Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory...
Vertical memory devices, memory arrays, and memory devices
Vertical memory devices comprise vertical transistors in an array region and digit lines extending in a first direction and comprising a source region or a...
Transistors and methods of forming transistors
Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. First channel...
The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom...
Vertical ferroelectric field effect transistor constructions,
constructions comprising a pair of vertical...
A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating...
Memory including blocking dielectric in etch stop tier
Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to...
Techniques for packaging multiple device components
Techniques for fabricating multiple device components. Specifically, techniques for fabricating a stacked package comprising at least one I/C module and a...
Semiconductor device with modified current distribution
Semiconductor devices having modified current distribution and methods of forming the same are described herein. As an example, a memory die in contact with a...
Integrated circuit device packages and methods for manufacturing
integrated circuit device packages
An integrated circuit device package may include a flexible substrate having a first wiring, an integrated circuit device having a second wiring, a flexible...
Soft post package repair of memory devices
Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store...
Identifying stacked dice
Various embodiments comprise apparatuses to assign unique device identifier values to addressable devices in a stacked package. In one embodiment, an apparatus...
Non-volatile memory programming
Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying voltages to data lines...
Fixed voltage sensing in a memory device
Methods for sensing ferroelectric memory devices and apparatuses using the same have been disclosed. One such apparatus includes a ferroelectric memory cell...
Timing violation handling in a synchronous interface memory
A memory device includes an operation having a phase to provide an upper row address from a row address buffer, a phase to combine the upper row address with a...
Interconnect systems and methods using hybrid memory cube links to send
packetized data over different...
System on a Chip (SoC) devices include two packetized memory buses for conveying local memory packets and system interconnect packets. In an in-situ...
Estimating an error rate associated with memory
The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored...
Semiconductor device and error correction method
A device is provided with: memory cell array including plurality of first and second memory cells and one or more third memory cells; judging circuit that...
Integrity of an address bus
A memory device has a controller, an address integrity feature, and an address register. The controller is configured to store error correction data in the...
Sequence power control
The present disclosure includes apparatuses and methods for sequence power control. A number of embodiments include executing a number of sequences associated...
Apparatuses and methods for die seal crack detection
Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around...
Disposed is a jet mill that has a cylindrical pulverization chamber (10) and a classification chamber (6) that connects to the pulverization chamber (10). A...
Method and apparatus providing pixel storage gate charge sensing for
electronic stabilization in imagers
An imaging device that stores charge from a photosensor under at least one storage gate. A driver used to operate the at least one storage gate, senses how much...
Memory cells and semiconductor structures including electrodes comprising
a metal, and related methods
Memory cells (e.g., CBRAM cells) include an ion source material over an active material and an electrode comprising metal silicide over the ion source material....
Resistive memory elements including buffer materials, and related memory
cells, memory devices, electronic systems
A resistive memory element comprises a first electrode, an active material over the first electrode, a buffer material over the active material and comprising...