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Patent # Description
US-9,767,904 Memory with three transistor memory cell device
Memory, memory devices, and a method for a backup sequence are disclosed. In one such memory device, sense circuitry and page buffers are coupled between a...
US-9,767,898 Memory device with reduced neighbor memory cell disturbance
In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes a memory cell, digit line driver, access line driver, clamping...
US-9,767,896 Apparatuses and methods for accessing memory cells in semiconductor memories
Apparatuses and methods for accessing a memory cell are described. An example apparatus includes a first voltage circuit coupled to a node and is configured to...
US-9,767,894 Programming memories with stepped programming pulses
Memories and methods for programming memories with multi-step programming pulses are provided. One method includes applying a plurality of programming pulses to...
US-9,767,886 Memory command received within two clock cycles
A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit...
US-9,767,880 Ferroelectric memory cell apparatuses and methods of operating ferroelectric memory cells
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a...
US-9,767,865 Apparatuses and methods for performing compare operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can...
US-9,767,864 Apparatuses and methods for storing a data value in a sensing circuitry element
The present disclosure includes apparatuses and methods related to storing a data value in a sensing circuitry element. An example method comprises sensing a...
US-9,767,860 Interconnection for memory electrodes
Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central...
US-9,767,857 Apparatus and methods to perform read-while write (RWW) operations
Subject matter disclosed herein relates to methods and apparatus, such as memory devices and systems including such memory devices. In one apparatus example, a...
US-9,767,721 Inspection apparatus and inspection method
An inspection apparatus and an inspection method capable of reducing the effect of noises are provided. An inspection apparatus according to the present...
US-9,767,012 Systems and methods for memory system management based on thermal information of a memory system
Methods of mapping memory regions to processes based on thermal data of memory regions are described. In some embodiments, a memory controller may receive a...
US-9,766,837 Stripe mapping in memory
Examples of the present disclosure provide apparatuses and methods related to redundant array of independent disks (RAID) stripe mapping in memory. An example...
US-9,766,831 Apparatuses and methods for arbitrating a shared terminal for calibration of an impedance termination
An arbitration system and method is disclosed. The apparatus includes a first and a second memory devices, and a resistor coupled in common to the first and...
US-9,766,830 Power consumption control
The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information...
US-9,762,247 Apparatuses with an embedded combination logic circuit for high speed operations
Apparatuses for performing combination logic operations with an combination logic circuit are disclosed. According to one embodiment, the apparatus comprises a...
US-9,762,215 Apparatuses and methods for voltage buffering
An apparatuses and methods for buffering a voltage from a circuit without current drive ability are described. An example apparatus includes a voltage buffer...
US-9,761,797 Methods of forming structures
Some embodiments include methods of forming structures. Spaced-apart features are formed which contain temperature-sensitive material. Liners are formed along...
US-9,761,715 Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row...
A ferroelectric field effect transistor comprises a semiconductive channel comprising opposing sidewalls and an elevationally outermost top. A source/drain...
US-9,761,621 Color filter array, imagers and systems having same, and methods of fabrication and use thereof
A pixel cell with a photosensitive region formed in association with a substrate, a color filter formed over the photosensitive region, the color filter...
US-9,761,599 Integrated structures containing vertically-stacked memory cells
Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory...
US-9,761,590 Passing access line structure in a memory device
A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The...
US-9,761,580 Methods of forming an array comprising pairs of vertically opposed capacitors and arrays comprising pairs of...
A method of forming an array comprising pairs of vertically opposed capacitors comprises forming an upwardly-open conductive lining in individual capacitor...
US-9,761,564 Layout of transmission vias for memory device
Apparatuses and methods for supplying power to a plurality of dies are described. An example apparatus includes: a substrate; first, second and third memory...
US-9,761,562 Semiconductor device packages including a controller element
Semiconductor device packages include a stack of semiconductor memory devices positioned over an interposer substrate, a controller element, and a...
US-9,761,559 Semiconductor package and fabrication method thereof
A semiconductor package includes a first logic die, a second logic die disposed in close proximity to the first logic die, a bridge memory die coupled to both...
US-9,761,540 Wafer level package and fabrication method thereof
A semiconductor device that includes a redistribution layer (RDL) is disclosed. A chip is mounted on the RDL within a chip mounting area. The RDL is...
US-9,761,474 Methods for processing semiconductor devices
Methods of forming semiconductor structures include providing a polymeric material over a carrier substrate, bonding another substrate to the polymeric...
US-9,761,457 Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device...
A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be...
US-9,761,322 Program operations with embedded leak checks
Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power...
US-9,761,312 FeRAM-DRAM hybrid memory
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. One method includes determining whether to access a first memory...
US-9,761,300 Data shift apparatuses and methods
The present disclosure includes data shift apparatuses and methods. An example apparatus includes a memory device. The example memory device includes an array...
US-9,760,446 Conveying value of implementing an integrated data management and protection system
A system and method are described for conveying to a user the value it would receive by implementing an integrated system to protect and manage its data. An...
US-9,760,436 Data storage error protection
Apparatuses and methods for data storage error protection are described. One example apparatus for data storage error protection includes an array of memory...
US-9,759,744 Contact inspection device
A contact inspection device including contacts that contact with a test object for inspection, each contact having a base end portion, a needle tip portion...
US-9,757,571 Remote control of power or polarity selection for a neural stimulator
A system, including: an implantable neural stimulator including electrodes, at least one antenna and an electrode interface; a radio-frequency (RF) pulse...
US-9,756,269 Pixel array with shared pixels in a single column and associated devices, systems, and methods
Pixel array with shared pixels in a single column and associated devices, systems, and methods are disclosed herein. In one embodiment, a pixel array includes a...
US-9,754,953 Charge storage apparatus and methods
Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is...
US-9,754,643 Asynchronous/synchronous interface
The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling...
US-9,748,959 Circuits, apparatuses, and methods for frequency division
Circuits, apparatuses, and methods are disclosed for frequency division. In one such example circuit, a frequency divider is configured to alternate between...
US-9,748,632 Radio frequency identification (RFID) tag(s) and sensor(s)
A wireless sensor includes an antenna, a sensing element, a tuning circuit, a processing module, a reference circuit block, and a transmitter. The tuning...
US-9,748,596 Single layer secondary battery having a folded structure
Provided is a secondary battery adopting an all-solid-state secondary cell structure with a storage layer sandwiched between a positive electrode layer and a...
US-9,748,480 Semiconductor constructions and memory arrays
Some embodiments include semiconductor constructions having an electrically conductive interconnect with an upper surface, and having an electrically conductive...
US-9,748,474 Nano-scale electrical contacts, memory devices including nano-scale electrical contacts, and related structures...
Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the...
US-9,748,461 Light emitting diodes with enhanced thermal sinking and associated methods of operation
Solid state lighting devices and associated methods of thermal sinking are described below. In one embodiment, a light emitting diode (LED) device includes a...
US-9,748,442 Light emitting diodes and associated methods of manufacturing
Light emitting diodes and associated methods of manufacturing are disclosed herein. In one embodiment, a light emitting diode (LED) includes a substrate, a...
US-9,748,311 Cross-point memory and methods for fabrication of same
A cross-point memory array includes a plurality of variable resistance memory cell pillars. Adjacent memory cell pillars are separated by a partially filled gap...
US-9,748,265 Integrated structures comprising charge-storage regions along outer portions of vertically-extending channel...
Some embodiments include an integrated structure having stacked conductive levels. At least some of the conductive levels are wordline levels and include...
US-9,748,204 Semiconductor device including semiconductor chips stacked over substrate
According to the present invention, a semiconductor device includes a substrate including a first surface and a second surface opposite to the first surface, a...
US-9,748,184 Wafer level package with TSV-less interposer
A semiconductor device includes an interposer having a first side and a second side opposite to the first side; a first semiconductor die mounted on the first...
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