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Patent # Description
US-9,292,383 Multilevel encoding with error correction
Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, a...
US-9,292,382 Codewords that span pages of memory
The present disclosure includes apparatuses and methods for codewords that span pages of memory. A number of methods include writing a first portion of a...
US-9,291,907 Methods for forming resist features and arrays of aligned, elongate resist features
Methods of forming resist features, resist patterns, and arrays of aligned, elongate resist features are disclosed. The methods include addition of a compound,...
US-9,290,857 Methods and apparatus for sorting and/or depositing nanotubes
Methods and apparatus for forming devices using nanotubes. In one embodiment, an apparatus for depositing nanotubes onto a workpiece comprises a vessel...
US-9,287,859 Flexible input/output transceiver
An I/O transceiver includes a driver with a feedback circuit having a mode select signal input, a serial data signal input, and a driver output signal input....
US-9,287,502 Resistance variable memory cell structures and methods
Resistance variable memory cell structures and methods are described herein. One or more resistance variable memory cell structures include a first electrode...
US-9,287,500 Memory cells and methods of forming memory cells
Some embodiments include a memory cell having an electrode and a switching material over the electrode. The electrode is a first composition which includes a...
US-9,287,452 Solid state lighting devices with dielectric insulation and methods of manufacturing
Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a first...
US-9,287,379 Memory arrays
Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and...
US-9,287,284 Semiconductor field-effect transistor, memory cell and memory device
Semiconductor device formed by a first conductive strip of semiconductor material; a control gate region of semiconductor material, facing a channel portion of...
US-9,287,275 Semiconductor constructions
Some embodiments include methods of forming flash memory cells and semiconductor constructions, and some embodiments include semiconductor constructions. Some...
US-9,287,271 Vertical transistor devices, memory arrays, and methods of forming vertical transistor devices
A vertical transistor device includes a line of active area adjacent a line of dielectric isolation. A buried data/sense line obliquely angles relative to the...
US-9,287,260 Transistors having one or more dummy lines with different collective widths coupled thereto
In an embodiment, an array of transistors has a first line coupled to a first transistor. The first line extends over a second transistor that is successively...
US-9,287,240 Stacked semiconductor die assemblies with thermal spacers and associated systems and methods
Stacked semiconductor die assemblies with thermal spacers and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die...
US-9,287,207 Methods for forming conductive vias in semiconductor device components
A method for forming conductive vias in a substrate of a semiconductor device component includes forming one or more holes, or apertures or cavities, in the...
US-9,287,184 Apparatuses and methods for die seal crack detection
Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around...
US-9,286,977 Semiconductor device
A semiconductor device including: a resistive memory element; a data line electrically coupled to the resistive memory element; a control line; a power supply...
US-9,286,161 Memory system and method using partial ECC to achieve low power refresh and fast access to data
A DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first...
US-9,281,682 Apparatuses and method for over-voltage event protection
Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. An example...
US-9,281,478 Phase change memory cell with constriction structure
Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly...
US-9,281,471 Phase change memory stack with treated sidewalls
Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line...
US-9,281,466 Memory cells, semiconductor structures, semiconductor devices, and methods of fabrication
A magnetic cell includes a magnetic region formed from a precursor magnetic material comprising a diffusive species and at least one other species. An amorphous...
US-9,281,402 Methods of fabricating fin structures
There is provided fin methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may include two...
US-9,281,309 Cross-hair cell wordline formation
Methods and devices depicting fabrication of non-planar access devices having fins and narrow trenches, among which is a method that includes wet etching a...
US-9,281,241 Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using...
Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods are disclosed herein. One embodiment,...
US-9,281,078 Program operations with embedded leak checks
Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power...
US-9,281,073 Methods of operating a memory device having a buried boosting plate
Memory devices are disclosed, such as those that include a semiconductor-on-insulator (SOI) NAND memory array having a boosting plate. The boosting plate may be...
US-9,281,066 Dynamically configurable MLC state assignment
Memory devices facilitating a data conditioning scheme for multilevel memory cells. For example, one such memory device is capable of inverting the lower page...
US-9,281,064 Fast programming memory device
In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one...
US-9,281,062 Systems, and devices, and methods for programming a resistive memory cell
Embodiments disclosed herein may relate to programming a memory cell with a programming pulse that comprises a quenching period having different portions.
US-9,281,061 Methods and apparatuses having a voltage generator with an adjustable voltage drop for representing a voltage...
Apparatus and methods utilize a replica circuit to generate a voltage for programming of a memory cell, such as a memory cell of a phase-change memory (PCM)....
US-9,281,044 Apparatuses having a ferroelectric field-effect transistor memory array and related method
An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates...
US-9,281,037 Memory device command decoding system and memory device and processor-based system using same
Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding...
US-9,280,456 Mapping between program states and data patterns
The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes mapping a data pattern to a...
US-9,280,329 Methods and systems for detection in a state machine
A device including a data analysis element including a plurality of memory cells. The memory cells analyze at least a portion of a data stream and output a...
US-9,276,568 Reference voltage generator for single-ended communication systems
A reference voltage (V.sub.ref) generator for a single-ended receiver in a communication system is disclosed. The V.sub.ref generator in one example comprises a...
US-9,276,207 Method, system, and device for heating a phase change memory cell
A memory device, comprising: a phase change material; and an electrode configured to heat the phase change material to change a state of the phase change...
US-9,276,134 Field effect transistor constructions and memory arrays
In some embodiments, a transistor includes a stack having a bottom source/drain region, a first insulative material, a conductive gate, a second insulative...
US-9,276,092 Transistors and methods of forming transistors
Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. First channel...
US-9,276,081 Methods of forming diodes
Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is...
US-9,276,059 Semiconductor device structures including metal oxide structures
Methods of forming metal oxide structures and methods of forming metal oxide patterns on a substrate using a block copolymer system formulated for...
US-9,276,011 Cell pillar structures and integrated flows
Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a...
US-9,276,000 Manufacturing process for zero-capacitor random access memory circuits
Embodiments of a manufacturing process flow for producing standalone memory devices that can achieve bit cell sizes on the order of 4F2 or 5F2, and that can be...
US-9,275,909 Methods of fabricating semiconductor structures
Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control...
US-9,275,871 Nanostructures having low defect density and methods of forming thereof
A method of forming nanostructure comprises forming self-assembled nucleic acids on at least a portion of a substrate. The method further comprises contacting...
US-9,275,730 Apparatuses and methods of reading memory cells based on response to a test pulse
The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to memory arrays and methods of...
US-9,275,728 Memory cells, non-volatile memory arrays, methods of operating memory cells, methods of writing to and writing...
In one aspect, a method of operating a memory cell includes using different electrodes to change a programmed state of the memory cell than are used to read the...
US-9,275,708 Row address decoding block for non-volatile memories and methods for decoding pre-decoded address information
Decoding blocks, memories, and methods for decoding pre-decoded address information are disclosed. One such decoding block includes a first latch and voltage...
US-9,275,701 Apparatuses and methods for performing logical operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an...
US-9,275,698 Memory system and method using stacked memory device dice, and system using the memory system
A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that...
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