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Patent # Description
US-9,257,430 Semiconductor construction forming methods
Memory device constructions include a first column line extending parallel to a second column line, the first column line being above the second column line; a...
US-9,257,294 Methods and apparatuses for energetic neutral flux generation for processing a substrate
Apparatuses and methods for processing substrates are disclosed. A processing apparatus includes a chamber for generating a plasma therein, an electrode...
US-9,257,256 Templates including self-assembled block copolymer films
Methods for fabricating sublithographic, nanoscale microstructures arrays including openings and linear microchannels utilizing self-assembling block...
US-9,257,203 Setting a default read signal based on error correction
Apparatuses and methods related to setting a default read signal based on error correction include reading a page of data from a group of memory cells with a...
US-9,257,197 Apparatuses and/or methods for operating a memory cell as an anti-fuse
Embodiments disclosed herein relate to operating a memory cell as an anti-fuse, such as for use in phase change memory, for example.
US-9,257,182 Memory devices and their operation having trim registers associated with access operation commands
Methods, and apparatus configured to perform methods, including loading trim settings into a trim register of a memory device associated with a command for an...
US-9,257,180 Random telegraph signal noise reduction scheme for semiconductor memories
Embodiments are provided that include a method including providing a first pulsed gate signal to a selected memory cell, wherein the pulsed gate signal...
US-9,257,155 Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or...
A method of generating a voltage as well as an integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i)...
US-9,257,154 Methods and apparatuses for compensating for source voltage
Apparatuses and methods for compensating for source voltage is described. An example apparatus includes a source coupled to a memory cell and a read-write...
US-9,257,136 Magnetic tunnel junctions
A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material. A conductive second magnetic electrode is...
US-9,256,577 Apparatuses and related methods for overflow detection and clamping with parallel operand processing
A method and apparatus for overflow detection and clamping with parallel operand processing for fixed-point multipliers is disclosed. The disclosure predicts...
US-9,255,964 Electronic apparatus having IC temperature control
The use of a power sink function in IC testing results in a simple and rapid method for testing ICs, and assembled modules, at elevated temperature profiles...
US-9,254,393 Wearable antenna assembly
A wearable device for facilitating neurophysiological treatment of a patient harboring an implanted neural stimulator is provided. The wearable device includes...
US-9,252,996 Apparatuses and methods to change information values
Some embodiments include apparatuses and methods having a component to change a value of a bit among a number of M bits of information when the M bits have the...
US-9,252,709 Apparatuses and methods for providing oscillation signals
Apparatuses and methods are disclosed for oscillators that are substantially insensitive to supply voltage variations. In one such example apparatus, a...
US-9,252,362 Method for making three dimensional memory array architecture using phase change and ovonic switching materials
Three dimension memory arrays and methods of forming the same are provided. An example three dimension memory array can include a stack comprising a plurality...
US-9,252,281 Silicon on germanium
A monolayer or partial monolayer sequencing processing, such as atomic layer deposition (ALD), can be used to form a semiconductor structure of a silicon film...
US-9,252,188 Methods of forming memory cells
Some embodiments include methods of forming memory cells. A series of rails is formed to include bottom electrode contact material. Sacrificial material is...
US-9,252,176 Ambient infrared detection in solid state sensors
A solid state imaging device includes an array of active pixels and an infrared cut filter formed over the sensor. Optionally, a slot in the infrared cut filter...
US-9,252,148 Methods and apparatuses with vertical strings of memory cells and support circuitry
Apparatuses and methods have been disclosed. One such apparatus includes strings of memory cells formed on a topside of a substrate. Support circuitry is formed...
US-9,251,908 Memory kink checking
This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a...
US-9,251,907 Memory devices and methods of operating memory devices including applying a potential to a source and a select...
Devices, systems and methods of biasing in memory devices facilitate memory device programming and/or erase operations. In at least one embodiment, a first...
US-9,251,897 Methods for a phase-change memory array
Methods of operating phase-change memory arrays are described. A method includes determining a pattern to be written to a phase-change memory array and...
US-9,251,867 Voltage generators having reduced or eliminated cross current
Embodiments described include voltage generators having reduced or eliminated cross current. Dynamic adjustment of a low or high threshold voltage used in a...
US-9,251,860 Memory devices with local and global devices at substantially the same level above stacked tiers of memory...
In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a...
US-9,251,068 Systems, devices, memory controllers, and methods for memory initialization
Systems, devices, memory controllers, and methods for initializing memory are described. Initializing memory can include configuring memory devices in parallel....
US-9,251,000 Apparatuses and methods for combining error coding and modulation schemes
Methods and apparatuses for combining error coding and modulation schemes are described herein. One or more methods include encoding data using linear error...
US-9,249,498 Forming memory using high power impulse magnetron sputtering
Forming memory using high power impulse magnetron sputtering is described herein. One or more method embodiments include forming a resistive memory material on...
US-9,246,382 Charge pump including supply voltage-based control signal level
Some embodiments include apparatuses and methods having an input node to receive a first voltage, an output node to provide an output voltage, and a charge pump...
US-9,246,100 Memory cell array structures and methods of forming the same
The present disclosure includes memory cell array structures and methods of forming the same. One such array includes a stack structure comprising a memory cell...
US-9,246,093 Phase change memory cell with self-aligned vertical heater and low resistivity interface
A low resistivity interface material is provided between a self-aligned vertical heater element and a contact region of a selection device. A phase change...
US-9,246,051 Solid state lighting devices with reduced crystal lattice dislocations and associated methods of manufacturing
Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a substrate...
US-9,245,987 Semiconductor devices and fabrication methods
Methods of fabricating vertical devices are described, along with apparatuses and systems that include them. In one such method, a vertical device is formed at...
US-9,245,964 Integrated circuitry comprising nonvolatile memory cells and methods of forming a nonvolatile memory cell
An integrated circuit has a nonvolatile memory cell that includes a first electrode, a second electrode, and an ion conductive material there-between. At least...
US-9,245,927 Semiconductor constructions, memory cells and memory arrays
Some embodiments include a construction having oxygen-sensitive structures directly over spaced-apart nodes. Each oxygen-sensitive structure includes an angled...
US-9,245,926 Apparatuses and methods including memory access in cross point memory
Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch...
US-9,245,923 Method of fabricating a semiconductor device having a colossal magneto-capacitive material being formed close...
Semiconductor devices include a transistor having a gate structure located close to a channel region that comprises a colossal magnetocapacitive material. The...
US-9,245,893 Semiconductor constructions having grooves dividing active regions
Some embodiments include semiconductor constructions having an active region surrounded by insulating material. A groove crosses the active region to divide the...
US-9,245,646 Program verify operation in a memory device
Methods for program verifying a memory cell include generating an access line voltage in response to a count and applying the access line voltage to a control...
US-9,245,620 Drift acceleration in resistance variable memory
The present disclosure includes apparatuses and methods including drift acceleration in resistance variable memory. A number of embodiments include applying a...
US-9,245,598 Circuitry and methods minimizing output switching noise through split-level signaling and bus division enabled...
Disclosed herein are circuitry and methods for transmitting data across a parallel bus using both high common mode and low common mode signaling. The...
US-9,245,597 Reference voltage generators and sensing circuits
Described examples include sensing circuits and reference voltage generators for providing a reference voltage to a sensing circuit. The sensing circuits may...
US-9,244,479 Current generator circuit and methods for providing an output current
Current circuits, circuits configured to provide a bias voltage, and methods for providing a bias voltage are described, including a current circuit configured...
US-9,244,477 Reference voltage generation for single-ended communication channels
An improved reference voltage (Vref) generator useable, for example, in sensing data on single-ended channels is disclosed. The Vref generator can be placed on...
US-9,242,103 Relay module for implant
An implementation provides a system that includes: a control module including a first antenna, the control module configured to generate a first radio frequency...
US-9,240,548 Memory arrays and methods of forming an array of memory cells
A method of forming an array of memory cells includes forming lines of covering material that are elevationally over and along lines of spaced sense line...
US-9,240,547 Magnetic tunnel junctions and methods of forming magnetic tunnel junctions
A method of forming a line of magnetic tunnel junctions includes forming magnetic recording material over a substrate, non-magnetic material over the recording...
US-9,240,496 Semiconductor device with floating gate and electrically floating body
Techniques for providing floating body memory devices are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor...
US-9,240,495 Methods of forming nanoscale floating gate
A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first...
US-9,240,477 Transistor-containing constructions and memory arrays
Some embodiments include transistor-containing constructions having gate material within an opening in a semiconductor material and spaced from the...
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