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Patent # Description
US-9,275,692 Memory, memory controllers, and methods for dynamically switching a data masking/data bus inversion input
Examples are described herein of dynamic switching of data masking and data bus inversion functionality of a memory input. Both dynamic switching and a static...
US-9,275,290 Methods and systems for routing in a state machine
A device includes a routing buffer. The routing buffer includes a first port configured to receive a signal relating to an analysis of at least a portion of a...
US-9,274,991 Memory hub architecture having programmable lane widths
A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input...
US-9,274,973 Memory address translation
The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller...
US-9,274,883 Apparatuses and methods for storing validity masks and operating apparatuses
Apparatuses and methods for storing a validity mask and operating apparatuses are described. A number of methods for operating an apparatus include storing a...
US-9,274,272 Photonic device and methods of formation
A photonic device and methods of formation that provide an area providing reduced optical coupling between a substrate and an inner core of the photonic device...
US-9,271,403 Semiconductor assemblies with multi-level substrates and associated methods of manufacturing
Various embodiments of semiconductor assemblies with multi-level substrates and associated methods of manufacturing are described below. In one embodiment, a...
US-9,271,393 Multilayer wiring base plate and probe card using the same
A multilayer wiring base plate includes an insulating plate including a plurality of synthetic resin layers made of an insulating material, a wiring circuit...
US-9,270,506 Methods for bypassing faulty connections
Apparatus are disclosed, such as those involving a 3-D integrated circuit. One such apparatus includes a first die including a plurality of vertical connectors...
US-9,269,900 Methods of depositing phase change materials and methods of forming memory
A method of forming a phase change material which having germanium and tellurium therein includes depositing a germanium-containing material over a substrate....
US-9,269,899 Electronic device, memory cell, and method of flowing electric current
An electronic device includes two conductive electrodes. A first current path extends from one of the electrodes to the other and has a dominant thermally...
US-9,269,888 Memory cells, methods of fabrication, and semiconductor devices
A magnetic cell includes a magnetic tunnel junction that comprises magnetic and nonmagnetic materials exhibiting hexagonal crystal structures. The hexagonal...
US-9,269,858 Engineered substrates for semiconductor devices and associated systems and methods
Engineered substrates for semiconductor devices are disclosed herein. A device in accordance with a particular embodiment includes a transducer structure having...
US-9,269,795 Circuit structures, memory circuitry, and methods
A circuit structure includes a substrate having an array region and a peripheral region. The substrate in the array and peripheral regions includes insulator...
US-9,269,747 Self-aligned interconnection for integrated circuits
Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one...
US-9,269,716 Method of manufacturing semiconductor device having embedded conductive line
Disclosed herein is a method includes: forming first and second cavities, the first cavity having a first width, each of the second cavities having a second...
US-9,269,700 Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods
Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods are disclosed herein. In one embodiment, a...
US-9,269,695 Semiconductor device assemblies including face-to-face semiconductor dice and related methods
Methods of manufacturing semiconductor device assemblies include attaching a back side of a first semiconductor die to a substrate and structurally and...
US-9,269,646 Semiconductor die assemblies with enhanced thermal management and semiconductor devices including same
A semiconductor die assembly comprises a plurality of semiconductor dice in a stack. Another semiconductor die is adjacent to the stack and has a region, which...
US-9,269,586 Selective metal deposition over dielectric layers
Selective deposition of metal over dielectric layers in a manner that minimizes or eliminates keyhole formation is provided. According to one embodiment, a...
US-9,269,452 Determining system lifetime characteristics
Methods and systems for determining system lifetime characteristics are described. A number of embodiments include a number of memory devices and a controller...
US-9,269,450 Methods, devices, and systems for adjusting sensing voltages in devices
The present disclosure includes methods, devices, and systems for adjusting sensing voltages in devices. One or more embodiments include memory cells, and a...
US-9,269,432 Memory systems and memory programming methods
Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a memory array comprising a plurality of...
US-9,269,431 Configurable reference current generation for non volatile memory
This disclosure relates to generating a reference current for a memory device. In one aspect, a non-volatile memory device, such as a phase change memory...
US-9,269,410 Leakage measurement systems
Described examples include leakage measurement systems and methods for measuring leakage current between a word line at a boosted voltage and a word line at a...
US-9,269,403 Independent control of stacked electronic modules
Various embodiments of apparatuses are disclosed to allow independent control of stacked modules. In one embodiment, an apparatus may include a plurality of...
US-9,268,690 Circuits and methods for providing data to and from arrays of memory cells
A memory device uses a global input/output line or a pair of complementary global input/output lines to couple write data signals and read data signals to and...
US-9,268,629 Dual mapping between program states and data patterns
The present disclosure includes methods and apparatuses for dual mapping between program states and data patterns. One apparatus includes a memory and a...
US-9,268,210 Double-exposure mask structure and photolithography method thereof
Double-exposure mask structure and photolithography method for performing a photolithography process on a substrate are provided. The substrate has a central...
US-9,267,980 Capacitance evaluation apparatuses and methods
Apparatus and methods for evaluating leakage currents of capacitances are described. Capacitances having excessive leakage currents may be disabled from use. An...
US-9,264,068 Deflate compression algorithm
A compression algorithm replaces duplicative strings with a copy pair indicating a location and length of a preceding identical string that is within a window...
US-9,264,050 Apparatuses and methods for delaying signals using a delay line with homogenous architecture and integrated...
Apparatuses and methods for delaying signals using a delay line are described. An example apparatus includes a controller configured to in a first mode, set a...
US-9,263,675 Switching components and memory units
Some embodiments include a switching component which includes a selector region between a pair of electrodes. The selector region contains silicon doped with...
US-9,263,674 ETCH bias homogenization
Methods and memory devices formed using etch bias homogenization are provided. One example method of forming a memory device using etch bias homogenization...
US-9,263,672 Transistors, memory cells and semiconductor constructions
Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within...
US-9,263,577 Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row...
A ferroelectric field effect transistor comprises a semiconductive channel comprising opposing sidewalls and an elevationally outermost top. A source/drain...
US-9,263,461 Apparatuses including memory arrays with source contacts adjacent edges of sources
Various apparatuses, including three-dimensional (3D) memory devices and systems including the same, are described herein. In one embodiment, a 3D memory device...
US-9,263,460 Methods and apparatuses including a select transistor having a body region including monocrystalline...
Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatuses and a select...
US-9,263,455 Methods of forming an array of conductive lines and methods of forming an array of recessed access gate lines
An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material...
US-9,263,341 Methods of forming transistors
Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with...
US-9,263,133 Techniques for providing a semiconductor memory device
Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory...
US-9,263,130 Memory device page buffer configuration and methods
Memory devices and methods are described that include communication circuitry between page buffers in a memory array. Examples include communication circuitry...
US-9,263,128 Methods and apparatuses for programming memory cells
Methods and apparatus for programming memory cells in a memory array are disclosed. A most recent programming time is determined, the most recent programming...
US-9,263,115 Semiconductor device
A method includes measuring a first pulse width of a resistance variable memory cell coupled between a first terminal and a second terminal, the first pulse...
US-9,263,111 Sub-block disabling in 3D memory
Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of...
US-9,263,104 Semiconductor device
Disclosed herein is an apparatus that includes: a first terminal configured to receive a serial write data signal that includes at least four bits transferred...
US-9,263,095 Memory having buried digit lines and methods of making the same
A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a...
US-9,262,335 Re-building mapping information for memory devices
Memory modules and methods of operating memory modules re-build mapping information from data read from last valid physical pages. Corruption of mapping...
US-9,262,317 Non-volatile configuration for serial non-volatile memory
Example embodiments for configuring a serial non-volatile memory device may comprise a non-volatile configuration register to store a configuration value...
US-9,262,261 Memory devices facilitating differing depths of error detection and/or error correction coverage
Memory devices facilitating differing depths of error detection and/or error correction coverage for differing portions of a memory array.
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