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Patent # Description
US-9,431,890 Apparatuses and methods for converting single input voltage regulators to dual input voltage regulators
Apparatuses and methods for providing output power are disclosed. In an example method, a control signal is received at an output stage. The control signal may...
US-9,431,606 Memory cells
Some embodiments include a memory cell having a pair of electrodes, and a plurality of switching levels between the electrodes. Each switching level has an ion...
US-9,431,605 Methods of forming semiconductor device structures
A method of forming a semiconductor device structure. The method comprises forming a block copolymer assembly comprising at least two different domains over an...
US-9,431,493 Methods of forming charge-trapping regions
Some embodiments include methods of forming charge-trapping zones. The methods may include forming nanoparticles, transferring the nanoparticles to a liquid to...
US-9,431,459 Switching components and memory units
Some embodiments include a switching component which includes a selector region between a pair of electrodes. The selector region contains silicon doped with...
US-9,431,422 Semiconductor constructions and NAND unit cells
Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed....
US-9,431,421 Data line arrangement and pillar arrangement in apparatuses
Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed...
US-9,431,410 Methods and apparatuses having memory cells including a monolithic semiconductor channel
Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of...
US-9,431,128 Semiconductor device including fuse circuit
Disclosed herein is an apparatus that includes a fuse circuit including a fuse element, the fuse circuit configured to provide a first output signal having a...
US-9,431,121 Read voltage adjustment
The present disclosure includes apparatuses and methods related to adjusting read voltages of charge-trapping flash memory. An example embodiment apparatus can...
US-9,431,102 Apparatus and method for reading a phase-change memory cell
An apparatus and a method of reading a phase-change memory cell are described. A circuit includes a current ramp circuit. A current forcing module is coupled to...
US-9,431,094 Input buffer
Apparatuses including a data input circuit of a semiconductor device are described. An example apparatus includes a first transistor that receives a reference...
US-9,430,735 Neural network in a memory device
Devices, systems and methods for operating a memory device facilitating a neural network in a memory device are disclosed. In at least one embodiment, the...
US-9,430,417 Sequential memory access operations
Methods of operating a memory include performing a memory access operation, obtaining an address corresponding to a subsequent memory access operation prior to...
US-9,430,385 Moveable locked lines in a multi-level cache
A processor includes a multi-level cache hierarchy where a lock property is associated with a cache line. The cache line retains the lock property and may move...
US-9,430,378 Differential delay compensation
In one embodiment, a method includes receiving a plurality of data frames representing at least one virtually concatenated data stream, storing the plurality of...
US-9,430,373 Apparatus including memory channel control circuit and related methods for relaying commands to logical units
Memory system controllers can include a switch and non-volatile memory control circuitry coupled to the switch. The non-volatile memory control circuitry can...
US-9,430,191 Division operations for memory
Examples of the present disclosure provide apparatuses and methods for performing division operations in a memory. An example apparatus comprises a first...
US-9,426,384 Method, apparatus, and system providing an imager with pixels having extended dynamic range
The dynamic range of a pixel is increased by using selective photosensor resets during a frame time of image capture at a timing depending on the light...
US-9,425,390 Select device for memory cell applications
The present disclosure includes select devices and methods of using select device for memory cell applications. An example select device includes a first...
US-9,425,190 Techniques for providing a direct injection semiconductor memory device
Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as...
US-9,425,177 Method of manufacturing semiconductor device including grinding semiconductor wafer
A method of manufacturing a semiconductor device according to one embodiment includes: preparing a semiconductor water which is partitioned into a plurality of...
US-9,425,133 Integrated circuits and methods of forming conductive lines and conductive pads therefor
An integrated circuit includes circuitry, a first conductor coupled to the circuitry, a conductive pad coupled to the first conductor, and a second conductor...
US-9,424,938 Reduced voltage nonvolatile flash memory
Subject matter disclosed herein relates to a memory device, and more particularly to nonvolatile memory. The nonvolatile memory may include a memory cell array...
US-9,424,920 Memory cells, methods of forming memory cells, and methods of programming memory cells
Some embodiments include methods in which a memory cell is formed to have programmable material between first and second access lines, with the programmable...
US-9,424,907 Semiconductor device suppressing BTI deterioration
Disclosed herein is a device includes a command generation circuit that activates first and second command signals, an internal circuit that includes a...
US-9,424,899 Apparatuses and methods for providing active and inactive clock signals to a command path circuit
Apparatuses and methods for providing active and inactive clock signals to a command path circuit are described. An example method includes providing an active...
US-9,424,891 Methods and devices for temperature sensing of a memory device
Methods, apparatuses and systems are disclosed involving a memory device. In one embodiment, a memory device is disclosed that includes a command error module...
US-9,424,222 Apparatuses and methods for charge sharing across data buses based on respective levels of a data buses
Apparatuses and methods for charge sharing across data buses based on respective levels of the data buses are disclosed herein. An example apparatus may include...
US-9,423,969 Sensing operations in a memory device
Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a...
US-9,423,960 Methods of operating memory devices within a communication protocol standard timeout requirement
The present disclosure includes methods and devices for logical memory blocks. One method for operating a memory device includes receiving a command to operate...
US-9,419,628 Measurement initialization circuitry
Measurement initialization circuitry is described. Propagation of a start signal through a variable delay line may be stopped by either of two stop signals. One...
US-9,419,220 Resistive memory elements, resistive memory cells, and resistive memory devices
A method of forming a resistive memory element comprises forming an oxide material over a first electrode. The oxide material is exposed to a plasma process to...
US-9,419,219 Resistive RAM devices and methods
The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One...
US-9,419,215 Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming...
Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and...
US-9,419,182 Solid-state radiation transducer devices having at least partially transparent buried-contact elements, and...
Solid-state radiation transducer (SSRT) devices having buried contacts that are at least partially transparent and associated systems and methods are disclosed...
US-9,419,056 Resistive memory cell structures and methods
Resistive memory cell structures and methods are described herein. One or more memory cell structures comprise a first resistive memory cell comprising a first...
US-9,418,974 Stacked semiconductor die assemblies with support members and associated systems and methods
Stacked semiconductor die assemblies with support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die...
US-9,418,970 Redistribution layers for microfeature workpieces, and associated systems and methods
Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system...
US-9,418,968 Semiconductor device including semiconductor chips mounted over both surfaces of substrate
A semiconductor chip 10 flip-chip mounted on a first surface 32 of a wiring substrate 30, a semiconductor chip 20 flip-chip mounted on a second surface 33 of...
US-9,418,926 Package-on-package semiconductor assemblies and methods of manufacturing the same
Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device...
US-9,418,872 Packaged microelectronic components
A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths...
US-9,418,848 Methods of forming patterns with a mask formed utilizing a brush layer
Some embodiments include methods of forming patterns. A first mask is formed over a material. The first mask has features extending therein and defines a first...
US-9,418,735 Memory device with reduced neighbor memory cell disturbance
In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes a memory cell, digit line driver, access line driver, clamping...
US-9,418,734 Multi-function resistance change memory cells and apparatuses including the same
Various embodiments comprise apparatuses including drive circuitry to provide signal pulses of a selected time duration and/or amplitude to a number of memory...
US-9,418,711 Semiconductor memory device having main word lines and sub-word lines
A plurality of memory mats classified into groups selected by bits of a row address, a main word driver for selecting a main word line based on bits of the row...
US-9,418,017 Hot memory block table in a solid state storage device
Solid state storage devices and methods for populating a hot memory block look-up table (HBLT) are disclosed. In one such method, an indication to an accessed...
US-9,417,685 Power management
Methods, and apparatus configured to perform such methods, providing peak power management are useful in mitigating excessive current levels within a multi-die...
US-9,417,517 Photomask having a blind region including periodical clear portions
A photo mask includes a plurality of dark patterns disposed on a transparent substrate, a first region, a shield region, and a second region. The first region...
US-9,413,535 Critical security parameter generation and exchange system and method for smart-card memory modules
A storage device contains a smart-card device and a memory device, which is connected to a controller. The storage device may be used in the same manner as a...
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