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Methods of forming semiconductor devices having recesses
Fin-FET (fin field-effect transistor) devices and methods of fabrication are disclosed. The fin-FET devices include dual fin structures that may form a channel...
Access line management in a memory device
Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device...
Methods, articles and devices for pulse adjustments to program a memory
Embodiments disclosed herein may relate to adjusting an aspect of a programming pulse for one or more memory cells, such as based at least in part on one or...
STT-MRAM cell structure incorporating piezoelectric stress material
A magnetic memory cell including a piezoelectric material, and methods of operating the memory cell are provided. The memory cell includes a stack, and the...
Apparatuses and methods including selectively providing a single or
separate chip select signals
Apparatus and methods are disclosed herein, including those that operate to initialize registers of a first memory device and a second memory device of a...
Wiring base plate and method for manufacturing the same
In a method for manufacturing a circuit board, as a photomask adapted to form an etching mask for selective removal of a seed layer covering a conductive...
Method of fabricating a microstrip line dielectric overlay
A printed circuit board has a dielectric constant different from the dielectric constant of free space, with at least two microstrip lines routed adjacent to...
Memory cell arrays
Some embodiments include memory cells. The memory cells may have a first electrode, and a trench-shaped programmable material structure over the first...
Methods of forming diodes
Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is...
Reconfigurable connections for stacked semiconductor devices
Some embodiments include apparatus, systems, and methods comprising semiconductor dice arranged in a stack, a number of connections configured to provide...
A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second...
Methods for forming interconnects in microelectronic workpieces and
microelectronic workpieces formed using...
Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces having such interconnects are disclosed herein. One aspect of the...
Methods of forming memory arrays
Some embodiments include methods of forming memory arrays. An assembly is formed which has an upper level over a lower level. The lower level includes...
Semiconductor constructions and methods of forming electrically conductive
Some embodiments include methods of forming electrically conductive contacts. An opening is formed through an insulative material to a conductive structure. A...
Method and apparatus for simultaneously removing multiple conductive
materials from microelectronic substrates
A method and apparatus for simultaneously removing conductive materials from a microelectronic substrate. A method in accordance with one embodiment of the...
Methods and apparatuses for calibrating data sampling points
Methods and apparatuses for calibrating data sampling points are disclosed herein. An example apparatus may include a memory that may be configured to receive a...
An image rescue system includes an application program for communication with a mass storage device, the application program being in communication with an...
Controller to manage NAND memories
In various embodiments, a single virtualized error correcting code (ECC) NAND controller executes an ECC algorithm and manages a stack of NAND flash memories....
System and method for configuring drivers
Driver systems and methods are provided, such as those that include identifying a process corner of a driver; and configuring the driver based on the identified...
Apparatuses and methods and for providing power responsive to a power loss
Apparatuses and methods for providing power responsive a power loss are disclosed herein. A power chip may comprise a power sensor, a write command control...
Methods of forming patterns for semiconductor device structures
Methods of forming a pattern in a semiconductor device structure include deprotecting an outer portion of a first photosensitive resist material, forming a...
Vertical 4-way shared pixel in a single column with internal reset and no
A method and apparatus for reducing space and pixel circuit complexity by using a 4-way shared vertically aligned pixels in a same column. The at least four...
Optical waveguide with cascaded modulator circuits
A method of operating an optical waveguide for transmitting an optical signal input to the optical waveguide with a first frequency. The optical waveguide...
Combination ESD protection circuits and methods
Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. In an...
Variable resistance memory with lattice array using enclosing transistors
A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is...
Memory arrays and associated methods of manufacturing
Memory arrays and associated methods of manufacturing are disclosed herein. In one embodiment, a memory array includes an access line extending along a first...
Memory cells and methods of forming memory cells
Some embodiments include a memory cell that has an electrode, a switching material over the electrode, a buffer region over the switching material, and an ion...
Semiconductor constructions comprising fuse capacitors
Some embodiments include a semiconductor construction having a semiconductor substrate and an interlayer insulating material over the substrate. Memory cells...
Methods of forming an array of gated devices
A method of forming an array of gated devices includes forming a plurality of semiconductor material-comprising blocks individually projecting elevationally...
Semiconductor assemblies, stacked semiconductor devices, and methods of
manufacturing semiconductor assemblies...
Stacked semiconductor devices, semiconductor assemblies, methods of manufacturing stacked semiconductor devices, and methods of manufacturing semiconductor...
Pass-through 3D interconnect for microelectronic dies and associated
systems and methods
Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a...
Apparatus and method for high density multi-chip structures
Devices and methods are described including a multi-chip assembly. Embodiments of multi-chip assemblies are provided that uses both lateral connection...
Methods of forming a reversed pattern in a substrate, and related
semiconductor device structures
A method of forming a reversed pattern in a substrate. A resist on a substrate is exposed and developed to form a pattern therein, the patterned resist having a...
Constructions comprising thermally conductive stacks containing
rutile-type titanium oxide
Some embodiments include methods of forming rutile-type titanium oxide. A monolayer of titanium nitride may be formed. The monolayer of titanium nitride may...
Memory buffer having accessible information after a program-fail
A memory device, and a method of operating same, utilize a memory buffer associated with a memory array to maintain information to be available subsequent to a...
Memory array with power-efficient read architecture
Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings...
Timing violation handling in a synchronous interface memory
A phase-change memory includes a phase to provide an upper row address from a row address buffer, a phase to combine the upper row address with a lower row...
Sequential memory operation without deactivating access line signals
Some embodiments include apparatuses and methods for activating a signal associated with an access line coupled to different groups of memory cells during a...
Non-volatile memory device adapted to identify itself as a boot memory
Non-volatile memory devices and methods of their operation are provided. One such non-volatile memory device has an interface and a control circuit. The...
Method and apparatus to perform concurrent read and write memory
Subject matter disclosed herein relates to read and write processes of a memory device. During a write process to a particular partition in a memory array, a...
Probe block, probe card and probe apparatus both having the probe block
The present invention provides a probe block, which comprises 1) a conductive base on which a first groove is formed, 2) a pair of signal transmitting probes...
Stress measurement sensor
A stress measurement sensor provided with a sensor element that operates according to the SAW principle, comprising a base composed of a first material and the...
Efficient operations of components in a wireless communications device
Various embodiments comprise apparatuses and methods including a communications subsystem having an interface module and a protocol module with the...
Adaptive communication interface
Embodiments of the invention include a communication interface and protocol for allowing communication between devices, circuits, integrated circuits and...
Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits....
Analog delay lines and adaptive biasing
Examples of analog delay lines and analog delay systems, such as DLLs incorporating analog delay lines are described, as are circuits and methods for adaptive...
Methods of forming repeating structures
Some embodiments include integrated memory having an array of repeating plates across a plurality of nodes. The array includes rows and columns. The plates...
JFET devices with increased barrier height and methods of making same
Devices for providing transistors with improved operating characteristics are provided. In one example, a system includes a processor and a memory device. A...
Low-resistance interconnects and methods of making same
Devices and methods for providing low-resistance interconnects in a semiconductor device are provided. Specifically, one or more embodiments of the present...
Methods for forming semiconductor device packages
Methods for forming semiconductor device packages include applying an underfill material over a semiconductor wafer including conductive elements such that an...