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Patent # Description
US-9,312,480 Memory cells
Some embodiments include a memory cell having a data storage region between a pair of conductive structures. The data storage region is configured to support a...
US-9,312,266 Memories with memory arrays extending in opposite directions from a semiconductor and their formation
Memories and their formation are disclosed. One such memory has a first array of first memory cells extending in a first direction from a first surface of a...
US-9,312,023 Devices and methods of programming memory cells
Devices and methods of programming memory cells, both SLC and MLC, such as to reduce charge-storage structure to charge-storage structure coupling, are shown...
US-9,312,022 Memory timing self-calibration
Methods for memory input timing self-calibration, apparatuses for input timing self-calibration, and systems are disclosed. One such method includes...
US-9,312,020 Methods of operating memory devices
Methods of operating a memory device include applying an increasing sense voltage to a plurality of memory cells, wherein memory cells of the plurality of...
US-9,312,007 Memory device and method having charge level assignments selected to minimize signal coupling
A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the...
US-9,312,005 Accessing memory cells in parallel in a cross-point array
Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first...
US-9,311,999 Memory sense amplifiers and memory verification methods
Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a...
US-9,310,552 Methods and apparatus providing thermal isolation of photonic devices
Described embodiments include photonic integrated circuits and systems with photonic devices, including thermal isolation regions for the photonic devices....
US-9,306,600 Read threshold calibration for LDPC
Apparatuses and methods for soft read threshold location calibration are provided. One example method can include selecting read threshold sets (RTSs), and...
US-9,306,579 Output driver robust to data dependent noise
Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may...
US-9,306,518 Voltage regulators, amplifiers, memory devices and methods
Circuits, devices and methods are provided, such as an amplifier (e.g., a voltage regulator) that includes a feedback circuit that supplies negative feedback...
US-9,306,165 Replacement materials processes for forming cross point memory
Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line...
US-9,306,159 Phase change memory stack with treated sidewalls
Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements....
US-9,305,938 Methods of fabricating integrated structures, and methods of forming vertically-stacked memory cells
Some embodiments include a method of fabricating integrated structures. A metal-containing material is formed over a stack of alternating first and second...
US-9,305,929 Memory cells
A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor...
US-9,305,905 Apparatuses and related methods for staggering power-up of a stack of semiconductor dies
An apparatus including semiconductor dies in a stack. The semiconductor dies are configured to power-up in a staggered manner. Methods for powering up an...
US-9,305,865 Devices, systems and methods for manufacturing through-substrate vias and front-side structures
Methods of manufacturing semiconductor devices and semiconductor devices with through-substrate vias (TSVs). One embodiment of a method of manufacturing a...
US-9,305,861 Method and system for electrically coupling a chip to chip package
A chip and a chip package can transmit information to each other by using a set of converters capable of communicating with each other through the emission and...
US-9,305,844 Method of making a semiconductor device
Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon...
US-9,305,826 Semiconductor substrate for photonic and electronic structures and method of manufacture
A method of forming a substrate with isolation areas suitable for integration of electronic and photonic devices is provided. A common reticle and...
US-9,305,782 Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device...
A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be...
US-9,305,660 Page buffer connections and determining pass/fail condition of memories
Apparatus and methods for determining pass/fail condition of memories facilitate array efficiencies. In at least one embodiment, a set of common lines, one for...
US-9,305,659 Dynamic program window determination in a memory device
A memory device has an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to determine a program window...
US-9,305,656 Methods applying a non-zero voltage differential across a memory cell not involved in an access operation
Methods applying a non-zero voltage differential across a memory cell not involved in an access operation can facilitate improved data retention characteristics.
US-9,305,625 Apparatuses and methods for unit identification in a master/slave memory stack
Apparatuses and methods including a plurality of memory units are disclosed. An example apparatus includes a plurality of memory units. Each of the plurality of...
US-9,305,609 System and method of command based and current limit controlled memory device power up
Devices and systems for powering up a memory device, for example, are disclosed. One such memory device includes power up circuitry configured to receive an...
US-9,305,606 High-speed wireless serial communication link for a stacked device configuration using near field coupling
A memory module houses stacked memory devices and a memory controller each having a near-field interface coupled to loop antennas to communicate over-the-air...
US-9,304,968 Methods and devices for programming a state machine engine
A state machine engine having a program buffer. The program buffer is configured to receive configuration data via a bus interface for configuring a state...
US-9,304,750 System and method for processor with predictive memory retrieval assist
A system and method are described for a memory management processor which, using a table of reference addresses embedded in the object code, can open the...
US-9,299,930 Memory cells, integrated devices, and methods of forming memory cells
Some embodiments include integrated devices, such as memory cells. The devices may include chalcogenide material, an electrically conductive material over the...
US-9,299,929 Phase change memory cells including nitrogenated carbon materials, and related methods
A phase change memory cell comprising a first chalcogenide compound on a first electrode, a first nitrogenated carbon material directly on the first...
US-9,299,742 High-voltage solid-state transducers and associated systems and methods
High-voltage solid-state transducer (SST) devices and associated systems and methods are disclosed herein. An SST device in accordance with a particular...
US-9,299,709 Semiconductor device and semiconductor memory devices having first, second, and third insulating layers
Disclosed herein is a device that includes: a semiconductor substrate; a first insulating layer over a surface of the semiconductor substrate; first and second...
US-9,299,684 Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing...
A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second ...
US-9,299,663 Semiconductor devices and methods for backside photo alignment
Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature...
US-9,299,449 Methods and apparatus for sensing a memory cell
Methods of operating a memory include selectively discharging a data line through a memory cell selected for sensing, discharging a sense node to the data line...
US-9,299,442 Dynamic data caches, decoders and decoding methods
Examples described include dynamic data caches (DDCs), decoders and decoding methods that may fit into a smaller width area. The DDCs, decoders and decoding...
US-9,299,441 Programming and/or erasing a memory device in response to its program and/or erase history
For one embodiment, a programming method includes programming one or more memory cells of a memory device during a programming operation, determining, internal...
US-9,299,440 Methods and apparatuses including a variable termination impedance ratio
Methods of changing a centerline voltage of a data signal are described, along with apparatuses to change the centerline voltage. In one such method, portions...
US-9,299,439 Erasable block segmentation for memory
Various embodiments comprise apparatuses such as those having a block of memory divided into sub-blocks that share a common data line. Each of the sub-blocks of...
US-9,299,437 Apparatuses and methods including memory write operation
Some embodiments include apparatuses and methods having memory cells and access lines coupled to the memory cells. In one such apparatus, the access lines...
US-9,299,423 Optical interconnect in high-speed memory systems
A optical link for achieving electrical isolation between a controller and a memory device is disclosed. The optical link increases the noise immunity of...
US-9,299,416 Semiconductor device having a reduced footprint of wires connecting a DLL circuit with an input/output buffer
An apparatus includes a clock terminal configured to receive an external clock signal, a clock generator configured to generate an internal clock signal in...
US-9,299,406 Apparatuses and methods for providing word line voltages during standby
Apparatuses and methods of providing word line voltages include an example apparatus including a voltage driver and a word line driver. The voltage driver is...
US-9,299,405 Methods for sensing memory elements in semiconductor devices
A memory device that, in certain embodiments, includes a plurality of memory elements connected to a bit-line and a delta-sigma modulator with a digital output...
US-9,298,545 Data protection across multiple memory blocks
Data protection across multiple memory blocks can include writing a first portion of a codeword in a first location of a first memory block and writing a second...
US-9,298,437 Unrolling quantifications to control in-degree and/or out-degree of automaton
Apparatus, systems, and methods for a compiler are disclosed. One such compiler parses a human readable expression into a syntax tree and converts the syntax...
US-9,298,374 Methods of providing access to I/O devices
A method of providing one or more computing devices with access to a plurality of resources. The plurality of resources are provided by at least one physical...
US-D752,762 External transmit modulator for an implantable neural stimulator
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