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Patent # Description
US-9,235,134 Lens heating compensation in photolithography
Photolithographic apparatus and methods are disclosed. One such apparatus includes an optical path configured to provide a first diffraction pattern in a...
US-9,235,097 Active alignment of optical fiber to chip using liquid crystals
Devices and systems to perform optical alignment by using one or more liquid crystal layers to actively steer a light beam from an optical fiber to an optical...
US-9,234,279 Porous organosilicate layers, and vapor deposition systems and methods for preparing same
A vapor deposition system includes a deposition chamber having a substrate positioned therein. The system includes at least one vessel containing at least one...
US-9,234,273 Unsymmetrical ligand sources, reduced symmetry metal-containing compounds, and systems and methods including same
The present invention provides metal-containing compounds that include at least one .beta.-diketiminate ligand, and methods of making and using the same. In...
US-9,232,121 Image sensor defect identification using blurring techniques
Embodiments described herein may operate to image a scene with an imaging system using an image blurring technique. An image sensor array (ISA) element may be...
US-9,231,572 Output slew rate control
This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver...
US-9,231,206 Methods of forming a ferroelectric memory cell
A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation....
US-9,231,117 Charge storage apparatus and methods
Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is...
US-9,231,103 Vertical MOSFET transistor, in particular operating as a selector in nonvolatile memory devices
A vertical MOSFET transistor is formed in a body of semiconductor material having a surface. The transistor includes a buried conductive region of a first...
US-9,231,047 Capacitors and methods with praseodymium oxide insulators
Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and...
US-9,230,986 3D memory
Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional...
US-9,230,978 Semiconductor constructions and NAND unit cells
Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed....
US-9,230,968 Methods of forming memory arrays and semiconductor constructions
Some embodiments include methods of forming semiconductor constructions. A heavily-doped region is formed within a first semiconductor material, and a second...
US-9,230,859 Redistribution layers for microfeature workpieces, and associated systems and methods
Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system...
US-9,230,847 Engineered substrate assemblies with thermally opaque materials, and associated systems, devices, and methods
Engineered substrates having thermally opaque materials for preventing transmission of radiative energy during epitaxial growth processes and for separating...
US-9,230,692 Apparatuses and methods for mapping memory addresses to redundant memory
Apparatuses and methods related to redundant memory and mapping memory addresses to redundant memory are disclosed. An example apparatus includes a plurality of...
US-9,230,688 Determining an age of data stored in memory
The present disclosure includes apparatuses and methods for determining an age of data stored in memory. A number of embodiments include determining a sensing...
US-9,230,686 Semiconductor device having roll call circuit
Disclosed herein is an apparatus that includes: a plurality of memory banks each including a plurality of memory cells; a plurality of redundant circuits each...
US-9,230,685 Memory programming methods and memory systems
Memory programming methods and memory systems are described. One example memory programming method includes first applying a first signal to a memory cell to...
US-9,230,679 Apparatuses and methods for sensing fuse states
Apparatuses and methods for sensing fuse states are disclosed herein. An apparatus may include an array having a plurality of sense lines. A plurality of cells...
US-9,230,666 Drain select gate voltage management
Some embodiments include apparatus, systems, and methods that operate to apply a first value of a drain select gate voltage during a first portion of a...
US-9,230,661 Determining soft data for combinations of memory cells
The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of...
US-9,230,660 Data modulation for groups of memory cells
Methods, devices, and systems for data modulation for groups of memory cells. Data modulation for groups of memory cells can include modulating N units of data...
US-9,230,658 Method of storing data on a flash memory device
Methods and apparatus are disclosed, such as those involving a flash memory device. One such method includes storing data on memory cells on a memory block...
US-9,230,645 Apparatus and methods for forming a memory cell using charge monitoring
Apparatus and methods of forming a memory cell are described. In one such method, a forming charge applied to a memory cell, such as a Resistive RAM (RRAM)...
US-9,230,643 Verify or read pulse for phase change memory and switch
Embodiments disclosed herein may relate to applying verify or read pulses for phase change memory and switch (PCMS) devices. The read pulses may be applied at a...
US-9,230,616 Memory devices, memory device operational methods, and memory device implementation methods
Memory devices, memory device operational methods, and memory device implementation methods are described. According to one arrangement, a memory device...
US-9,229,887 Memory device with network on chip methods, apparatus, and systems
Apparatus, method and systems are provided such as those that can include a processor module, an interface device disposed above or below the processor module,...
US-9,229,848 Determining soft data for fractional digit memory cells
Apparatuses and methods for determining soft data for fractional digit memory cells are provided. One example apparatus can include a controller to determine...
US-9,229,802 Non-systematic coded error correction
Methods are described that facilitate the detection and correction of data in memory systems or devices by encoding the data bits of a memory row or block in a...
US-9,229,706 Method and apparatus for field firmware updates in data storage systems
Data storage devices and methods for updating firmware are disclosed. For example, one such data storage device includes a device firmware and a controller,...
US-9,229,328 Methods of forming semiconductor device structures, and related semiconductor device structures
A method of forming a semiconductor device structure comprises forming a template material over a substrate, the template material exhibiting preferential...
US-9,227,378 Methods, devices and processes for multi-state phase change devices
Devices include multiple phase change materials connected in parallel between electrodes. Memory cells with multiple parallel phase change materials can be...
US-9,219,225 Multi-bit ferroelectric memory device and methods of forming the same
Multi-bit ferroelectric memory devices and methods of forming the same are provided. One example method of forming a multi-bit ferroelectric memory device can...
US-9,219,132 Transistors, semiconductor constructions, and methods of forming semiconductor constructions
Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically...
US-9,219,070 3-D memory arrays
A 3-D memory array comprises a plurality of elevationally extending strings of memory cells. An array of select devices is elevationally over and individually...
US-9,219,001 Methods of forming semiconductor devices having recesses
Fin-FET (fin field-effect transistor) devices and methods of fabrication are disclosed. The fin-FET devices include dual fin structures that may form a channel...
US-9,218,884 Access line management in a memory device
Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device...
US-9,218,876 Methods, articles and devices for pulse adjustments to program a memory cell
Embodiments disclosed herein may relate to adjusting an aspect of a programming pulse for one or more memory cells, such as based at least in part on one or...
US-9,218,863 STT-MRAM cell structure incorporating piezoelectric stress material
A magnetic memory cell including a piezoelectric material, and methods of operating the memory cell are provided. The memory cell includes a stack, and the...
US-9,218,861 Apparatuses and methods including selectively providing a single or separate chip select signals
Apparatus and methods are disclosed herein, including those that operate to initialize registers of a first memory device and a second memory device of a...
US-9,215,810 Wiring base plate and method for manufacturing the same
In a method for manufacturing a circuit board, as a photomask adapted to form an etching mask for selective removal of a seed layer covering a conductive...
US-9,214,713 Method of fabricating a microstrip line dielectric overlay
A printed circuit board has a dielectric constant different from the dielectric constant of free space, with at least two microstrip lines routed adjacent to...
US-9,214,627 Memory cell arrays
Some embodiments include memory cells. The memory cells may have a first electrode, and a trench-shaped programmable material structure over the first...
US-9,214,527 Methods of forming diodes
Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is...
US-9,214,449 Reconfigurable connections for stacked semiconductor devices
Some embodiments include apparatus, systems, and methods comprising semiconductor dice arranged in a stack, a number of connections configured to provide...
US-9,214,394 CMOS fabrication
A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second...
US-9,214,391 Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using...
Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces having such interconnects are disclosed herein. One aspect of the...
US-9,214,389 Methods of forming memory arrays
Some embodiments include methods of forming memory arrays. An assembly is formed which has an upper level over a lower level. The lower level includes...
US-9,214,386 Semiconductor constructions and methods of forming electrically conductive contacts
Some embodiments include methods of forming electrically conductive contacts. An opening is formed through an insulative material to a conductive structure. A...
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