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Patent # Description
US-9,184,385 Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells
An array of nonvolatile memory cells includes a plurality of vertically stacked tiers of nonvolatile memory cells. The tiers individually include a first...
US-9,184,384 Memory cells and methods of forming memory cells
Some embodiments include methods of forming memory cells. An opening is formed over a first conductive structure to expose an upper surface of the first...
US-9,184,377 Resistance variable memory cell structures and methods
Resistance variable memory cell structures and methods are described herein. A number of embodiments include a first resistance variable memory cell comprising...
US-9,184,336 Light emitting devices with built-in chromaticity conversion and methods of manufacturing
Various embodiments of light emitting devices with built-in chromaticity conversion and associated methods of manufacturing are described herein. In one...
US-9,184,191 Method providing an epitaxial photonic device having a reduction in defects and resulting structure
A method of forming a photonic device and resulting structure are described in which the photonic device is epitaxially grown over a substrate surface...
US-9,184,175 Floating gate memory cells in vertical memory
Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A...
US-9,184,167 Memory cell support lattice
Memory cell support lattices and methods of forming the same are described herein. As an example, a method of forming a memory cell support lattice includes...
US-9,184,161 Vertical gated access transistor
A method of forming an apparatus includes forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least...
US-9,184,159 Simplified pitch doubling process flow
A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further...
US-9,184,105 Semiconductor device packages including thermally insulating materials and methods of making and using such...
Semiconductor devices may include a first semiconductor die comprising a heat-generating region located at a periphery thereof. A second semiconductor die is...
US-9,184,061 Systems and methods for forming zirconium and/or hafnium-containing layers
A method of forming (and apparatus for forming) a zirconium and/or hafnium-containing layer on a substrate, particularly a semiconductor substrate or substrate...
US-9,184,058 Methods of forming patterns by using a brush layer and masks
Some embodiments include methods of forming patterns. A first mask is formed over a material. The first mask has features extending therein and defines a first...
US-9,183,952 Apparatuses and methods for compressing data received over multiple memory accesses
Apparatuses and methods for compressing data responsive to a plurality of memory accesses is described. An example compression circuit includes a comparator...
US-9,183,948 Apparatuses, integrated circuits, and methods for measuring leakage current
Methods, apparatuses, and integrated circuits for measuring leakage current are disclosed. In one such example method, a word line is charged to a first...
US-9,183,941 Thermal treatment of flash memories
A memory controller can provide current to a heater in a flash memory to reduce cycling induced errors. If necessary, after heating, the memory may be...
US-9,183,929 Systems, methods and devices for programming a multilevel resistive memory cell
Embodiments disclosed herein may relate to programming a multi-level memory cell with programming pulse sequences that comprise forward-biased and...
US-9,183,928 Descending set verify for phase change memory
Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.
US-9,183,904 Apparatuses, memories, and methods for facilitating splitting of internal commands using a shared signal path
Apparatuses, memories, and methods for facilitating splitting of internal commands using a shared signal path are described. In an example shared signal path, a...
US-9,183,900 Data paths using a first signal to capture data and a second signal to output data and methods for providing data
Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register....
US-9,183,135 Preparation of memory device for access using memory access type indicator signal
Subject matter disclosed herein relates to memory devices or accessing memory devices, and more particularly, but by way of example and not limitation, to...
US-9,183,070 Resting blocks of memory cells in response to the blocks being deemed to fail
In an embodiment, a block of memory cells is rested in response to the block of memory cells being deemed to fail. For some embodiments, a rested block may be...
US-9,183,057 Systems and methods for accessing memory
Methods of mapping memory cells to applications, methods of accessing memory cells, systems, and memory controllers are described. In some embodiments, a memory...
US-9,178,141 Memory elements using self-aligned phase change material layers and methods of manufacturing same
A memory element and method of forming the same. The memory element includes a first electrode within a via in a first dielectric material. An insulating...
US-9,178,077 Semiconductor constructions
Some embodiments include a semiconductor construction having a stack containing alternating levels of control gate material and intervening dielectric material....
US-9,178,017 Semiconductor device and method for manufacturing same
A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well...
US-9,177,927 Method of forming a memory device
A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an...
US-9,177,917 Semiconductor constructions
Some embodiments include methods for depositing copper-containing material utilizing physical vapor deposition of the copper-containing material while keeping a...
US-9,177,910 Interconnect structures for integrated circuits and their formation
An embodiment of an interconnect structure for an integrated circuit may include a first conductor coupled to circuitry, a second conductor, a dielectric...
US-9,177,872 Memory cells, semiconductor devices, systems including such cells, and methods of fabrication
A memory cell is disclosed. The memory cell includes a transistor and a capacitor. The transistor includes a source region, a drain region, and a channel region...
US-9,177,828 External gettering method and device
Disclosed embodiments include external gettering provided by electronic packaging. An external gettering element for a semiconductor substrate, which may be...
US-9,177,795 Methods of forming nanostructures including metal oxides
A method of forming nanostructures may include forming a block copolymer composition within a trench in a material on a substrate, wherein the block copolymer...
US-9,177,794 Methods of patterning substrates
A method of patterning a substrate includes forming spaced first features over a substrate. Individual of the spaced first features include sidewall portions of...
US-9,177,672 Methods of operating memory involving identifiers indicating repair of a memory cell
Method of operating memory including storing and/or using an identifier indicating repair of a memory cell.
US-9,177,659 Determining and using soft data in memory devices and systems
The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include...
US-9,177,653 Method and system for programming non-volatile memory cells based on programming of proximate memory cells
A multi-level non-volatile memory device programs cells in each row in a manner that takes into account the coupling from the programming of cells that are...
US-9,177,651 Programming methods and memories
Methods of programming a memory and memories are disclosed. In at least one embodiment, a memory is programmed by determining a pretarget threshold voltage for...
US-9,177,622 Supply independent delayer
Electronic apparatus, systems, and methods can include a delayer having an inverter chain, where each inverter of the chain can be operatively regulated using...
US-9,177,614 Apparatuses and methods including memory with top and bottom data lines
Some embodiments include apparatuses and methods having a first set of data lines, a second set of data lines, and memory cells located in different levels of...
US-9,176,904 Control of page access in memory
The present techniques provide systems and methods of controlling access to more than one open page in a memory component, such as a memory bank. Several...
US-9,176,868 Translation layer in a solid state storage device
Solid state storage devices and methods for flash translation layers are disclosed. In one such translation layer, a sector indication is translated to a memory...
US-9,176,831 Rearranging programming data to avoid hard errors
This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one...
US-9,176,800 Memory refresh methods and apparatuses
Apparatuses and memory refresh methods are disclosed, such as those involving checking a portion of a memory device for errors in response to the memory device...
US-9,176,740 System and method of indirect register access via directly accessible registers
Systems and methods are provided for managing access to registers. A system may include a set of direct registers and a set of indirect registers. The indirect...
US-9,176,385 Lithography methods, methods for forming patterning tools and patterning tools
Methods of lithography, methods for forming patterning tools, and patterning tools are described. One such patterning tool include an active region that forms a...
US-9,175,217 Wet etchants including at least one fluorosurfactant etch blocker
Methods for preventing isotropic removal of materials at corners faulted by seams, keyholes, and other anomalies in films or other structures include use of...
US-9,172,372 Apparatuses, circuits, and methods for reducing metastability in data synchronization
Apparatuses, circuits, and methods are disclosed for reducing or eliminating unintended operation resin ling from metastability in data synchronization. In one...
US-9,172,040 Resistive memory cell fabrication methods and devices
A phase change memory cell and methods of fabricating the same are presented. The memory cell includes a variable resistance region and a top and bottom...
US-9,172,037 Combined conductive plug/conductive line memory arrays and methods of forming the same
Memory arrays and methods of forming the same are provided. One example method of forming a memory array can include forming a conductive material in a number...
US-9,171,903 Transistors having features which preclude straight-line lateral conductive paths from a channel region to a...
Some embodiments include transistors having a channel region under a gate, having a source/drain region laterally spaced from the channel region by an active...
US-9,171,902 Semiconductor structures comprising a plurality of active areas separated by isolation regions
Methods of pitch doubling of asymmetric features and semiconductor structures including the same are disclosed. In one embodiment, a single photolithography...
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