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Patent # Description
US-9,230,679 Apparatuses and methods for sensing fuse states
Apparatuses and methods for sensing fuse states are disclosed herein. An apparatus may include an array having a plurality of sense lines. A plurality of cells...
US-9,230,666 Drain select gate voltage management
Some embodiments include apparatus, systems, and methods that operate to apply a first value of a drain select gate voltage during a first portion of a...
US-9,230,661 Determining soft data for combinations of memory cells
The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of...
US-9,230,660 Data modulation for groups of memory cells
Methods, devices, and systems for data modulation for groups of memory cells. Data modulation for groups of memory cells can include modulating N units of data...
US-9,230,658 Method of storing data on a flash memory device
Methods and apparatus are disclosed, such as those involving a flash memory device. One such method includes storing data on memory cells on a memory block...
US-9,230,645 Apparatus and methods for forming a memory cell using charge monitoring
Apparatus and methods of forming a memory cell are described. In one such method, a forming charge applied to a memory cell, such as a Resistive RAM (RRAM)...
US-9,230,643 Verify or read pulse for phase change memory and switch
Embodiments disclosed herein may relate to applying verify or read pulses for phase change memory and switch (PCMS) devices. The read pulses may be applied at a...
US-9,230,616 Memory devices, memory device operational methods, and memory device implementation methods
Memory devices, memory device operational methods, and memory device implementation methods are described. According to one arrangement, a memory device...
US-9,229,887 Memory device with network on chip methods, apparatus, and systems
Apparatus, method and systems are provided such as those that can include a processor module, an interface device disposed above or below the processor module,...
US-9,229,848 Determining soft data for fractional digit memory cells
Apparatuses and methods for determining soft data for fractional digit memory cells are provided. One example apparatus can include a controller to determine...
US-9,229,802 Non-systematic coded error correction
Methods are described that facilitate the detection and correction of data in memory systems or devices by encoding the data bits of a memory row or block in a...
US-9,229,706 Method and apparatus for field firmware updates in data storage systems
Data storage devices and methods for updating firmware are disclosed. For example, one such data storage device includes a device firmware and a controller,...
US-9,229,328 Methods of forming semiconductor device structures, and related semiconductor device structures
A method of forming a semiconductor device structure comprises forming a template material over a substrate, the template material exhibiting preferential...
US-9,227,378 Methods, devices and processes for multi-state phase change devices
Devices include multiple phase change materials connected in parallel between electrodes. Memory cells with multiple parallel phase change materials can be...
US-9,219,225 Multi-bit ferroelectric memory device and methods of forming the same
Multi-bit ferroelectric memory devices and methods of forming the same are provided. One example method of forming a multi-bit ferroelectric memory device can...
US-9,219,132 Transistors, semiconductor constructions, and methods of forming semiconductor constructions
Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically...
US-9,219,070 3-D memory arrays
A 3-D memory array comprises a plurality of elevationally extending strings of memory cells. An array of select devices is elevationally over and individually...
US-9,219,001 Methods of forming semiconductor devices having recesses
Fin-FET (fin field-effect transistor) devices and methods of fabrication are disclosed. The fin-FET devices include dual fin structures that may form a channel...
US-9,218,884 Access line management in a memory device
Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device...
US-9,218,876 Methods, articles and devices for pulse adjustments to program a memory cell
Embodiments disclosed herein may relate to adjusting an aspect of a programming pulse for one or more memory cells, such as based at least in part on one or...
US-9,218,863 STT-MRAM cell structure incorporating piezoelectric stress material
A magnetic memory cell including a piezoelectric material, and methods of operating the memory cell are provided. The memory cell includes a stack, and the...
US-9,218,861 Apparatuses and methods including selectively providing a single or separate chip select signals
Apparatus and methods are disclosed herein, including those that operate to initialize registers of a first memory device and a second memory device of a...
US-9,215,810 Wiring base plate and method for manufacturing the same
In a method for manufacturing a circuit board, as a photomask adapted to form an etching mask for selective removal of a seed layer covering a conductive...
US-9,214,713 Method of fabricating a microstrip line dielectric overlay
A printed circuit board has a dielectric constant different from the dielectric constant of free space, with at least two microstrip lines routed adjacent to...
US-9,214,627 Memory cell arrays
Some embodiments include memory cells. The memory cells may have a first electrode, and a trench-shaped programmable material structure over the first...
US-9,214,527 Methods of forming diodes
Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is...
US-9,214,449 Reconfigurable connections for stacked semiconductor devices
Some embodiments include apparatus, systems, and methods comprising semiconductor dice arranged in a stack, a number of connections configured to provide...
US-9,214,394 CMOS fabrication
A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second...
US-9,214,391 Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using...
Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces having such interconnects are disclosed herein. One aspect of the...
US-9,214,389 Methods of forming memory arrays
Some embodiments include methods of forming memory arrays. An assembly is formed which has an upper level over a lower level. The lower level includes...
US-9,214,386 Semiconductor constructions and methods of forming electrically conductive contacts
Some embodiments include methods of forming electrically conductive contacts. An opening is formed through an insulative material to a conductive structure. A...
US-9,214,359 Method and apparatus for simultaneously removing multiple conductive materials from microelectronic substrates
A method and apparatus for simultaneously removing conductive materials from a microelectronic substrate. A method in accordance with one embodiment of the...
US-9,214,232 Methods and apparatuses for calibrating data sampling points
Methods and apparatuses for calibrating data sampling points are disclosed herein. An example apparatus may include a memory that may be configured to receive a...
US-9,213,606 Image rescue
An image rescue system includes an application program for communication with a mass storage device, the application program being in communication with an...
US-9,213,603 Controller to manage NAND memories
In various embodiments, a single virtualized error correcting code (ECC) NAND controller executes an ECC algorithm and manages a stack of NAND flash memories....
US-9,213,553 System and method for configuring drivers
Driver systems and methods are provided, such as those that include identifying a process corner of a driver; and configuring the driver based on the identified...
US-9,213,386 Apparatuses and methods and for providing power responsive to a power loss
Apparatuses and methods for providing power responsive a power loss are disclosed herein. A power chip may comprise a power sensor, a write command control...
US-9,213,239 Methods of forming patterns for semiconductor device structures
Methods of forming a pattern in a semiconductor device structure include deprotecting an outer portion of a first photosensitive resist material, forming a...
US-9,210,347 Vertical 4-way shared pixel in a single column with internal reset and no row select
A method and apparatus for reducing space and pixel circuit complexity by using a 4-way shared vertically aligned pixels in a same column. The at least four...
US-9,209,904 Optical waveguide with cascaded modulator circuits
A method of operating an optical waveguide for transmitting an optical signal input to the optical waveguide with a first frequency. The optical waveguide...
US-9,209,620 Combination ESD protection circuits and methods
Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. In an...
US-9,209,395 Variable resistance memory with lattice array using enclosing transistors
A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is...
US-9,209,393 Memory arrays and associated methods of manufacturing
Memory arrays and associated methods of manufacturing are disclosed herein. In one embodiment, a memory array includes an access line extending along a first...
US-9,209,388 Memory cells and methods of forming memory cells
Some embodiments include a memory cell that has an electrode, a switching material over the electrode, a buffer region over the switching material, and an ion...
US-9,209,194 Semiconductor constructions comprising fuse capacitors
Some embodiments include a semiconductor construction having a semiconductor substrate and an interlayer insulating material over the substrate. Memory cells...
US-9,209,187 Methods of forming an array of gated devices
A method of forming an array of gated devices includes forming a plurality of semiconductor material-comprising blocks individually projecting elevationally...
US-9,209,166 Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies...
Stacked semiconductor devices, semiconductor assemblies, methods of manufacturing stacked semiconductor devices, and methods of manufacturing semiconductor...
US-9,209,158 Pass-through 3D interconnect for microelectronic dies and associated systems and methods
Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a...
US-9,209,127 Apparatus and method for high density multi-chip structures
Devices and methods are described including a multi-chip assembly. Embodiments of multi-chip assemblies are provided that uses both lateral connection...
US-9,209,039 Methods of forming a reversed pattern in a substrate, and related semiconductor device structures
A method of forming a reversed pattern in a substrate. A resist on a substrate is exposed and developed to form a pattern therein, the patterned resist having a...
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