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Methods and apparatuses including strings of memory cells formed along
levels of semiconductor material
Various embodiments include methods and apparatuses including strings of memory cells formed along levels of semiconductor material. One such apparatus includes...
High voltage solid-state transducers and solid-state transducer arrays
having electrical cross-connections and...
Solid-state transducer ("SST") dies and SST arrays having electrical cross-connections are disclosed herein. An array of SST dies in accordance with a...
Methods of forming electrically conductive lines
A method of forming an electrically conductive buried line and an electrical contact thereto includes forming of a longitudinally elongated conductive line...
Memory and sense parameter determination methods
Memory devices and methods for operating a memory include filtering a histogram of sensed data of the memory, and adjusting a parameter used to sense the memory...
Memory devices and programming memory arrays thereof
An embodiment of a method includes decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source while the first...
Apparatuses and methods to modify pillar potential
Apparatus are disclosed, such as a block including a number of strings of charge storage devices, each string including a number of charge storage devices...
Method and apparatus for configuring write performance for electrically
writable memory devices
Methods and systems are provided that may include a nonvolatile memory to store information, where the nonvolatile memory is associated with a configuration...
Reliable set operation for phase-change memory cell
A Phase-Change Memory (PCM) device and a method of writing data to the PCM device are described. The PCM device includes a multi-phase data storage cell having...
Circuits, apparatuses, and methods for oscillators
Circuits, apparatuses, and methods are disclosed for oscillators. In one such example oscillator circuit, a plurality of delay stages are coupled in series. A...
Apparatuses and methods for providing strobe signals to memories
Apparatuses and methods for providing strobe signals to memories are described herein. An example apparatus may include a plurality of memories and a memory...
Semiconductor device capable of performing a read leveling and a write
leveling based on an ambient temperature
Disclosed herein is an apparatus that includes a first semiconductor chip including a first electrode, and a second semiconductor chip including a second...
Vertical memory with body connection
An embodiment of an apparatus includes a substrate, a body semiconductor, a vertical memory access line stack over the body semiconductor, and a body connection...
Apparatus and methods for providing data integrity
The present disclosure includes apparatus (e.g., computing systems, memory systems, controllers, etc.) and methods for providing data integrity. One or more...
Resolving trapping sets
Apparatuses and methods for resolving trapping sets are provided. One example method can include attempting to decode a codeword using initial values for...
Method and system for generating object code to facilitate predictive
A method and system are described for generating reference tables in object code which specify the addresses of branches, routines called, and data references...
Methods, systems, and devices for management of a memory system
Methods, devices, and systems for a memory management system within an electronic device are disclosed, such as those wherein the memory management system is...
Circuits, integrated circuits, and methods for interleaved parity
Circuits, integrated circuits, and methods are disclosed for interleaved parity computation. In one such example circuit, an interleaved parity computation...
Methods and apparatuses for shifting data signals to match command signal
Methods and apparatuses for shifting data signals are disclosed herein. An apparatus may comprise a clock generation circuit, a delay path, and a driver. The...
Semiconductor constructions and methods of forming memory cells
Some embodiments include semiconductor constructions having stacks containing electrically conductive material over dielectric material. Programmable material...
Apparatuses including electrodes having a conductive barrier material and
methods of forming same
Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus...
Memory cells, methods of forming memory cells and methods of forming
Some embodiments include memory cells which have multiple programmable material structures between a pair of electrodes. One of the programmable material...
Solid state lighting devices with selected thermal expansion and/or
surface characteristics, and associated methods
Solid state lighting devices with selected thermal expansion and/or surface characteristics, and associated methods are disclosed. A method in accordance with a...
Semiconductor devices including stair step structures, and related methods
Semiconductor devices, such as three-dimensional memory devices, include a memory array including a stack of conductive tiers and a stair step structure. The...
Microelectronic die packages with metal leads, including metal leads for
stacked die packages, and associated...
Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked...
Interconnect structures for stacked dies, including penetrating structures
for through-silicon vias, and...
Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system...
Apparatuses, systems, devices, and methods of replacing at least partially
non-functional portions of memory
Subject matter disclosed herein relates to determining that a portion of a memory is at least partially non-functional, replacing the portion of at least...
Applying a voltage-delay correction to a non-defective memory block that
replaces a defective memory block...
In an embodiment, a defective memory block is replaced with a non-defective memory block, and a voltage-delay correction is applied to the non-defective memory...
Charge pump apparatus, a memory integrated circuit and methods of power
A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a...
Sensing operations in a memory device
Methods and apparatus for sensing operations in memory devices are disclosed. In at least one embodiment, a sensing operation to determine negative threshold...
Disturb verify for programming memory cells
Apparatuses and methods for disturb verify for programming operations are described. Programming memory cells can include applying a number of programming...
Determining sector status in a memory device
The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. A number of method embodiments include reading data...
Spin torque transfer memory cell structures and methods
Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures comprise an annular STT stack...
Devices, systems, and methods to synchronize parallel processing of a
single data stream
Disclosed are methods and devices, among which is a system that includes one or more pattern-recognition processors, such as in a pattern-recognition cluster....
Methods and systems to accomplish variable width data input
Disclosed are methods and systems for variable width data input to a pattern-recognition processor. A variable width data input method may include receiving...
Apparatus and method for data bypass for a bi-directional data bus in a
hub-based memory sub-system
A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and...
Staggered programming for resistive memories
Subject matter disclosed herein relates to a memory device and method of programming same. In some embodiments, a memory device can be programmed by...
Read bias management to reduce read errors for phase change memory
During a read process for a memory device, such as a phase change memory device, a bias condition can be applied to a memory cell to determine the memory cell's...
Network printing system and network printing program adapted to execute
printing from a mobile terminal to a...
A desired printer can be reliably selected and the setting of which printer is permitted to communicate with which mobile terminal can be easily altered. A...
Logical address translation
The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes...
Memory having internal processors and methods of controlling memory access
Memories having internal processors and methods of data communication within such memories are provided. One such memory may include a fetch unit configured to...
Method and device for writing photomasks with reduced mura errors
The problem of mura in large area photomasks is solved or at least reduced by setting up a writing system to write a pattern with high accuracy and with the...
Testing device and testing method for quantum battery using semiconductor
This invention provide a testing device and method for a quantum battery by a semiconductor probe, whereby the electrical characteristics of the charging layer...
Method for manufacturing a probe
A method for manufacturing a probe, includes forming a recess on a sacrificial layer with a resist matching a plane pattern of the probe and a fixing tab...
Method and apparatus providing analytical device and operating method
based on solid state image sensor
An analytical system-on-a-chip can be used as an analytical imaging device, for example, for detecting the presence of a chemical compound. A layer of...
High speed ring/bus
A data communication bus and method of operation thereof, including a plurality of nodes connected to a respective plurality of media segments. A typical node...
Die location compensation
Embodiments are described that compensate for a difference in a characteristic (e.g., of performance or operation) of a semiconductor device that is a function...
Resistive memory cell
Semiconductor memory devices, resistive memory devices, memory cell structures, and methods of forming a resistive memory cell are provided. One example method...
Vertical solid-state transducers and high voltage solid-state transducers
having buried contacts and associated...
Solid-state transducers ("SSTs") and vertical high voltage SSTs having buried contacts are disclosed herein. An SST die in accordance with a particular...
Charge-retaining transistor, array of memory cells, and methods of forming
a charge-retaining transistor
A charge-retaining transistor includes a control gate and an inter-gate dielectric alongside the control gate. A charge-storage node of the transistor includes...
Recessed transistors containing ferroelectric material
Some embodiments include transistor constructions having a first insulative structure lining a recess within a base. A first conductive structure lines an...