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Patent # Description
US-9,197,251 Method and apparatus for reading data from non-volatile memory
Methods and apparatus are disclosed related to a memory device, such as a flash memory device that includes an array of memory cells. One such method includes...
US-9,196,810 Vertical solid-state transducers having backside terminals and associated systems and methods
Vertical solid-state transducers ("SSTs") having backside contacts are disclosed herein. An SST in accordance with a particular embodiment can include a...
US-9,196,753 Select devices including a semiconductive stack having a semiconductive material
Methods, devices, and systems are provided for a select device that can include a semiconductive stack of at least one semiconductive material formed on a first...
US-9,196,673 Methods of forming capacitors
A method of forming capacitors includes providing first capacitor electrodes within support material. The first capacitor electrodes contain TiN and the support...
US-9,196,619 Semiconductor device having metal bit line
Disclosed herein is a device that includes: a semiconductor substrate including a memory cell region and a peripheral circuit region arranged around the memory...
US-9,196,530 Forming self-aligned conductive lines for resistive random access memories
Resistive random access memory elements, such as phase change memory elements, may be defined using a plurality of parallel conductive lines over a stack of...
US-9,196,370 Reducing noise in semiconductor devices
The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a...
US-9,196,359 Read distribution management for phase change memory
Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.
US-9,196,357 Voltage stabilizing for a memory cell array
Voltage balancing for a memory cell array is provided. One example method of voltage balancing for a memory array can include activating an access node coupled...
US-9,196,355 Memory including a selector switch on a variable resistance memory cell
Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a...
US-9,196,349 Semiconductor device
A device includes an output circuit, a DLL (Delay Locked Loop) circuit including a first delay line receiving a first clock signal and outputting, in response...
US-9,196,346 Non-volatile memory with LPDRAM
Memory, systems and devices are disclosed where a non-volatile memory device (such as a Flash memory device) is paired with a LPDRAM memory device or array and...
US-9,196,321 On-die termination apparatuses and methods
Apparatuses and methods are disclosed herein, including those, performed by a memory die, that operate to detect that a command on a bus connected to the memory...
US-9,196,313 Stacked device identification assignment
Some embodiments include apparatus and methods having dice arranged in a stack. The dice include at least a first die and a second die, and a connection coupled...
US-9,195,604 Dynamic memory cache size adjustment in a memory device
Methods for dynamic memory cache size adjustment, enabling dynamic memory cache size adjustment, memory devices, and memory systems are disclosed. One such...
US-9,195,590 Sub-sector wear leveling in memories
Methods and memories for wear leveling by sub-sectors of a block are provided. In one such method, data are transferred from a first block of the memory to a...
US-9,195,406 Operation management in a memory device
Multiple segment operations having non-volatile state trackers in memory devices are disclosed. Operations are segmented in multiple segments and selectively...
US-9,195,149 Photolithography systems and associated methods of overlay error correction
Several embodiments of photolithography systems and associated methods of overlay error correction are disclosed herein. In one embodiment, a method for...
US-9,194,886 Probe and probe card
A probe is provided with a linear main body portion having a tip in contact with an electrode of a member to be tested in a state where a board-side end is in...
US-9,190,494 Systems and devices including fin field-effect transistors each having U-shaped semiconductor fin
Disclosed are methods, systems and devices, including a system, having a memory device. In some embodiments, the memory device includes a plurality of fin...
US-9,190,472 Apparatuses and methods comprising a channel region having different minority carrier lifetimes
Apparatuses, such as memory devices, memory cell strings, and electronic systems, and methods of forming such apparatuses are shown. One such apparatus includes...
US-9,190,416 Three-dimensional structured memory devices
In various embodiments, a three-dimensional structured nonvolatile semiconductor memory devices and methods for manufacturing the devices are disclosed. One...
US-9,190,265 Memory devices and formation methods
A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant...
US-9,190,174 Determining soft data from a hard read
Apparatuses and methods involving the determination of soft data from hard reads are provided. One example method can include determining, using a hard read, a...
US-9,190,162 Nonconsecutive sensing of multilevel memory cells
Apparatuses and methods for nonconsecutive sensing of multilevel memory cells include methods of sensing a unit of information from a multilevel memory cell...
US-9,190,153 Asynchronous/synchronous interface
The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling...
US-9,190,144 Memory device architecture
Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.
US-9,190,133 Apparatuses and methods for a memory die architecture including an interface memory
Apparatuses and methods for reducing capacitance on a data bus are disclosed herein. In accordance with one or more described embodiments, an apparatus may...
US-9,190,126 Transistor voltage threshold mismatch compensated sense amplifiers and methods for precharging sense amplifiers
Sense amplifiers and methods for precharging are disclosed, including a sense amplifier having a pair of cross-coupled complementary transistor inverters, and a...
US-9,189,444 Apparatus, electronic devices and methods associated with an operative transition from a first interface to a...
Subject matter disclosed herein relates to an apparatus comprising memory and a controller, such as a controller which determines block locking states in...
US-9,189,440 Data interleaving module
The present disclosure includes apparatuses and methods related to a data interleaving module. A number of methods can include interleaving data received from a...
US-9,189,390 Wear leveling for erasable memories
In accordance with some embodiments, wear leveling may be done based on the difference in age of discarded blocks and engaged blocks. Data is moved to an older...
US-9,188,491 Semiconductor device including a temperature sensor circuit
A semiconductor device including a temperature sensor includes a pull up circuit, a pull down circuit, a first additional current path, and a second additional...
US-9,186,439 Drug-eluting catheter and method of manufacturing the same
Biocompatible nanoparticles 1 which entrap a bioactive substance and whose surface is positive-charge-modified are electrically adhered to a balloon portion 9...
US-9,185,315 Anti-eclipse circuitry with tracking of floating diffusion reset level
An anti-eclipse circuit for an imager is formed from pixel circuitry over the same semiconductor substrate as the imaging pixels. More specifically, two...
US-9,184,711 Signaling systems, preamplifiers, memory devices and methods
Signaling systems, preamplifiers, memory devices and methods are disclosed, such as a signaling system that includes a transmitter configured to receive a first...
US-9,184,385 Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells
An array of nonvolatile memory cells includes a plurality of vertically stacked tiers of nonvolatile memory cells. The tiers individually include a first...
US-9,184,384 Memory cells and methods of forming memory cells
Some embodiments include methods of forming memory cells. An opening is formed over a first conductive structure to expose an upper surface of the first...
US-9,184,377 Resistance variable memory cell structures and methods
Resistance variable memory cell structures and methods are described herein. A number of embodiments include a first resistance variable memory cell comprising...
US-9,184,336 Light emitting devices with built-in chromaticity conversion and methods of manufacturing
Various embodiments of light emitting devices with built-in chromaticity conversion and associated methods of manufacturing are described herein. In one...
US-9,184,191 Method providing an epitaxial photonic device having a reduction in defects and resulting structure
A method of forming a photonic device and resulting structure are described in which the photonic device is epitaxially grown over a substrate surface...
US-9,184,175 Floating gate memory cells in vertical memory
Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A...
US-9,184,167 Memory cell support lattice
Memory cell support lattices and methods of forming the same are described herein. As an example, a method of forming a memory cell support lattice includes...
US-9,184,161 Vertical gated access transistor
A method of forming an apparatus includes forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least...
US-9,184,159 Simplified pitch doubling process flow
A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further...
US-9,184,105 Semiconductor device packages including thermally insulating materials and methods of making and using such...
Semiconductor devices may include a first semiconductor die comprising a heat-generating region located at a periphery thereof. A second semiconductor die is...
US-9,184,061 Systems and methods for forming zirconium and/or hafnium-containing layers
A method of forming (and apparatus for forming) a zirconium and/or hafnium-containing layer on a substrate, particularly a semiconductor substrate or substrate...
US-9,184,058 Methods of forming patterns by using a brush layer and masks
Some embodiments include methods of forming patterns. A first mask is formed over a material. The first mask has features extending therein and defines a first...
US-9,183,952 Apparatuses and methods for compressing data received over multiple memory accesses
Apparatuses and methods for compressing data responsive to a plurality of memory accesses is described. An example compression circuit includes a comparator...
US-9,183,948 Apparatuses, integrated circuits, and methods for measuring leakage current
Methods, apparatuses, and integrated circuits for measuring leakage current are disclosed. In one such example method, a word line is charged to a first...
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