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Patent # Description
US-9,245,598 Circuitry and methods minimizing output switching noise through split-level signaling and bus division enabled...
Disclosed herein are circuitry and methods for transmitting data across a parallel bus using both high common mode and low common mode signaling. The...
US-9,245,597 Reference voltage generators and sensing circuits
Described examples include sensing circuits and reference voltage generators for providing a reference voltage to a sensing circuit. The sensing circuits may...
US-9,244,479 Current generator circuit and methods for providing an output current
Current circuits, circuits configured to provide a bias voltage, and methods for providing a bias voltage are described, including a current circuit configured...
US-9,244,477 Reference voltage generation for single-ended communication channels
An improved reference voltage (Vref) generator useable, for example, in sensing data on single-ended channels is disclosed. The Vref generator can be placed on...
US-9,242,103 Relay module for implant
An implementation provides a system that includes: a control module including a first antenna, the control module configured to generate a first radio frequency...
US-9,240,548 Memory arrays and methods of forming an array of memory cells
A method of forming an array of memory cells includes forming lines of covering material that are elevationally over and along lines of spaced sense line...
US-9,240,547 Magnetic tunnel junctions and methods of forming magnetic tunnel junctions
A method of forming a line of magnetic tunnel junctions includes forming magnetic recording material over a substrate, non-magnetic material over the recording...
US-9,240,496 Semiconductor device with floating gate and electrically floating body
Techniques for providing floating body memory devices are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor...
US-9,240,495 Methods of forming nanoscale floating gate
A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first...
US-9,240,477 Transistor-containing constructions and memory arrays
Some embodiments include transistor-containing constructions having gate material within an opening in a semiconductor material and spaced from the...
US-9,240,385 Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes...
US-9,240,240 Apparatus having indications of memory cell density and methods of their determination and use
Methods and apparatus utilizing indications of memory cell density facilitate management of memory density of a memory device. By permitting each of a plurality...
US-9,239,806 Systems, devices, memory controllers, and methods for controlling memory
Systems, devices, memory controllers, and methods for controlling memory are described. One such method includes activating a memory unit of a memory device;...
US-9,239,759 Switchable on-die memory error correcting engine
Subject matter disclosed herein relates to a user-switchable error correction coding (ECC) engine residing on a memory die.
US-9,239,432 Photonics grating coupler and method of manufacture
A structure for coupling an optical signal between an integrated circuit photonic structure and an external optical fiber is disclosed as in a method of...
US-9,237,629 Organic EL display panel for reducing resistance of electrode lines
An organic EL display comprising a substrate having an EL region, an anode on the EL region of the substrate, a supplementary electrode coupled to a portion of...
US-9,236,566 Memory cells and methods of forming memory cells
Some embodiments include methods of forming memory cells. Programmable material may be formed directly adjacent another material. A dopant implant may be...
US-9,236,550 Light emitting diodes with enhanced thermal sinking and associated methods of operation
Solid state lighting devices and associated methods of thermal sinking are described below. In one embodiment, a light emitting diode (LED) device includes a...
US-9,236,473 Field effect transistor devices
A memcapacitor device includes a pair of opposing conductive electrodes. A semiconductive material including mobile dopants within a dielectric and a mobile...
US-9,236,427 Multi-material structures and capacitor-containing semiconductor constructions
Some embodiments include a method of forming a capacitor. An opening is formed through a silicon-containing mass to a base, and sidewalls of the opening are...
US-9,236,383 Method and apparatus for fabricating a memory device with a dielectric etch stop layer
The present technique relates to a method and apparatus to provide a dielectric etch stop layer that prevents shorts for a buried digit layer as an...
US-9,236,307 Methods of forming transistors with broken up active regions
Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second...
US-9,236,270 High resolution printing technique
A pattern having exceptionally small features is printed on a partially fabricated integrated circuit during integrated circuit fabrication. The pattern is...
US-9,236,245 ZrA1ON films
Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium aluminum oxynitride (ZrAlON) for use in a variety of electronic devices....
US-9,236,146 Single check memory devices and methods
Memory devices and methods of operating memory devices are shown. Configurations described include circuits to perform a single check between programming pulses...
US-9,236,133 Adjusted read for partially programmed block
The present disclosure is related to an adjusted read for a partially programmed block. A number of methods can include receiving a read request including a...
US-9,236,123 Semiconductor device and write method
A semiconductor device includes a memory cell array including a plurality of first and second memory cells each comprising a variable resistance element that...
US-9,236,119 Diode/superionic conductor/polymer memory structure
A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second...
US-9,236,112 Apparatuses and methods for reducing cycle times in successive memory accesses
Methods and apparatuses are disclosed including an apparatus that includes a controller circuit configured to access a first subarray of a memory and to access...
US-9,236,102 Apparatuses, circuits, and methods for biasing signal lines
Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled...
US-9,235,798 Methods and systems for handling data received by a state machine engine
A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also...
US-9,235,730 Secure controller for block oriented storage
A storage controller includes a command pointer register. The command pointer register points to a chain of commands in memory, and also includes a security...
US-9,235,546 System and method for data read of a synchronous serial interface NAND
A method and system is disclosed for operating a NAND memory device. The NAND memory device is operated by transmitting serial peripheral interface signals from...
US-9,235,503 Stripe-based non-volatile multilevel memory operation
Stripe-based non-volatile multilevel memory operation can include writing a number of lower stripes including programming a number of lower pages of information...
US-9,235,459 Failure recovery memory devices and methods
Memory devices and methods are described that include serially chained memory devices. In one or more of the configurations shown, a serial chain of memory...
US-9,235,343 State change in systems having devices coupled in a chained configuration
The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of...
US-9,235,134 Lens heating compensation in photolithography
Photolithographic apparatus and methods are disclosed. One such apparatus includes an optical path configured to provide a first diffraction pattern in a...
US-9,235,097 Active alignment of optical fiber to chip using liquid crystals
Devices and systems to perform optical alignment by using one or more liquid crystal layers to actively steer a light beam from an optical fiber to an optical...
US-9,234,279 Porous organosilicate layers, and vapor deposition systems and methods for preparing same
A vapor deposition system includes a deposition chamber having a substrate positioned therein. The system includes at least one vessel containing at least one...
US-9,234,273 Unsymmetrical ligand sources, reduced symmetry metal-containing compounds, and systems and methods including same
The present invention provides metal-containing compounds that include at least one .beta.-diketiminate ligand, and methods of making and using the same. In...
US-9,232,121 Image sensor defect identification using blurring techniques
Embodiments described herein may operate to image a scene with an imaging system using an image blurring technique. An image sensor array (ISA) element may be...
US-9,231,572 Output slew rate control
This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver...
US-9,231,206 Methods of forming a ferroelectric memory cell
A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation....
US-9,231,117 Charge storage apparatus and methods
Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is...
US-9,231,103 Vertical MOSFET transistor, in particular operating as a selector in nonvolatile memory devices
A vertical MOSFET transistor is formed in a body of semiconductor material having a surface. The transistor includes a buried conductive region of a first...
US-9,231,047 Capacitors and methods with praseodymium oxide insulators
Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and...
US-9,230,986 3D memory
Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional...
US-9,230,978 Semiconductor constructions and NAND unit cells
Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed....
US-9,230,968 Methods of forming memory arrays and semiconductor constructions
Some embodiments include methods of forming semiconductor constructions. A heavily-doped region is formed within a first semiconductor material, and a second...
US-9,230,859 Redistribution layers for microfeature workpieces, and associated systems and methods
Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system...
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