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Patent # Description
US-9,190,494 Systems and devices including fin field-effect transistors each having U-shaped semiconductor fin
Disclosed are methods, systems and devices, including a system, having a memory device. In some embodiments, the memory device includes a plurality of fin...
US-9,190,472 Apparatuses and methods comprising a channel region having different minority carrier lifetimes
Apparatuses, such as memory devices, memory cell strings, and electronic systems, and methods of forming such apparatuses are shown. One such apparatus includes...
US-9,190,416 Three-dimensional structured memory devices
In various embodiments, a three-dimensional structured nonvolatile semiconductor memory devices and methods for manufacturing the devices are disclosed. One...
US-9,190,265 Memory devices and formation methods
A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant...
US-9,190,174 Determining soft data from a hard read
Apparatuses and methods involving the determination of soft data from hard reads are provided. One example method can include determining, using a hard read, a...
US-9,190,162 Nonconsecutive sensing of multilevel memory cells
Apparatuses and methods for nonconsecutive sensing of multilevel memory cells include methods of sensing a unit of information from a multilevel memory cell...
US-9,190,153 Asynchronous/synchronous interface
The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling...
US-9,190,144 Memory device architecture
Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.
US-9,190,133 Apparatuses and methods for a memory die architecture including an interface memory
Apparatuses and methods for reducing capacitance on a data bus are disclosed herein. In accordance with one or more described embodiments, an apparatus may...
US-9,190,126 Transistor voltage threshold mismatch compensated sense amplifiers and methods for precharging sense amplifiers
Sense amplifiers and methods for precharging are disclosed, including a sense amplifier having a pair of cross-coupled complementary transistor inverters, and a...
US-9,189,444 Apparatus, electronic devices and methods associated with an operative transition from a first interface to a...
Subject matter disclosed herein relates to an apparatus comprising memory and a controller, such as a controller which determines block locking states in...
US-9,189,440 Data interleaving module
The present disclosure includes apparatuses and methods related to a data interleaving module. A number of methods can include interleaving data received from a...
US-9,189,390 Wear leveling for erasable memories
In accordance with some embodiments, wear leveling may be done based on the difference in age of discarded blocks and engaged blocks. Data is moved to an older...
US-9,188,491 Semiconductor device including a temperature sensor circuit
A semiconductor device including a temperature sensor includes a pull up circuit, a pull down circuit, a first additional current path, and a second additional...
US-9,186,439 Drug-eluting catheter and method of manufacturing the same
Biocompatible nanoparticles 1 which entrap a bioactive substance and whose surface is positive-charge-modified are electrically adhered to a balloon portion 9...
US-9,185,315 Anti-eclipse circuitry with tracking of floating diffusion reset level
An anti-eclipse circuit for an imager is formed from pixel circuitry over the same semiconductor substrate as the imaging pixels. More specifically, two...
US-9,184,711 Signaling systems, preamplifiers, memory devices and methods
Signaling systems, preamplifiers, memory devices and methods are disclosed, such as a signaling system that includes a transmitter configured to receive a first...
US-9,184,385 Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells
An array of nonvolatile memory cells includes a plurality of vertically stacked tiers of nonvolatile memory cells. The tiers individually include a first...
US-9,184,384 Memory cells and methods of forming memory cells
Some embodiments include methods of forming memory cells. An opening is formed over a first conductive structure to expose an upper surface of the first...
US-9,184,377 Resistance variable memory cell structures and methods
Resistance variable memory cell structures and methods are described herein. A number of embodiments include a first resistance variable memory cell comprising...
US-9,184,336 Light emitting devices with built-in chromaticity conversion and methods of manufacturing
Various embodiments of light emitting devices with built-in chromaticity conversion and associated methods of manufacturing are described herein. In one...
US-9,184,191 Method providing an epitaxial photonic device having a reduction in defects and resulting structure
A method of forming a photonic device and resulting structure are described in which the photonic device is epitaxially grown over a substrate surface...
US-9,184,175 Floating gate memory cells in vertical memory
Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A...
US-9,184,167 Memory cell support lattice
Memory cell support lattices and methods of forming the same are described herein. As an example, a method of forming a memory cell support lattice includes...
US-9,184,161 Vertical gated access transistor
A method of forming an apparatus includes forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least...
US-9,184,159 Simplified pitch doubling process flow
A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further...
US-9,184,105 Semiconductor device packages including thermally insulating materials and methods of making and using such...
Semiconductor devices may include a first semiconductor die comprising a heat-generating region located at a periphery thereof. A second semiconductor die is...
US-9,184,061 Systems and methods for forming zirconium and/or hafnium-containing layers
A method of forming (and apparatus for forming) a zirconium and/or hafnium-containing layer on a substrate, particularly a semiconductor substrate or substrate...
US-9,184,058 Methods of forming patterns by using a brush layer and masks
Some embodiments include methods of forming patterns. A first mask is formed over a material. The first mask has features extending therein and defines a first...
US-9,183,952 Apparatuses and methods for compressing data received over multiple memory accesses
Apparatuses and methods for compressing data responsive to a plurality of memory accesses is described. An example compression circuit includes a comparator...
US-9,183,948 Apparatuses, integrated circuits, and methods for measuring leakage current
Methods, apparatuses, and integrated circuits for measuring leakage current are disclosed. In one such example method, a word line is charged to a first...
US-9,183,941 Thermal treatment of flash memories
A memory controller can provide current to a heater in a flash memory to reduce cycling induced errors. If necessary, after heating, the memory may be...
US-9,183,929 Systems, methods and devices for programming a multilevel resistive memory cell
Embodiments disclosed herein may relate to programming a multi-level memory cell with programming pulse sequences that comprise forward-biased and...
US-9,183,928 Descending set verify for phase change memory
Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.
US-9,183,904 Apparatuses, memories, and methods for facilitating splitting of internal commands using a shared signal path
Apparatuses, memories, and methods for facilitating splitting of internal commands using a shared signal path are described. In an example shared signal path, a...
US-9,183,900 Data paths using a first signal to capture data and a second signal to output data and methods for providing data
Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register....
US-9,183,135 Preparation of memory device for access using memory access type indicator signal
Subject matter disclosed herein relates to memory devices or accessing memory devices, and more particularly, but by way of example and not limitation, to...
US-9,183,070 Resting blocks of memory cells in response to the blocks being deemed to fail
In an embodiment, a block of memory cells is rested in response to the block of memory cells being deemed to fail. For some embodiments, a rested block may be...
US-9,183,057 Systems and methods for accessing memory
Methods of mapping memory cells to applications, methods of accessing memory cells, systems, and memory controllers are described. In some embodiments, a memory...
US-9,178,141 Memory elements using self-aligned phase change material layers and methods of manufacturing same
A memory element and method of forming the same. The memory element includes a first electrode within a via in a first dielectric material. An insulating...
US-9,178,077 Semiconductor constructions
Some embodiments include a semiconductor construction having a stack containing alternating levels of control gate material and intervening dielectric material....
US-9,178,017 Semiconductor device and method for manufacturing same
A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well...
US-9,177,927 Method of forming a memory device
A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an...
US-9,177,917 Semiconductor constructions
Some embodiments include methods for depositing copper-containing material utilizing physical vapor deposition of the copper-containing material while keeping a...
US-9,177,910 Interconnect structures for integrated circuits and their formation
An embodiment of an interconnect structure for an integrated circuit may include a first conductor coupled to circuitry, a second conductor, a dielectric...
US-9,177,872 Memory cells, semiconductor devices, systems including such cells, and methods of fabrication
A memory cell is disclosed. The memory cell includes a transistor and a capacitor. The transistor includes a source region, a drain region, and a channel region...
US-9,177,828 External gettering method and device
Disclosed embodiments include external gettering provided by electronic packaging. An external gettering element for a semiconductor substrate, which may be...
US-9,177,795 Methods of forming nanostructures including metal oxides
A method of forming nanostructures may include forming a block copolymer composition within a trench in a material on a substrate, wherein the block copolymer...
US-9,177,794 Methods of patterning substrates
A method of patterning a substrate includes forming spaced first features over a substrate. Individual of the spaced first features include sidewall portions of...
US-9,177,672 Methods of operating memory involving identifiers indicating repair of a memory cell
Method of operating memory including storing and/or using an identifier indicating repair of a memory cell.
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