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Memory array with a pair of memory-cell strings to a single conductive
An array of memory cells has a conductive pillar and a plurality of first and second memory cells coupled in series by the conductive pillar. Each first memory...
Multi-tiered semiconductor devices and associated methods
Methods of fabricating multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, a first...
Methods of forming ferroelectric capacitors
A method of forming a ferroelectric capacitor includes forming inner conductive capacitor electrode material over a substrate. After forming the inner electrode...
Electronic systems having substantially vertical semiconductor structures
An electronic system has first and second substantially vertical semiconductor structures. A first string of series-coupled first memory cells is adjacent to...
Memory cell repair
A repairable memory cell in accordance with one or more embodiments of the present disclosure includes a storage element positioned between a first and a second...
Stacked microelectronic devices and methods for manufacturing stacked
Stacked microelectronic devices and methods of manufacturing stacked microelectronic devices are disclosed herein. In one embodiment, a method of manufacturing...
Integrated circuit fabrication
A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a...
Shielded vertically stacked data line architecture for memory
Apparatuses and methods include an apparatus that includes first and second strings of vertically stacked memory cells, and first and second pluralities of...
Continuous adjusting of sensing voltages
The present disclosure includes apparatuses and methods for continuous adjusting of sensing voltages. A number of embodiments include continuously monitoring an...
Programming methods and memories
Methods of programming a memory and memories are disclosed. In at least one embodiment, a memory is programmed by determining a pretarget threshold voltage for...
Apparatuses and methods for driving a voltage of a wordline of a memory
Apparatuses, global and local wordline drivers, and methods for driving a wordline voltage in a memory is described. An example apparatus includes a memory...
Semiconductor device having level shift circuit
Disclosed herein is a device includes: a level conversion circuit coupled to first and third power supply lines, receiving a first signal and an inverted signal...
Remapping and compacting in a memory device
Methods for remapping and/or compacting data in memory devices, memory devices, and systems are disclosed. One such method of remapping and/or compacting data...
Method and apparatus for repairing high capacity/high bandwidth memory
Memory systems, systems and methods are disclosed that may include a plurality of stacked memory device dice and a logic die connected to each other by through...
Method and apparatus for compiling regular expressions
Apparatus, systems, and methods for a compiler are described. One such compiler converts source code into an automaton comprising states and transitions between...
Contact probe and probe card
A contact probe electrically connects the tester side and an electrode pad of a circuit to be tested. This contact probe has a mounting portion on a base end...
Probe assembly for inspecting power semiconductor devices and inspection
apparatus using the same, the probe...
A probe assembly for inspecting power semiconductor devices, which includes a probe block having more than one probe holding hole, more than one probe, each of...
Microfluidic apparatus and methods for performing blood typing and
Microfluidic cartridges for agglutination reactions are provided. The cartridges include a microfluidic reaction channel with at least two intake channels, one...
Scatterometry metrology methods and methods of modeling formation of a
vertical region of a multilayer...
A scatterometry target formed relative to an elevationally outermost surface of a substrate includes features having an optical property that is different from...
Heat-dissipating assemblies and methods of assembling heat-dissipating
Heat-dissipating assemblies may comprise mounting tabs attached to heat-generating electrical components at a first surface of each mounting tab. An opposing...
Termination for complementary signals
Apparatuses including termination for complementary signals are described, along with methods for terminating complementary signals. One such apparatus includes...
Resistive RAM devices and methods
The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One...
Resistive memory cell including integrated select device and storage
Resistive memory cells including an integrated select device and storage element and methods of forming the same are described herein. As an example, a...
Memory cells containing metal oxides
Some embodiments include memory cells which have first and second metal oxides between first and second electrodes. The first and second electrodes include...
Methods of forming dual gate structures
Semiconductor devices including dual gate structures and methods of forming such semiconductor devices are disclosed. For example, semiconductor devices are...
Semiconductor device having shared diffusion layer between transistors
A device includes a first transistor including a first gate electrode including first and second parallel electrode portions each extending in a first...
Semiconductor device structures
Methods of forming features are disclosed. One method comprises forming a resist over a pool of acidic or basic material on a substrate structure, selectively...
Methods of forming gated devices
Some embodiments include methods of forming gated devices. An upper region of a semiconductor material is patterned into a plurality of walls that extend...
Methods of making an interposer structure with embedded capacitor
A device is disclosed which includes an interposer, at least one capacitor formed at least partially within an opening formed in the interposer and an...
Extensions of self-assembled structures to increased dimensions via a
"bootstrap" self-templating method
Methods for fabricating sublithographic, nanoscale arrays of openings and linear microchannels utilizing self-assembling block copolymers, and films and devices...
Limiting flash memory over programming
Certain aspects of this disclosure relate to programming an at least one flash memory cell using an at least one programming pulse with a new programming...
Techniques for refreshing a semiconductor memory device
Techniques for refreshing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor...
Architecture for virtual security module
A device supports the processing of multiple active applications in a processor through a mapping system that securely identifies and differentiates commands...
Imaging devices, methods of forming same, and methods of forming
semiconductor device structures
An imaging device comprising a first region and a second region. Imaging features in the first region and assist features in the second region are substantially...
Image sensor defect identification using optical flare
Embodiments described herein may operate to compare an illuminance corresponding to a signal from an image sensor array (ISA) element in a production imaging...
Resistive memory and methods of processing resistive memory
Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include forming...
Forming resistive random access memories together with fuse arrays
A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same...
Phase change memory cells and methods of forming phase change memory cells
A phase change memory cell has first and second electrodes having phase change material there-between. The phase change memory cell is devoid of heater material...
Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy...
Memory cells and memory cell formation methods using sealing material
Memory cells, arrays of memory cells, and methods of forming the same with sealing material on sidewalls thereof are disclosed herein. One example of forming a...
Memory structures and arrays
Some embodiments include memory structures having a diode over a memory cell. The memory cell can include programmable material between a pair of electrodes,...
Memories and methods of forming thin-film transistors using hydrogen
Methods of forming thin-film transistors and memories are disclosed. In one such method, polycrystalline silicon is hydrogen plasma doped to form doped...
Methods of forming vertically-stacked memory cells
Some embodiments include a method of fabricating integrated structures. A metal-containing material is formed over a stack of alternating first and second...
Method of creating alignment/centering guides for small diameter, high
density through-wafer via die stacking
A method is provided for forming a die stack. The method includes forming a plurality of through-wafer vias and a first plurality of alignment features in a...
Interconnection designs and materials having improved strength and fatigue
Methods and designs for increasing interconnect areas for interconnect bumps are disclosed. An interconnect bump may be formed on a substrate such that the...
Methods and apparatuses including memory cells with air gaps and other low
dielectric constant materials
Various embodiments include apparatuses and methods of forming the same. One such apparatus can include a first dielectric material and a second dielectric...
In an embodiment, a short-checking method includes charging a data line to an initial voltage while activating a memory cell coupled to the data line, allowing...
Sense operation flags in a memory device
Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines...
Methods of reading and using memristor memory cells with a short read
Some embodiments include methods of reading memory cells. The memory cells have a write operation that occurs only if a voltage of sufficient absolute value is...
Methods for forming memory devices with reduced operational energy in
phase change material
Methods of forming and operating phase change memory devices include adjusting an activation energy barrier between a metastable phase and a stable phase of a...