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Patent # Description
US-9,209,187 Methods of forming an array of gated devices
A method of forming an array of gated devices includes forming a plurality of semiconductor material-comprising blocks individually projecting elevationally...
US-9,209,166 Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies...
Stacked semiconductor devices, semiconductor assemblies, methods of manufacturing stacked semiconductor devices, and methods of manufacturing semiconductor...
US-9,209,158 Pass-through 3D interconnect for microelectronic dies and associated systems and methods
Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a...
US-9,209,127 Apparatus and method for high density multi-chip structures
Devices and methods are described including a multi-chip assembly. Embodiments of multi-chip assemblies are provided that uses both lateral connection...
US-9,209,039 Methods of forming a reversed pattern in a substrate, and related semiconductor device structures
A method of forming a reversed pattern in a substrate. A resist on a substrate is exposed and developed to form a pattern therein, the patterned resist having a...
US-9,209,013 Constructions comprising thermally conductive stacks containing rutile-type titanium oxide
Some embodiments include methods of forming rutile-type titanium oxide. A monolayer of titanium nitride may be formed. The monolayer of titanium nitride may...
US-9,208,901 Memory buffer having accessible information after a program-fail
A memory device, and a method of operating same, utilize a memory buffer associated with a memory array to maintain information to be available subsequent to a...
US-9,208,891 Memory array with power-efficient read architecture
Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings...
US-9,208,835 Timing violation handling in a synchronous interface memory
A phase-change memory includes a phase to provide an upper row address from a row address buffer, a phase to combine the upper row address with a lower row...
US-9,208,833 Sequential memory operation without deactivating access line signals
Some embodiments include apparatuses and methods for activating a signal associated with an access line coupled to different groups of memory cells during a...
US-9,208,075 Non-volatile memory device adapted to identify itself as a boot memory
Non-volatile memory devices and methods of their operation are provided. One such non-volatile memory device has an interface and a control circuit. The...
US-9,208,019 Method and apparatus to perform concurrent read and write memory operations
Subject matter disclosed herein relates to read and write processes of a memory device. During a write process to a particular partition in a memory array, a...
US-9,207,260 Probe block, probe card and probe apparatus both having the probe block
The present invention provides a probe block, which comprises 1) a conductive base on which a first groove is formed, 2) a pair of signal transmitting probes...
US-9,207,132 Stress measurement sensor
A stress measurement sensor provided with a sensor element that operates according to the SAW principle, comprising a base composed of a first material and the...
US-9,204,487 Efficient operations of components in a wireless communications device
Various embodiments comprise apparatuses and methods including a communications subsystem having an interface module and a protocol module with the...
US-9,203,898 Adaptive communication interface
Embodiments of the invention include a communication interface and protocol for allowing communication between devices, circuits, integrated circuits and...
US-9,203,662 Multi-level signaling
Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits....
US-9,203,386 Analog delay lines and adaptive biasing
Examples of analog delay lines and analog delay systems, such as DLLs incorporating analog delay lines are described, as are circuits and methods for adaptive...
US-9,203,025 Methods of forming repeating structures
Some embodiments include integrated memory having an array of repeating plates across a plurality of nodes. The array includes rows and columns. The plates...
US-9,202,871 JFET devices with increased barrier height and methods of making same
Devices for providing transistors with improved operating characteristics are provided. In one example, a system includes a processor and a memory device. A...
US-9,202,786 Low-resistance interconnects and methods of making same
Devices and methods for providing low-resistance interconnects in a semiconductor device are provided. Specifically, one or more embodiments of the present...
US-9,202,714 Methods for forming semiconductor device packages
Methods for forming semiconductor device packages include applying an underfill material over a semiconductor wafer including conductive elements such that an...
US-9,202,700 Charge storage nodes with conductive nanodots
Methods of forming memory cells having conductive nanodots over a charge storage material are useful in non-volatile memory devices and electronic systems.
US-9,202,686 Electronic devices including barium strontium titanium oxide films
Apparatus and methods of forming the apparatus include a dielectric layer containing barium strontium titanium oxide layer, an erbium-doped barium strontium...
US-9,202,595 Post package repair of memory devices
An apparatus for post package repair can include memory cells in a package. A storage element can store information responsive to a post-package repair mode...
US-9,202,586 Non-volatile memory programming
Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying a signal to a line...
US-9,202,574 Memory device having a different source line coupled to each of a plurality of layers of memory cell arrays
In an embodiment, a memory device may have a plurality of layers of memory cell arrays. Each layer may have a plurality of strings of memory cells and a...
US-9,202,569 Methods for providing redundancy and apparatuses
Methods for providing redundancy and apparatuses are disclosed. One such method for providing redundancy performs a mapping of data between an address of a...
US-9,202,550 Appatuses and methods for precharge operations and accumulated charge dissipation
Examples described include precharge operations and circuitry for performing precharge operations. Digit lines may be driven to ground during a portion of...
US-9,202,542 Power supply induced signal jitter compensation
Examples of circuits and methods for compensating for power supply induced signal jitter in path elements sensitive to power supply variation. An example...
US-9,202,193 Early alert system and method for livestock disease detection
An early alert system and a related method for livestock disease detection are disclosed. In one embodiment of the invention, an activity measurement zone (AMZ)...
US-9,201,820 Solid state storage device controller with parallel operation mode
A master memory controller comprises a plurality of memory communication channels. At least one of the memory communication channels is used to communicate with...
US-9,201,718 Data recovery in a solid state storage system
Methods for data recovery and memory systems are provided. According to at least one such method, when defective data is read from a memory location, the data...
US-9,201,705 Multi-partitioning of memories
Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method...
US-9,200,937 Electrical configuration for a vibrating meter
A sensor assembly (200) for a vibrating meter (50) is provided. The sensor assembly (200) includes one or more conduits (103A, 103B). The sensor assembly (200)...
US-9,199,089 Remote control of power or polarity selection for a neural stimulator
An implantable neural stimulator includes one or more electrodes, at least one antenna, and one or more circuits connected to the at least one antenna. The one...
US-9,197,251 Method and apparatus for reading data from non-volatile memory
Methods and apparatus are disclosed related to a memory device, such as a flash memory device that includes an array of memory cells. One such method includes...
US-9,196,810 Vertical solid-state transducers having backside terminals and associated systems and methods
Vertical solid-state transducers ("SSTs") having backside contacts are disclosed herein. An SST in accordance with a particular embodiment can include a...
US-9,196,753 Select devices including a semiconductive stack having a semiconductive material
Methods, devices, and systems are provided for a select device that can include a semiconductive stack of at least one semiconductive material formed on a first...
US-9,196,673 Methods of forming capacitors
A method of forming capacitors includes providing first capacitor electrodes within support material. The first capacitor electrodes contain TiN and the support...
US-9,196,619 Semiconductor device having metal bit line
Disclosed herein is a device that includes: a semiconductor substrate including a memory cell region and a peripheral circuit region arranged around the memory...
US-9,196,530 Forming self-aligned conductive lines for resistive random access memories
Resistive random access memory elements, such as phase change memory elements, may be defined using a plurality of parallel conductive lines over a stack of...
US-9,196,370 Reducing noise in semiconductor devices
The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a...
US-9,196,359 Read distribution management for phase change memory
Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.
US-9,196,357 Voltage stabilizing for a memory cell array
Voltage balancing for a memory cell array is provided. One example method of voltage balancing for a memory array can include activating an access node coupled...
US-9,196,355 Memory including a selector switch on a variable resistance memory cell
Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a...
US-9,196,349 Semiconductor device
A device includes an output circuit, a DLL (Delay Locked Loop) circuit including a first delay line receiving a first clock signal and outputting, in response...
US-9,196,346 Non-volatile memory with LPDRAM
Memory, systems and devices are disclosed where a non-volatile memory device (such as a Flash memory device) is paired with a LPDRAM memory device or array and...
US-9,196,321 On-die termination apparatuses and methods
Apparatuses and methods are disclosed herein, including those, performed by a memory die, that operate to detect that a command on a bus connected to the memory...
US-9,196,313 Stacked device identification assignment
Some embodiments include apparatus and methods having dice arranged in a stack. The dice include at least a first die and a second die, and a connection coupled...
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