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Patent # Description
US-9,177,872 Memory cells, semiconductor devices, systems including such cells, and methods of fabrication
A memory cell is disclosed. The memory cell includes a transistor and a capacitor. The transistor includes a source region, a drain region, and a channel region...
US-9,177,828 External gettering method and device
Disclosed embodiments include external gettering provided by electronic packaging. An external gettering element for a semiconductor substrate, which may be...
US-9,177,795 Methods of forming nanostructures including metal oxides
A method of forming nanostructures may include forming a block copolymer composition within a trench in a material on a substrate, wherein the block copolymer...
US-9,177,794 Methods of patterning substrates
A method of patterning a substrate includes forming spaced first features over a substrate. Individual of the spaced first features include sidewall portions of...
US-9,177,672 Methods of operating memory involving identifiers indicating repair of a memory cell
Method of operating memory including storing and/or using an identifier indicating repair of a memory cell.
US-9,177,659 Determining and using soft data in memory devices and systems
The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include...
US-9,177,653 Method and system for programming non-volatile memory cells based on programming of proximate memory cells
A multi-level non-volatile memory device programs cells in each row in a manner that takes into account the coupling from the programming of cells that are...
US-9,177,651 Programming methods and memories
Methods of programming a memory and memories are disclosed. In at least one embodiment, a memory is programmed by determining a pretarget threshold voltage for...
US-9,177,622 Supply independent delayer
Electronic apparatus, systems, and methods can include a delayer having an inverter chain, where each inverter of the chain can be operatively regulated using...
US-9,177,614 Apparatuses and methods including memory with top and bottom data lines
Some embodiments include apparatuses and methods having a first set of data lines, a second set of data lines, and memory cells located in different levels of...
US-9,176,904 Control of page access in memory
The present techniques provide systems and methods of controlling access to more than one open page in a memory component, such as a memory bank. Several...
US-9,176,868 Translation layer in a solid state storage device
Solid state storage devices and methods for flash translation layers are disclosed. In one such translation layer, a sector indication is translated to a memory...
US-9,176,831 Rearranging programming data to avoid hard errors
This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one...
US-9,176,800 Memory refresh methods and apparatuses
Apparatuses and memory refresh methods are disclosed, such as those involving checking a portion of a memory device for errors in response to the memory device...
US-9,176,740 System and method of indirect register access via directly accessible registers
Systems and methods are provided for managing access to registers. A system may include a set of direct registers and a set of indirect registers. The indirect...
US-9,176,385 Lithography methods, methods for forming patterning tools and patterning tools
Methods of lithography, methods for forming patterning tools, and patterning tools are described. One such patterning tool include an active region that forms a...
US-9,175,217 Wet etchants including at least one fluorosurfactant etch blocker
Methods for preventing isotropic removal of materials at corners faulted by seams, keyholes, and other anomalies in films or other structures include use of...
US-9,172,372 Apparatuses, circuits, and methods for reducing metastability in data synchronization
Apparatuses, circuits, and methods are disclosed for reducing or eliminating unintended operation resin ling from metastability in data synchronization. In one...
US-9,172,040 Resistive memory cell fabrication methods and devices
A phase change memory cell and methods of fabricating the same are presented. The memory cell includes a variable resistance region and a top and bottom...
US-9,172,037 Combined conductive plug/conductive line memory arrays and methods of forming the same
Memory arrays and methods of forming the same are provided. One example method of forming a memory array can include forming a conductive material in a number...
US-9,171,903 Transistors having features which preclude straight-line lateral conductive paths from a channel region to a...
Some embodiments include transistors having a channel region under a gate, having a source/drain region laterally spaced from the channel region by an active...
US-9,171,902 Semiconductor structures comprising a plurality of active areas separated by isolation regions
Methods of pitch doubling of asymmetric features and semiconductor structures including the same are disclosed. In one embodiment, a single photolithography...
US-9,171,863 Methods and apparatuses including strings of memory cells formed along levels of semiconductor material
Various embodiments include methods and apparatuses including strings of memory cells formed along levels of semiconductor material. One such apparatus includes...
US-9,171,826 High voltage solid-state transducers and solid-state transducer arrays having electrical cross-connections and...
Solid-state transducer ("SST") dies and SST arrays having electrical cross-connections are disclosed herein. An array of SST dies in accordance with a...
US-9,171,750 Methods of forming electrically conductive lines
A method of forming an electrically conductive buried line and an electrical contact thereto includes forming of a longitudinally elongated conductive line...
US-9,171,633 Memory and sense parameter determination methods
Memory devices and methods for operating a memory include filtering a histogram of sensed data of the memory, and adjusting a parameter used to sense the memory...
US-9,171,626 Memory devices and programming memory arrays thereof
An embodiment of a method includes decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source while the first...
US-9,171,625 Apparatuses and methods to modify pillar potential
Apparatus are disclosed, such as a block including a number of strings of charge storage devices, each string including a number of charge storage devices...
US-9,171,619 Method and apparatus for configuring write performance for electrically writable memory devices
Methods and systems are provided that may include a nonvolatile memory to store information, where the nonvolatile memory is associated with a configuration...
US-9,171,614 Reliable set operation for phase-change memory cell
A Phase-Change Memory (PCM) device and a method of writing data to the PCM device are described. The PCM device includes a multi-phase data storage cell having...
US-9,171,599 Circuits, apparatuses, and methods for oscillators
Circuits, apparatuses, and methods are disclosed for oscillators. In one such example oscillator circuit, a plurality of delay stages are coupled in series. A...
US-9,171,597 Apparatuses and methods for providing strobe signals to memories
Apparatuses and methods for providing strobe signals to memories are described herein. An example apparatus may include a plurality of memories and a memory...
US-9,171,588 Semiconductor device capable of performing a read leveling and a write leveling based on an ambient temperature
Disclosed herein is an apparatus that includes a first semiconductor chip including a first electrode, and a second semiconductor chip including a second...
US-9,171,587 Vertical memory with body connection
An embodiment of an apparatus includes a substrate, a body semiconductor, a vertical memory access line stack over the body semiconductor, and a body connection...
US-9,170,898 Apparatus and methods for providing data integrity
The present disclosure includes apparatus (e.g., computing systems, memory systems, controllers, etc.) and methods for providing data integrity. One or more...
US-9,170,877 Resolving trapping sets
Apparatuses and methods for resolving trapping sets are provided. One example method can include attempting to decode a codeword using initial values for...
US-9,170,781 Method and system for generating object code to facilitate predictive memory retrieval
A method and system are described for generating reference tables in object code which specify the addresses of branches, routines called, and data references...
US-9,170,635 Methods, systems, and devices for management of a memory system
Methods, devices, and systems for a memory management system within an electronic device are disclosed, such as those wherein the memory management system is...
US-9,166,625 Circuits, integrated circuits, and methods for interleaved parity computation
Circuits, integrated circuits, and methods are disclosed for interleaved parity computation. In one such example circuit, an interleaved parity computation...
US-9,166,579 Methods and apparatuses for shifting data signals to match command signal delay
Methods and apparatuses for shifting data signals are disclosed herein. An apparatus may comprise a clock generation circuit, a delay path, and a driver. The...
US-9,166,159 Semiconductor constructions and methods of forming memory cells
Some embodiments include semiconductor constructions having stacks containing electrically conductive material over dielectric material. Programmable material...
US-9,166,158 Apparatuses including electrodes having a conductive barrier material and methods of forming same
Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus...
US-9,166,156 Memory cells, methods of forming memory cells and methods of forming memory arrays
Some embodiments include memory cells which have multiple programmable material structures between a pair of electrodes. One of the programmable material...
US-9,166,107 Solid state lighting devices with selected thermal expansion and/or surface characteristics, and associated methods
Solid state lighting devices with selected thermal expansion and/or surface characteristics, and associated methods are disclosed. A method in accordance with a...
US-9,165,937 Semiconductor devices including stair step structures, and related methods
Semiconductor devices, such as three-dimensional memory devices, include a memory array including a stack of conductive tiers and a stair step structure. The...
US-9,165,910 Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated...
Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked...
US-9,165,888 Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and...
Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system...
US-9,165,688 Apparatuses, systems, devices, and methods of replacing at least partially non-functional portions of memory
Subject matter disclosed herein relates to determining that a portion of a memory is at least partially non-functional, replacing the portion of at least...
US-9,165,681 Applying a voltage-delay correction to a non-defective memory block that replaces a defective memory block...
In an embodiment, a defective memory block is replaced with a non-defective memory block, and a voltage-delay correction is applied to the non-defective memory...
US-9,165,666 Charge pump apparatus, a memory integrated circuit and methods of power supply
A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a...
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