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Method for positioning spacers in pitch multiplication
Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers...
Methods of forming a span comprising silicon dioxide
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
Memory block quality identification in a memory device
If a memory block in a flash memory device is found to have a defect, a memory block quality indication is generated in response to the type of memory defect....
Adjusting operational parameters for memory cells
Techniques and devices relating to adjusting one or more operational parameters for memory cells are provided. One such device may include a detection unit...
Methods, devices and systems using over-reset state in a memory cell
Memory cells, devices and methods are disclosed, including those that involve applying a waveform to a resistive memory cell to program the memory cell to an...
Volume select for affecting a state of a non-selected memory volume
Apparatuses and methods of operating memory are described. One such method can include receiving a select command at a plurality of memory volumes of a memory...
Memory array plane select and methods
Memory arrays and methods of forming the same are provided. An example memory array can include at least one plane having a plurality of memory cells arranged...
Pinning content in nonvolatile memory
Systems and methods relating to pinning selected data to sectors in non-volatile memory. A graphical user interface allows a user to specify certain data (e.g.,...
Data bus inversion usable in a memory system
Implementations of Data Bus Inversion (DBI) techniques within a memory system are disclosed. In one embodiment, a set of random access memory (RAM) integrated...
Stopping criteria for layered iterative error correction
The present disclosure includes apparatuses and methods related to stopping criteria for layered iterative error correction. A number of methods can include...
Block-based storage device with a memory-mapped interface
Described herein are methods for accessing a block-based storage device having a memory-mapped interface and a block interface. In one embodiment, an apparatus...
Write command overlap detection
The present disclosure includes methods and apparatuses that include write command overlap detection. A number of embodiments include receiving an incoming...
Electrical connecting apparatus and method for assembling the same
An electrical connecting apparatus includes a wiring base plate having a first surface coupled with a reinforcing plate and provided on an opposite surface with...
Method for aligning plate-like members and method for manufacturing
electrical connecting apparatus
One plate-like member and the other plate-like member to be aligned with each other are provided with guide holes and guide portions to be received in the guide...
Method for manufacturing electric film body
A method for manufacturing an electric film body is made by forming a film body to have a shape in accordance with a desired electric characteristic and...
Methods of forming memory cells and arrays
Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed...
Methods of forming resistive memory elements
A method of forming a resistive memory element comprises forming an oxide material over a first electrode. The oxide material is exposed to a plasma process to...
Epitaxial growth methods and devices are described that include a textured surface on a substrate. Geometry of the textured surface provides a reduced lattice...
Memory cells and methods of storing information
Memory cells which have channel-supporting material, dielectric material over the channel-supporting material, carrier-trapping material over the dielectric...
Threshold voltage adjustment of a transistor
A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor...
Semiconductor devices comprising interconnect structures and methods of
Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of...
Semiconductor processing methods, and methods for forming silicon dioxide
Some embodiments include methods for semiconductor processing. A semiconductor substrate may be placed within a reaction chamber. The semiconductor substrate...
Method, system and device for recessed contact in memory array
Embodiments disclosed herein may relate to forming a contact region for an interconnect between a selector transistor and a word-line electrode in a memory device.
Method for fabricating a phase-change memory cell
A method for fabricating a phase-change memory cell is described. The method includes forming a dielectric layer (228) on a metal layer (226) above a substrate....
Methods of forming doped elements of semiconductor device structures
Methods of forming doped elements of semiconductor device structures include forming trenches having undercut portions separating stem portions of a substrate....
Memory with carbon-containing silicon channel
A memory includes a first memory cell and a second memory cell formed over the first memory cell. Each of the first memory cell and the second memory cell...
Memory device constructions, memory cell forming methods, and
semiconductor construction forming methods
Memory device constructions include a first column line extending parallel to a second column line, the first column line being above the second column line; a...
Forming three dimensional isolation structures
A three dimensional shallow trench isolation structure including sets of parallel trenches extending in two perpendicular directions may be formed by depositing...
Reading memory cell history during program operation for adaptive
Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a memory device.
Memory having memory cell string and coupling components
Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the...
Interconnections for 3D memory
Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs...
Intelligent controller system and method for smart card memory modules
A storage device contains a smart-card device and a memory device, both of which are accessed though a controller. The storage device may be used in the same...
Object oriented memory in solid state devices
The present disclosure includes methods, devices, and systems for object oriented memory in solid state devices. One embodiment of a method for object oriented...
Differential delay compensation
In one embodiment, a method includes recording, for each of a plurality of data frames, a virtual write address including a multiframe indicator and a byte...
Probe card and testing apparatus
Provided is a probe card capable of effectively placing electronic parts. A probe card according to the present invention includes a plurality of probes that...
On-die system and method for controlling termination impedance of memory
device data bus terminals
A system for controlling the termination impedance of memory device data bus terminals is fabricated on the same die as the memory device. The system includes a...
Multilevel mixed valence oxide (MVO) memory
Various embodiments include a memory device and methods of forming the same. The memory device can include an electrode coupled to one or more memory elements,...
Some embodiments include methods of forming vertical memory strings. A trench is formed to extend through a stack of alternating electrically conductive levels...
Semiconductor devices having compact footprints
Semiconductor devices and methods for making semiconductor devices are disclosed herein. A semiconductor device configured in accordance with a particular...
Methods of fabricating semiconductor structures
Semiconductor structures including an etch stop material between a substrate and a stack of alternating insulating materials and first conductive materials,...
Gettering agents in memory charge storage structures
Methods of forming memory cells including a charge storage structure having a gettering agent therein can be useful for non-volatile memory devices. Providing...
Semiconductor constructions and methods of forming electrically conductive
Some embodiments include methods of forming electrically conductive contacts. An opening is formed through an insulative material to a conductive structure. A...
Methods of forming semiconductor structures with sulfur dioxide etch
Methods of forming a semiconductor device structure and sulfur dioxide etch chemistries. The methods and chemistries, which may be plasma chemistries, include...
Apparatuses and methods of operating for memory endurance
Methods of operating an apparatus such as a computing system and/or memory device for memory endurance are provided. One example method can include receiving m...
Memories and methods of programming memories
Apparatus and methods for adjusting programming for upper pages of memories are disclosed. In at least one embodiment, a threshold voltage distribution upper...
Memory devices configured to apply different weights to different strings
of memory cells coupled to a data...
Memory devices and methods are disclosed. One such method compares input data to stored data in a memory device and includes applying a first weight factor to a...
Methods and systems for channel skewing are described. One or more methods for channel skewing includes providing a number of groups of data signals to a memory...
Memory device power managers and methods
Memory devices and methods are described that include a stack of memory dies and an attached logic die. Method and devices described provide for power...
Memory devices and methods of operating the same
The present disclosure includes memory devices and methods of operating the same. One such device includes an array of groups of memory cells, a group selector...
Program-disturb decoupling for adjacent wordlines of a memory device
Subject matter disclosed herein relates to memory operations regarding programming bits into a memory array.