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Patent # Description
US-9,583,163 Loop structure for operations in memory
Examples of the present disclosure provide apparatuses and methods related to performing a loop structure for operations performed in memory. An example...
US-9,583,160 Apparatuses including multiple read modes and methods for same
Apparatuses and methods including multiple read modes for reading data from a memory are described. An example apparatus includes a memory including a first...
US-9,583,157 Memory device power managers and methods
Memory devices and methods are described that include a stack of memory dies and an attached logic die. Method and devices described provide for power...
US-9,583,154 Methods and apparatuses including a string of memory cells having a first select transistor coupled to a second...
Generally discussed herein are apparatuses and methods. One such apparatus includes a data line, a first memory cell and a first select transistor. The first...
US-9,582,362 Setting a default read signal based on error correction
The present disclosure includes apparatuses and methods related to setting a default read signal based on error correction. A number of methods can include...
US-9,582,191 Memory block quality identification in a memory
Methods of operating electronic systems having a memory include reading indications of memory block quality from a plurality of memory blocks of the memory in...
US-9,579,825 Methods and systems for imaging and cutting semiconductor wafers and other semiconductor workpieces
Methods and systems for imaging and cutting semiconductor wafers and other microelectronic device substrates are disclosed herein. In one embodiment, a system...
US-9,578,266 Image sensor defect identification using optical flare
Embodiments described herein may operate to compare an illuminance corresponding to a signal from an image sensor array (ISA) element in a production imaging...
US-9,577,854 Apparatuses and methods for asymmetric bi-directional signaling incorporating multi-level encoding
Apparatuses and methods for asymmetric bi-directional signaling incorporating multi-level encoding are disclosed. An example apparatus may include first and...
US-9,577,673 Error correction methods and apparatuses using first and second decoders
Apparatuses and methods for error correcting data are provided. A first error correction code (ECC) decoder is configured to decode a first codeword to provide...
US-9,577,611 Controlling clock input buffers
An integrated circuit may have a clock input pin coupled to a buffer (24). The buffer may supply a clock signal (28) to an integrated circuit chip such as the...
US-9,577,188 Semiconductor constructions and methods of forming memory cells
Some embodiments include semiconductor constructions having stacks containing electrically conductive material over dielectric material. Programmable material...
US-9,577,186 Non-volatile resistive oxide memory cells and methods of forming non-volatile resistive oxide memory cells
A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. The...
US-9,577,168 Solid state lighting device with different illumination parameters at different regions of an emitter array
Solid state lighting (SSL) devices and methods of manufacturing such devices. One embodiment of an SSL device comprises a support and an emitter array having a...
US-9,577,092 Apparatuses having a vertical memory cell
Methods, apparatuses, and systems for providing a body connection to a vertical access device. The vertical access device may include a digit line extending...
US-9,577,058 Devices, systems, and methods related to removing parasitic conduction in semiconductor devices
Semiconductor devices and methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes...
US-9,577,010 Cross-point memory and methods for fabrication of same
The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same....
US-9,576,943 Apparatuses and methods of communicating differential serial signals including charge injection
Apparatuses and methods are disclosed, including an apparatus that includes a differential driver with charge injection pre-emphasis. One such apparatus...
US-9,576,904 Semiconductor devices comprising interconnect structures and methods of fabrication
Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of...
US-9,576,805 Fortification of charge-storing material in high-K dielectric environments and resulting apparatuses
Memories, systems, and methods for forming memory cells are disclosed. One such memory cell includes a charge storage node that includes nanodots over a tunnel...
US-9,576,674 Memory cell sensing
This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first memory cell coupled to a first data line,...
US-9,576,667 Apparatuses and methods for non-volatile memory programming schemes
Apparatuses and methods for a non-volatile memory scheme are described herein. An example apparatus may include a memory block including a plurality of...
US-9,576,662 Phase change memory in a dual inline memory module
Subject matter disclosed herein relates to management of a memory device.
US-9,576,659 Apparatuses and methods including memory access in cross point memory
Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch...
US-9,576,658 Systems, and devices, and methods for programming a resistive memory cell
Embodiments disclosed herein may relate to programming a memory cell with a programming pulse that comprises a quenching period having different portions. The...
US-9,576,654 Apparatuses, sense circuits, and methods for compensating for a wordline voltage increase
Apparatuses, sense circuits, and methods for compensating for a voltage increase on a wordline in a memory is described. An example apparatus includes a...
US-9,576,618 Memory devices, memory device operational methods, and memory device implementation methods
Memory devices, memory device operational methods, and memory device implementation methods are described. According to one arrangement, a memory device...
US-9,576,154 Methods of operating storage systems including using a key to determine whether a password can be changed
An embodiment of a method of operating a storage system includes combining a password, a first number, and a number of iterations to produce a first key,...
US-9,575,907 Memory apparatuses, computer systems and methods for ordering memory responses
Memory apparatuses that may be used for receiving commands and ordering memory responses are provided. One such memory apparatus includes response logic that is...
US-9,575,674 Data streaming for solid-state bulk storage devices
Methods facilitate data streaming in bulk storage devices by generating linked lists containing entries for both user data and metadata. These linked lists...
US-9,575,662 Multi-device memory serial architecture
Subject matter disclosed herein relates to memory devices comprising a memory array, a first port to interface with a memory controller directly or indirectly...
US-9,575,527 Power delivery circuitry
Embodiments of the present disclosure are directed to systems and methods for a memory device comprising a memory system and power delivery circuitry comprising...
US-9,573,809 Method of forming a metal chalcogenide material and methods of forming memory cells including same
A method of forming a metal chalcogenide material. The method comprises exposing a metal to a solution comprising a chalcogenide element source compound and an...
US-9,572,247 Memory card systems comprising flexible integrated circuit element packages, and methods for manufacturing said...
A memory card system may include a flexible integrated circuit device package, an upper flexible case, a lower flexible case, a wiring structure, an anisotropic...
US-9,571,602 Asymmetric chip-to-chip interconnect
Methods and apparatus apparatuses to transfer data between a first device and a second device are disclosed. In various embodiments, an apparatus includes a...
US-9,571,105 System and method for an accuracy-enhanced DLL during a measure initialization mode
A clock generator having a delay locked loop and a delay control circuit. The delay locked loop receives an input clock signal and adjusts an adjustable delay...
US-9,570,681 Resistive random access memory
A resistive random access memory may include a memory array and a periphery around the memory array. Decoders in the periphery may be coupled to address lines...
US-9,570,677 Memory cells, integrated devices, and methods of forming memory cells
Some embodiments include integrated devices, such as memory cells. The devices may include chalcogenide material, an electrically conductive material over the...
US-9,570,350 Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
Microfeature workpieces having interconnects and conductive backplanes and associated systems and methods are disclosed herein. One such device includes a...
US-9,570,201 Repair of memory devices using volatile and non-volatile memory
Apparatus and methods for hybrid post package repair are disclosed. One such apparatus may include a package including memory cells and volatile memory. The...
US-9,570,172 Apparatuses and methods for providing set and reset voltages at the same time
Apparatuses and methods are described, such as those involving driver circuits that are configured to provide reset and set voltages to different variable state...
US-9,570,167 Apparatuses and methods of reading memory cells
A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (V.sub.TH) region between a first state...
US-9,570,142 Apparatus having dice to perorm refresh operations
Some embodiments include an apparatus that comprise an interface chip having an oscillator to produce an original clock signal, a first memory chip having first...
US-9,570,135 Apparatuses and methods to delay memory commands and clock signals
An example delay circuit may include a delay block configured to receive a command signal and/or a bank address signal, a first clock signal, and a second clock...
US-9,570,125 Apparatuses and methods for shifting data during a masked write to a buffer
Apparatuses and methods are provided that include a multiplexer configured to generate a plurality of sums of a plurality of data words, wherein the plurality...
US-9,570,122 Device having multiple switching buffers for data paths controlled based on IO configuration modes
A device includes a first data terminal, a second data terminal, a first switching buffer coupled between a data node and the first data terminal and a second...
US-9,569,622 Self-measuring nonvolatile memory device systems and methods
One embodiment describes a computing system that includes a boot device. The boot device includes nonvolatile memory that stores startup routine instructions...
US-9,569,129 Controller to manage NAND memories
Various embodiments disclose a controller to manage memory devices. In an exemplary method, signals are exchanged with a host processor to allow the host...
US-9,568,674 Photonic device structure and method of manufacture
Disclosed method and apparatus embodiments provide a photonic device with optical isolation from a supporting substrate. A generally rectangular cavity in cross...
US-9,568,500 Electrical test probe
An electrical test probe according to an embodiment includes a probe main body portion having a connection end to a circuit of a probe base plate and made of a...
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