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| Patent # | Description |
|---|---|
| US-9,922,704 |
Programming memories with multi-level pass signal Methods of operating a memory include applying a multi-step pass voltage to a plurality of memory cells selected for a programming operation, applying a... |
| US-9,922,694 |
Apparatuses and methods for controlling refresh operations An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit... |
| US-9,922,686 |
Apparatuses and methods for performing intra-module databus inversion
operations Apparatuses, memory modules, and methods for performing intra-module data bus inversion operations are described. An example apparatus include a memory module... |
| US-9,922,683 |
Power delivery circuitry A memory device includes a memory system and an energy storage device including a capacitor. Additionally, the memory storage device includes power delivery... |
| US-9,920,441 |
Ozone water generating device An ozonated water generating device includes a first housing, a second housing on the first housing, and a catalytic electrode disposed in a space in the first... |
| US-9,912,498 |
Testing impedance adjustment Methods of operating integrated circuit devices are useful in testing impedance adjustment. Methods include connecting a node of the integrated circuit device... |
| US-9,912,328 |
Apparatus and method for instant-on quadra-phase signal generator Apparatuses are provided for a quadra-phase clock signal generator. An example apparatus includes a first delay circuit configured to receive a first input... |
| US-9,911,903 |
Solid state transducer dies having reflective features over contacts and
associated systems and methods Systems and methods for improved light emitting efficiency of a solid state transducer (SST), for example light emitting diodes (LED), are disclosed. One... |
| US-9,911,769 |
Elevated pocket pixels, imaging devices and systems including the same and
method of forming the same An elevated photosensor for image sensors and methods of forming the photosensor. The photosensor may have light sensors having indentation features including,... |
| US-9,911,696 |
Packaged semiconductor assemblies and methods for manufacturing such
assemblies Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of... |
| US-9,911,693 |
Semiconductor devices including conductive lines and methods of forming
the semiconductor devices A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged portion,... |
| US-9,911,692 |
Conductive structures, systems and devices including conductive structures
and related methods Conductive structures include a plurality of conductive steps and a contact extending at least partially therethrough in communication with at least one of the... |
| US-9,911,653 |
Low capacitance interconnect structures and associated systems and methods Semiconductor device interconnect structures having low capacitance and associated systems and methods are disclosed herein. In one embodiment, a method of... |
| US-9,911,643 |
Semiconductor constructions and methods of forming intersecting lines of
material Some embodiments include semiconductor constructions having first and second electrically conductive lines that intersect with one another at an intersection.... |
| US-9,911,609 |
Methods of forming nanostructures having low defect density A method of forming a nanostructure comprises forming self-assembled nucleic acids on at least a portion of a substrate. The method further comprises contacting... |
| US-9,911,608 |
Method of forming patterns A method of forming patterns includes the steps of providing a substrate on which a target layer and a hard mask layer are formed; forming a plurality of first... |
| US-9,911,489 |
Memory cells, memory systems, and memory programming methods Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically... |
| US-9,911,484 |
Oscillator controlled random sampling method and circuit Various embodiments comprise methods and apparatuses for selecting a randomly-chosen seed row from among a stream of available data in a memory system. A... |
| US-9,911,471 |
Input buffer circuit Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes: a first amplifier that provides first and... |
| US-9,911,469 |
Apparatuses and methods for power efficient driver circuits An apparatus comprising is disclosed. The apparatus a driver circuit configured to selectively provide a first supply voltage to an output node in a first... |
| US-9,911,466 |
Read threshold voltage selection Apparatuses and methods for read threshold voltage selection are provided. One example method can include setting a first soft read threshold voltage and a... |
| US-9,910,974 |
Method for controlling user access to an electronic device A method and system for authenticating a user to access a computer system. The method comprises communicating security information to the computer system, and... |
| US-9,910,787 |
Virtual address table The present disclosure includes apparatuses and methods related to virtual address tables. An example method comprises generating an object file that comprises:... |
| US-9,910,637 |
Signed division in memory Examples of the present disclosure provide apparatuses and methods for performing signed division operations. An apparatus can include a first group of memory... |
| US-9,910,594 |
Apparatuses and methods for concurrently accessing multiple memory planes
of a memory during a memory access... Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include... |
| US-9,910,089 |
Inspection unit, probe card, inspection device, and control system for
inspection device An inspection unit in which a probe card is united with a connection body via a vacuum chamber. It prevents flatness of tips of probes provided on the probe... |
| US-9,908,731 |
Paper conveying mechanism for printing apparatus A paper conveying mechanism includes an elastic urging member provided on each side surface of an upper guide. The urging member includes a projecting portion... |
| US-9,907,950 |
System and method for stimulation with electrode Some implementations provide a method for modulating excitable tissue in a body of a patient, the method including: placing a wireless implantable stimulator... |
| US-9,905,279 |
Systems, circuits, and methods for charge sharing Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage... |
| US-9,904,515 |
Multiplication operations in memory Examples of the present disclosure provide apparatuses and methods for performing multi-variable bit-length multiplication operations in a memory. An example... |
| US-9,899,070 |
Modified decode for corner turn Examples of the present disclosure provide apparatuses and methods for performing a corner turn using a modified decode. An example apparatus can comprise an... |
| US-9,898,252 |
Multiplication operations in memory Examples of the present disclosure provide apparatuses and methods for performing multiplication operations in a memory. An example method comprises performing... |
| US-9,895,692 |
Sample-to-answer microfluidic cartridge A microfluidic cartridge and methods for performing a diagnostic, molecular or biochemical assay thereon, where all dried and/or liquid reagents necessary for... |
| US-9,893,723 |
Apparatuses and methods for reducing off state leakage currents Apparatuses and methods for reducing leakage currents during an off state for transistors are described herein. An example apparatus includes a switch having an... |
| US-9,893,282 |
Methods of forming resistive memory elements A resistive memory element comprises a first electrode, an active material over the first electrode, a buffer material over the active material and comprising... |
| US-9,893,279 |
Methods, apparatuses, and circuits for programming a memory device Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device. |
| US-9,893,277 |
Memory arrays and methods of forming memory cells Some embodiments include methods of forming memory cells. A series of rails is formed to include bottom electrode contact material. Sacrificial material is... |
| US-9,893,083 |
Elevationally-extending strings of memory cells individually comprising a
programmable charge storage... A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the... |
| US-9,893,072 |
DRAM with nanofin transistors One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second... |
| US-9,892,797 |
Apparatuses and methods for charging a global access line prior to
accessing a memory Apparatuses and methods for charging a global access line prior to accessing a memory are described. An example apparatus may include a memory array of a... |
| US-9,892,784 |
Semiconductor device and error correction method A device with error correction is provided. The device includes a plurality of memory cells, and reference read write circuit, a plurality of sense amplifiers,... |
| US-9,892,780 |
Semiconductor memory device including output buffer An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power... |
| US-9,892,777 |
Cell-based reference voltage generation Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be initialized to a first... |
| US-9,892,776 |
Half density ferroelectric memory and operation Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory array may be operated in a half density mode, in which... |
| US-9,892,770 |
Methods and apparatuses for command shifter reduction Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit,... |
| US-9,892,767 |
Data gathering in memory Examples of the present disclosure provide apparatuses and methods for storing a first element in memory cells coupled to a first sense line and a plurality of... |
| US-9,892,766 |
Apparatuses and methods for performing logical operations using sensing
circuitry The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an... |
| US-9,891,864 |
Non-volatile memory module architecture to support memory error correction Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first... |
| US-9,891,842 |
Searching data in parallel using processor-in-memory devices A method includes comparing, in parallel, a data pattern with data stored into a plurality of columns of memory cells, and in response to detecting the data... |
| US-9,888,574 |
Apparatus and methods for via connection with reduced via currents Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first... |
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