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| Patent # | Description |
|---|---|
| US-1,005,6120 |
Interconnection for memory electrodes Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central... |
| US-1,005,5293 |
High performance memory controller A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an... |
| US-1,005,5285 |
Physical page, logical page, and codeword correspondence The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a... |
| US-1,005,5196 |
Division operations for memory Examples of the present disclosure provide apparatuses and methods for performing division operations in a memory. An example apparatus comprises a first... |
| US-1,005,5180 |
Printer setting state updating system The invention facilitates a setting state updating operation of the printer. An updating system of a setting state of a printer comprises an application... |
| US-1,005,0084 |
Replacement materials processes for forming cross point memory Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line... |
| US-1,005,0049 |
Apparatuses including memory arrays with source contacts adjacent edges of
sources Various apparatuses, including three-dimensional (3D) memory devices and systems including the same, are described herein. In one embodiment, a 3D memory device... |
| US-1,005,0023 |
Solid state lighting device with different illumination parameters at
different regions of an emitter array Solid state lighting (SSL) devices and methods of manufacturing such devices. One embodiment of an SSL device comprises a support and an emitter array having a... |
| US-1,004,9874 |
Self-assembled nanostructures including metal oxides and semiconductor
structures comprised thereof A self-assembled nanostructure comprises first domains and second domains. The first domains comprise a first block of a block copolymer material and an... |
| US-1,004,9756 |
Memory devices that apply a programming potential to a memory cell in a
string coupled to a source and data... A first string of memory cells, including a selected memory cell, and a second string of memory cells are coupled to a common data line and a common source. The... |
| US-1,004,9750 |
Methods including establishing a negative body potential in a memory cell Apparatus and methods of operating such apparatus include establishing a negative potential in a body of a memory cell prior to initiating a sensing operation... |
| US-1,004,9737 |
Memory cell architecture for multilevel cell programming Methods, systems, and devices for operating and forming a multilevel memory cell and array are described. A multilevel memory cell includes two or more binary... |
| US-1,004,9722 |
Apparatuses and methods for a memory device with dual common data I/O
lines Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O... |
| US-1,004,9721 |
Apparatuses and methods for in-memory operations The present disclosure includes apparatuses and methods for in-memory operations. An example apparatus includes a memory device including a plurality of... |
| US-1,004,9713 |
Full bias sensing in a memory array Methods, systems, and apparatuses for full bias sensing in a memory array are described. Various embodiments of an access operation of a cell in a array may be... |
| US-1,004,9707 |
Shifting data The present disclosure includes apparatuses and methods related to shifting data. A number of embodiments of the present disclosure include an apparatus... |
| US-1,004,9705 |
Memories having select devices between access lines and in memory cells
formed of a same type of circuit element Memories may include a first select device connected between a first access line and a second access line, and a plurality of memory cells. Each memory cell of... |
| US-1,004,9207 |
Methods of operating storage systems including encrypting a key salt A method of operating a storage system includes using the device driver to combine a password, the key salt, and the number of iterations to generate a primary... |
| US-1,004,9054 |
Virtual register file The present disclosure is related to a virtual register file. Source code can be compiled to include references to a virtual register file for data subject to a... |
| US-1,004,9038 |
Memory devices with register banks storing actuators that cause operations
to be performed on a memory core A bus controller has a displacer, an arithmetic logic unit coupled to the displacer, and a replacer selectively coupled to the displacer and the arithmetic... |
| US-1,004,8888 |
Apparatuses and methods for partitioned parallel data movement The present disclosure includes apparatuses and methods for partitioned parallel data movement. An example apparatus includes a memory device that includes a... |
| US-1,004,8887 |
Apparatuses and methods for single level cell caching Methods and apparatuses for single level cell caching are described. According to one example, a method includes receiving, at a memory device, a first set of... |
| US-1,004,8882 |
Non-volatile memory with LPDRAM Low power DRAM (LPDRAM) memory devices for communication with a non-volatile memory coupled to the LPDRAM memory device, and systems containing such LPDRAM and... |
| US-1,004,5452 |
Electronic device structures and methods of making Electronic device structures may include a sleeve member including a cavity extending from a first end of a body toward a second, opposite end, and an opening... |
| US-1,004,3769 |
Semiconductor devices including dummy chips A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first... |
| US-1,004,3688 |
Method for mount tape die release system for thin die ejection An apparatus, system, and a method of using the apparatus or system that includes a bladder positioned between tape and an adhesive layer configured to... |
| US-1,004,3587 |
Apparatuses and methods including nested mode registers Apparatuses and methods for nested mode registers to extend mode register functionality are disclosed. An example apparatus comprises a mode register configured... |
| US-1,004,3574 |
Programming memories with multi-level pass signal Methods of operating a memory include applying a first voltage level to control gates of a plurality of memory cells selected to be programmed while applying a... |
| US-1,004,3570 |
Signed element compare in memory Examples of the present disclosure provide apparatuses and methods for performing signed element compare operations. An apparatus can include a first group of... |
| US-1,004,3566 |
Array data bit inversion Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge... |
| US-1,004,3557 |
Apparatuses and methods for parallel I/O operations in a memory Apparatuses and methods for a multi-level communication architectures are disclosed herein. An example apparatus may include an input/output (I/O) circuit... |
| US-1,004,3556 |
Data shifting The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense... |
| US-1,004,3041 |
Multi-function, modular system for network security, secure communication,
and malware protection Representative embodiments are disclosed for providing network and system security. A representative apparatus includes an input-output connector coupleable to... |
| US-1,004,2789 |
Programming interruption management The present disclosure is related to programming interruption management. An apparatus can be configured to detect an interruption during a programming... |
| US-1,004,2755 |
3D vertical NAND memory device including multiple select lines and control
lines having different vertical spacing Some embodiments include apparatuses, and methods of forming and operating the apparatuses. Some of the apparatuses include a pillar including a length, a... |
| US-1,004,2750 |
Apparatuses and methods for adaptive control of memory using an adaptive
memory controller with a memory... Apparatuses and methods for adaptive control of memory are disclosed. One example apparatus includes a processing unit configured to run an operating system,... |
| US-1,004,2608 |
Signed division in memory Examples of the present disclosure provide apparatuses and methods for performing signed division operations. An apparatus can include a first group of memory... |
| US-1,003,8861 |
Method, apparatus, and system providing an imager with pixels having
extended dynamic range The dynamic range of a pixel is increased by using selective photosensor resets during a frame time of image capture at a timing depending on the light... |
| US-1,003,8523 |
Apparatuses and methods to change information values Some embodiments include apparatuses and methods having a component to change a value of a bit among a number of M bits of information when the M bits have the... |
| US-1,003,8008 |
Integrated structures and NAND memory arrays Some embodiments include an integrated structure having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include... |
| US-1,003,8002 |
Semiconductor devices and methods of fabrication Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a... |
| US-1,003,7983 |
Semiconductor device with modified current distribution Semiconductor devices having modified current distribution and methods of forming the same are described herein. As an example, a memory die in contact with a... |
| US-1,003,7926 |
Apparatus and methods for through substrate via test A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side... |
| US-1,003,7818 |
Switched interface stacked-die memory architecture Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request... |
| US-1,003,7809 |
Memory devices for reading memory cells of different memory planes Memory devices may include digital-to-analog converters configured to convert digital values to analog read voltages and to apply the analog read voltages to... |
| US-1,003,7807 |
Boosting channels of memory cells A method for programming a non-volatile memory device includes concurrently boosting channels of memory cells in a selected memory string and an unselected... |
| US-1,003,7806 |
Memory cell programming using VgVt value Methods of operating a memory include applying a programming pulse having a particular voltage level to a selected access line connected to selected memory... |
| US-1,003,7797 |
Programming memories with stepped programming pulses including inhibiting
a memory cell for a portion of a... Methods of operating a memory device include applying a programming pulse to a plurality of memory cells selected for programming having an initial portion... |
| US-1,003,7791 |
Apparatuses and methods for setting a signal in variable resistance memory An example of a method reads a spin torque transfer (STT) memory cell, and writes the STT memory cell using information obtained during the reading of the STT... |
| US-1,003,7786 |
Apparatuses and methods for converting a mask to an index The present disclosure includes apparatuses and methods related to converting a mask to an index. An example apparatus comprises an array of memory cells and... |
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