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| Patent # | Description |
|---|---|
| US-1,010,3290 |
Ultrathin solid state dies and methods of manufacturing the same Various embodiments of SST dies and solid state lighting ("SSL") devices with SST dies, assemblies, and methods of manufacturing are described herein. In one... |
| US-1,010,3196 |
Methods of forming magnetic memory cells, and methods of forming arrays of
magnetic memory cells Methods of forming a magnetic memory cell are disclosed. The method comprises forming a magnetic cell core material over a substrate, wherein forming the... |
| US-1,010,3160 |
Semiconductor structures including dielectric materials having differing
removal rates Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control... |
| US-1,010,3053 |
Methods of forming integrated circuitry Some embodiments include methods in which a structure has a first semiconductor material over a dielectric region, a second semiconductor material under the... |
| US-1,010,3038 |
Thrumold post package with reverse build up hybrid additive structure Semiconductor devices having a semiconductor die electrically coupled to a redistribution structure and a molded material over the redistribution structure are... |
| US-1,010,2914 |
Random telegraph signal noise reduction scheme for semiconductor memories Embodiments are provided that include a method including providing a first voltage to a selected memory cell and providing a second voltage to the selected... |
| US-1,010,2905 |
Memory cells having a plurality of resistance variable materials Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an... |
| US-1,010,1365 |
Semiconductor module, electrical connector, and inspection apparatus A semiconductor module includes a control IC mounted on a mounting substrate and a plurality of semiconductor chips mounted on the mounting substrate, and each... |
| US-1,009,7181 |
Apparatus and method for standby current control of signal path Apparatuses and methods for standby current control of a signal path in a semiconductor device are described. An example apparatus includes: first and second... |
| US-1,009,7169 |
Method and apparatus for reducing impact of transistor random mismatch in
circuits An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node,... |
| US-1,009,6748 |
Wavelength converters, including polarization-enhanced carrier capture
converters, for solid state lighting... Wavelength converters, including polarization-enhanced carrier capture converters, for solid state lighting devices, and associated systems and methods are... |
| US-1,009,6696 |
Field effect transistors having a fin An embodiment of a transistor has a semiconductor fin, a dielectric over the semiconductor fin, a control gate over the dielectric, and source/drains in the... |
| US-1,009,6655 |
Three dimensional memory array The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive... |
| US-1,009,6617 |
Three-dimensional structured memory devices A 3D structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain... |
| US-1,009,6579 |
Thermal pads between stacked semiconductor dies and associated systems and
methods Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the... |
| US-1,009,6576 |
Semiconductor device assemblies with annular interposers A semiconductor device package is provided. The package can include a stack of semiconductor dies over a substrate, the substrate including a plurality of... |
| US-1,009,6551 |
Electronic component of integrated circuitry and a method of forming a
conductive via to a region of... An electronic component of integrated circuitry comprises a substrate comprising at least two terminals. Material of one of the terminals has an upper surface.... |
| US-1,009,6483 |
Pitch reduction technology using alternating spacer depositions during the
formation of a semiconductor device... A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be... |
| US-1,009,6380 |
Erase page check Disclosed in some examples are methods, systems, memory devices, and machine readable mediums for performing an erase page check. For example, in response to an... |
| US-1,009,6370 |
Voltage degradation aware NAND array management Devices and techniques for voltage degradation aware NAND array management are disclosed herein. Voltage to a NAND device is monitored to detect a voltage... |
| US-1,009,6365 |
Erasable block segmentation for memory Various embodiments comprise apparatuses such as those having a block of memory divided into sub-blocks that share a common data line. Each of the sub-blocks of... |
| US-1,009,5574 |
Apparatuses and methods for comparing a current representative of a number
of failing memory cells Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current... |
| US-1,009,4988 |
Method of forming photonics structures The disclosed embodiments relate to an integrated circuit structure and methods of forming them in which photonic devices are formed on the back end of... |
| US-1,009,1031 |
Apparatus having a data receiver with a real time clock decoding decision
feedback equalizer Various embodiments include apparatus and methods having a data receiver with a real time clock decoding decision feedback equalizer. In various embodiments, a... |
| US-1,009,0837 |
Apparatus and methods for leakage current reduction in integrated circuits This disclosure relates to leakage current reduction in integrated circuits (ICs). In one aspect, an IC can include a digital logic circuit and a polarization... |
| US-1,009,0836 |
Methods and systems for averaging impedance calibration A semiconductor device also includes programmable termination components and a calibration circuit. The calibration circuit generates impedance calibration... |
| US-1,009,0759 |
Electronic device with a reconfigurable charging mechanism An electronic device includes a reconfigurable charge pump including pump units that can be arranged differently for varying an output voltage generated by the... |
| US-1,009,0507 |
Secondary battery-mounted circuit chip and manufacturing method thereof A secondary battery-mounted circuit chip wherein secondary battery is directly fabricated on opposed surface of formed circuit into an integrated structure of... |
| US-1,009,0464 |
Buried low-resistance metal word lines for cross-point variable-resistance
material memories Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer... |
| US-1,009,0462 |
Resistive memory devices Electronic apparatus, systems, and methods can include a resistive memory cell having a structured as an operably variable resistance region between two... |
| US-1,009,0457 |
Semiconductor devices with magnetic regions and stressor structures, and
methods of operation A magnetic cell core includes at least one stressor structure proximate to a magnetic region (e.g., a free region or a fixed region). The magnetic region may be... |
| US-1,009,0451 |
Methods and apparatus providing thermal isolation of photonic devices Described embodiments include photonic integrated circuits and systems with photonic devices, including thermal isolation regions for the photonic devices.... |
| US-1,009,0376 |
Methods of forming semiconductor device structures, and methods of forming
capacitor structures A method of forming a semiconductor device structure comprises forming a mold template comprising trenches within a mold material. Structures are formed within... |
| US-1,009,0346 |
Color filter array, imagers and systems having same, and methods of
fabrication and use thereof A pixel cell with a photosensitive region formed in association with a substrate, a color filter formed over the photosensitive region, the color filter... |
| US-1,009,0324 |
Three dimensional memory and methods of forming the same Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the... |
| US-1,009,0318 |
Vertical string of memory cells individually comprising a programmable
charge storage transistor comprising a... A method of forming a vertical string of memory cells comprises forming a lower stack comprising first alternating tiers comprising vertically-alternating... |
| US-1,009,0317 |
Methods and apparatuses having memory cells including a monolithic
semiconductor channel Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of... |
| US-1,009,0310 |
Memory devices having select gates with P type bodies, memory strings
having separate source lines and methods Memory devices and methods of operating memory devices are shown. Configurations described include a memory cell string having an elongated n type body region... |
| US-1,009,0283 |
Methods and systems for improving power delivery and signaling in stacked
semiconductor devices Semiconductor die assemblies including stacked semiconductor dies having parallel plate capacitors formed between adjacent pairs of semiconductor dies in the... |
| US-1,009,0282 |
Semiconductor device assemblies with lids including circuit elements A semiconductor device package is provided. The semiconductor device package includes a stack of semiconductor dies over a substrate, the substrate including a... |
| US-1,009,0177 |
Cold fluid semiconductor device release during pick and place operations,
and associated systems and methods Systems and methods for releasing semiconductor dies during pick and place operations are disclosed. In one embodiment, a system for handling semiconductor dies... |
| US-1,009,0064 |
Timing based arbiter systems and circuits for ZQ calibration Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips.... |
| US-1,009,0053 |
Apparatus, systems, and methods to operate a memory Various embodiments, disclosed herein, include apparatus and methods to read a logic level in a selected memory cell in a selected string of a memory by sensing... |
| US-1,009,0052 |
Sequential write and sequential write verify in memory device Some embodiments include apparatuses and methods for performing a first stage of an operation of storing information in a first memory cell and a second memory... |
| US-1,009,0051 |
Memory array with power-efficient read architecture Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings... |
| US-1,009,0050 |
Apparatuses and methods including memory access in cross point memory Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch... |
| US-1,009,0026 |
Apparatuses and methods for providing internal memory commands and control
signals in semiconductor memories In an example apparatus, a command path receives read commands and provides respective control signals for each read command. The command path is configured to... |
| US-1,009,0024 |
Memory device including current generator plate Some embodiments include an apparatus and methods using a first conductive material located in a first level of an apparatus (e.g., a memory device); a second... |
| US-1,008,9359 |
Memory devices for pattern matching Memory devices for facilitating pattern matching and having an array of memory cells, a plurality of key registers to store a representation of a key word, and... |
| US-1,008,9250 |
State change in systems having devices coupled in a chained configuration The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of... |
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