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Patent # Description
US-1,023,6049 Power reduction for a sensing operation of a memory cell
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may leverage non-volatile memory properties of a...
US-1,023,6040 Two-step data-line precharge scheme
Apparatus and methods are disclosed, including an apparatus having a first transistor configured to be coupled to a first bit line, and a control circuit...
US-1,023,6039 Apparatuses and methods for chip identification in a memory package
Apparatuses, methods, memory packages, and semiconductor chips are disclosed. An example apparatus includes a semiconductor chip including a layer...
US-1,023,6038 Bank to bank data transfer
The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an...
US-1,023,6037 Data transfer in sensing components
Examples of the present disclosure provide apparatuses and methods related to performing a loop structure for operations performed in memory. An example...
US-1,023,6036 Sense amplifier signal boost
Apparatuses for signal boost are disclosed An example apparatus includes: first and second digit lines coupled to memory cells; a sense amplifier including:...
US-1,023,5627 Adaptive content inspection
Methods and apparatus are provided involving adaptive content inspection. In one embodiment, a content inspection processor may identify information with...
US-1,022,9923 Integrated assemblies and methods of forming integrated assemblies
Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with...
US-1,022,9922 Methods of forming memory devices with isolation structures
A first conductive region having a second conductivity type is formed in a first semiconductor over a first dielectric isolation region and having a first...
US-1,022,9890 Compensating for memory input capacitance
Methods, systems, and devices for compensating for memory input capacitance. Techniques are described herein to alter the capacitance of an access line coupled...
US-1,022,9874 Arrays of memory cells individually comprising a capacitor and a transistor and methods of forming such arrays
An array of memory cells individually comprising a capacitor and a transistor comprises, in a first level, alternating columns of digitlines and conductive...
US-1,022,9730 Timing control circuit shared by a plurality of banks
Apparatuses and methods for providing activation timings of sense amplifiers in a semiconductor device are described. An example apparatus includes: a first...
US-1,022,9728 Oscillator controlled random sampling method and circuit
Various embodiments comprise methods and apparatuses for selecting a randomly-chosen seed row from among a stream of available data in a memory system. A...
US-1,022,9727 Apparatus and method for controlling erasing data in ferroelectric memory cells
Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example...
US-1,022,8853 Advanced memory interfaces and methods
Controllers, interfaces, memory devices, methods and systems are disclosed, including a controller configured to interface with a separate memory device and...
US-1,022,6845 Machine tool
A machine tool capable of facilitating a process of mounting a fluid supplying unit to a spindle supporting unit is provided. The machine tool has a rotating...
US-1,022,4313 Interconnect structures with intermetallic palladium joints and associated systems and methods
Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes...
US-1,021,8342 System and method for duty cycle correction
Apparatuses and methods for correcting a duty cycle of a clock signal are described. An example apparatus includes: a duty cycle corrector (DCC) that receives...
US-1,021,8340 Adjustable delay circuit for optimizing timing margin
The present invention relates to timing margin adjustment circuits using adjustable delay circuits. An example adjustable delay circuit may include a signal...
US-1,021,7936 Apparatuses including electrodes having a conductive barrier material and methods of forming same
Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus...
US-1,021,7753 Memory cells
A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor...
US-1,021,7726 Stacked semiconductor dies including inductors and associated methods
Several embodiments of the present technology are directed to semiconductor devices, systems including semiconductor devices, and methods of making and...
US-1,021,7719 Semiconductor device assemblies with molded support substrates
Semiconductor device assemblies with molded support substrates and associated methods are disclosed herein. In one embodiment, a semiconductor device assembly...
US-1,021,7706 Semiconductor constructions
Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the...
US-1,021,7569 Devices comprising a capacitor and support material that laterally supports the capacitor
A device includes a capacitor that has first and second electrodes having a capacitor insulator there-between. The first electrode is elongated and extends...
US-1,021,7525 Memory apparatus with post package repair
Apparatuses for memory repair for a memory device are described. An example apparatus includes: a non-volatile storage element that stores information; a...
US-1,021,7524 Autorecovery after manufacturing/system integration
Methods of managing systems comprising a processor and a memory device external to the processor, including exposing the memory device to temperature levels...
US-1,021,7499 Modified decode for corner turn
Examples of the present disclosure provide apparatuses and methods for performing a corner turn using a modified decode. An example apparatus can comprise an...
US-1,021,6438 Methods and related devices for operating a memory array
Methods of operating memory arrays, as well as the memory arrays, are described. In various embodiments, a method includes determining a pattern to be written...
US-1,021,6213 Methods and apparatuses including a process, voltage, and temperature independent current generator circuit
Apparatuses, methods, and current generators that generate current are described. An example apparatus includes a current source configured to provide a...
US-1,021,5921 Method and structure providing optical isolation of a waveguide on a silicon-on-insulator substrate
Disclosed are a method and structure providing a silicon-on-insulator substrate on which photonic devices are formed and in which a core material of a waveguide...
US-1,021,5801 Contact inspection device having a probe head and rotation restricting portions
A contact inspection device includes: plural probes each having a first end to be brought into contact with a test object; a probe substrate including contact...
US-1,021,5500 Semiconductor device assembly with vapor chamber
Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one...
US-1,021,1832 Input buffer circuit
An example apparatus according to an embodiment of the disclosure includes first and second voltage terminals, and first, second, and third circuit nodes. A...
US-1,021,1725 Electronic device with a charging mechanism
An electronic device includes: a clock booster including a doubler capacitor, the clock booster configured to precharge the doubler capacitor and provide a...
US-1,021,1724 Electronic device with an output voltage booster mechanism
An electronic device includes: a clock booster configured to generate a boosted intermediate voltage greater than a source voltage, wherein the clock booster...
US-1,021,1114 Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
Microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a packaged microelectronic device can include an...
US-1,021,0940 Memory read apparatus and methods
Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential,...
US-1,021,0928 Apparatuses including current compliance circuits and methods
Apparatus, devices, systems, and methods are described that include variable state material data storage. Example devices include current compliance circuits...
US-1,021,0922 Apparatus and methods for refreshing memory cells of a semiconductor device
Apparatuses and methods for refreshing memory cells of a semiconductor device are described. An example apparatus includes: a memory cell array including a...
US-1,021,0918 Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase...
Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal are disclosed. An example apparatus...
US-1,021,0911 Apparatuses and methods for performing logical operations using sensing circuitry in a memory device
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an...
US-1,020,9449 Photonics grating coupler and method of manufacture
A structure for coupling an optical signal between an integrated circuit photonic structure and an external optical fiber is disclosed as in a method of...
US-1,020,5451 Methods and apparatuses for dynamic step size for impedance calibration of a semiconductor device
Methods and apparatuses are provided for dynamic step size for impedance calibration of a semiconductor device. An example apparatus includes a resistor, and a...
US-1,020,4667 Methods of determining host clock frequency for run time optimization of memory and memory devices employing...
A memory device is provided. The memory device includes one or more memories and a connector operably coupled to the one or more memories and configured to...
US-1,020,4666 Input buffer circuit
Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes: a first amplifier that provides first and...
US-1,020,4663 Methods and apparatuses for compensating for source voltage
Apparatuses and methods for compensating for source voltage are described. An example apparatus includes a source cooled to a memory cell and a read-write...
US-1,020,3885 Memory device including mixed non-volatile memory cell types
Some embodiments include apparatuses, and methods of forming and operating the apparatuses. Some of the apparatuses include a conductive line, non-volatile...
US-1,020,2583 Arrays of memory cells individually comprising a capacitor and an elevationally-extending transistor, methods...
A method of forming a tier of an array of memory cells within an array area, the memory cells individually comprising a capacitor and an elevationally-extending...
US-1,019,9363 Semiconductor memory device including output buffer
A semiconductor module includes a module substrate, a line pattern provided to the module substrate, first and second semiconductor chips on the module...
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