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| Patent # | Description |
|---|---|
| US-9,985,076 |
Diode/superionic conductor/polymer memory structure A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second... |
| US-9,985,049 |
Arrays of elevationally-extending strings of memory cells and methods of
forming memory arrays An array of elevationally-extending strings of memory cells comprises a vertical stack of alternating insulative levels and wordline levels. The wordline levels... |
| US-9,985,040 |
Integrated circuitry and 3D memory Integrated circuitry has an array circuitry region having a repeating array of electronic components. An adjacent circuitry region is immediately laterally... |
| US-9,985,000 |
Stacked semiconductor die assemblies with die support members and
associated systems and methods Stacked semiconductor die assemblies with die support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die... |
| US-9,984,977 |
Semiconductor constructions Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the... |
| US-9,984,756 |
Fast programming memory device In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one... |
| US-9,979,915 |
Pixel array with shared pixels in a single column and associated devices,
systems, and methods Pixel array with shared pixels in a single column and associated devices, systems, and methods are disclosed herein. In one embodiment, a pixel array includes a... |
| US-9,977,902 |
Enabling a secure boot from non-volatile memory A system may include a host that may include a processor coupled to a non-volatile memory over a secure communication protocol. As a result, prior to release... |
| US-9,977,603 |
Memory devices for detecting known initial states and related methods and
electronic systems A memory device includes a memory array having non-volatile memory cells, and a memory controller configured to detect a known state to enter based, at least in... |
| US-9,975,206 |
Composition of solid-containing paste Solder paste compositions and methods for applying solder paste. The solder paste includes lubricating additives to the flux to decrease friction and the... |
| US-9,974,965 |
Relay module for implant An implementation provides a system that includes: a control module including a first antenna, the control module configured to generate a first radio frequency... |
| US-9,973,719 |
Antiblooming imaging apparatus, systems, and methods Apparatus, systems, and methods are described to assist in reducing dark current in an active pixel sensor. In various embodiments, a potential barrier... |
| US-9,973,181 |
Synchronized semiconductor device with phase adjustment circuit According to one embodiment, a synchronous semiconductor device is disclosed According to this embodiment, the synchronous semiconductor device includes a pulse... |
| US-9,972,862 |
Secondary battery Provided is a secondary battery in which a single-layer secondary cell has an all-solid-state secondary cell structure with a storage layer sandwiched between a... |
| US-9,972,770 |
Methods of forming memory cells, arrays of magnetic memory cells, and
semiconductor devices Magnetic memory cells, methods of fabrication, semiconductor device structures, and memory systems are disclosed. A magnetic cell core includes at least one... |
| US-9,972,628 |
Conductive structures, wordlines and transistors Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 eV, and a second conductive... |
| US-9,972,532 |
Interconnect structures for integrated circuits and their formation An embodiment of an interconnect structure for an integrated circuit may include a first conductor coupled to circuitry, a second conductor, a dielectric... |
| US-9,972,391 |
Apparatus, systems, and methods to operate a memory Various embodiments, disclosed herein, include apparatus and methods to read a logic level in a selected memory cell in a selected string of a memory by sensing... |
| US-9,972,367 |
Shifting data in sensing circuitry The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises sensing circuitry including a sense amplifier... |
| US-9,972,363 |
Apparatus for impedance adjustment and methods of their operation Apparatus include a data bus and a signal driver circuit having pluralities of first and second termination devices connected in parallel between a voltage node... |
| US-9,971,541 |
Apparatuses and methods for data movement The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays... |
| US-9,971,536 |
Controller to manage NAND memories Various embodiments disclose a controller to manage memory devices. In an exemplary method, signals are exchanged with a host processor to allow the host... |
| US-9,966,451 |
Integrated structures Some embodiments include an integrated structure having a vertical stack of alternating insulative levels and conductive levels. Recesses extend into the... |
| US-9,966,406 |
Semiconductor devices including back-side integrated circuitry Semiconductor devices may include a semiconductor substrate comprising at least one of transistors and capacitors may be located at an active surface of the... |
| US-9,966,347 |
Under-bump metal structures for interconnecting semiconductor dies or
packages and associated systems and methods The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package... |
| US-9,966,127 |
Compensating for variations in selector threshold voltages Methods, systems, and devices are described for operating a memory array. A first voltage may be applied to a memory cell to activate a selection component of... |
| US-9,966,116 |
Apparatuses and methods for storing a data value in a sensing circuitry
element The present disclosure includes apparatuses and methods related to storing a data value in a sensing circuitry element. An example method comprises sensing a... |
| US-9,960,346 |
Magnetic tunnel junctions A magnetic tunnel junction has a conductive first magnetic electrode comprising magnetic recording material. A conductive second magnetic electrode is spaced... |
| US-9,960,258 |
Methods of forming transistor gates Some embodiments include methods of forming charge storage transistor gates and standard FET gates in Which common processing is utilized for fabrication of at... |
| US-9,960,150 |
Semiconductor device assembly with through-mold cooling channel formed in
encapsulant Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one... |
| US-9,960,148 |
Methods for transferring heat from stacked microfeature devices Methods and apparatuses for transferring heat from stacked microfeature devices are disclosed herein. In one embodiment, a microfeature device assembly... |
| US-9,960,114 |
Structure of integrated circuitry and a method of forming a conductive via A method of forming a conductive via comprises forming a structure comprising an elevationally-extending-conductive via and a conductive line electrically... |
| US-9,960,094 |
Packaged semiconductor components having substantially rigid support
members and methods of packaging... Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member... |
| US-9,959,931 |
Programming a memory device in response to its program history A method includes determining, internal to a memory device, a number of program pulses required to program a sample of memory cells of the memory device during... |
| US-9,959,929 |
Memory device and method having on-board processing logic for facilitating
interface with multiple processors,... A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating... |
| US-9,959,923 |
Apparatuses and methods to reverse data stored in memory Apparatuses and methods are provided for reversing data stored in memory. An example apparatus comprises an array of memory cells, a first plurality of sensing... |
| US-9,959,921 |
Apparatuses and methods for refresh control Apparatuses and methods of for refresh control of a semiconductor device are described. An example apparatus includes a command control circuit that provides a... |
| US-9,959,913 |
Apparatuses and methods for performing logical operations using sensing
circuitry The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an... |
| US-9,959,732 |
Method and system for fall detection The present disclosure provides a method and a system for fall detection. Measurement signals are received from a plurality of sensors to monitor user... |
| US-9,959,474 |
Bus translator Disclosed are methods and devices, among which is a device including a bus translator. In some embodiments, the device also includes a core module and a core... |
| US-9,959,220 |
Memory tile access and selection patterns In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile... |
| US-9,958,887 |
Device having internal voltage generating circuit A device includes an amplifying circuit having first and second input terminals and an output terminal, a ground terminal, a variable resistance circuit, and a... |
| US-9,958,624 |
Apparatus providing simplified alignment of optical fiber in photonic
integrated circuits A structure for optically aligning an optical fiber to a protonic device and method of fabrication of same. The structure optically aligns an optical fiber to... |
| US-9,954,517 |
Apparatuses and methods for duty cycle adjustment Apparatuses, duty cycle adjustment circuits, adjustment circuits, and methods for duty cycle adjustment are disclosed herein. An example duty cycle adjustment... |
| US-9,954,437 |
Charge pump One charge pump includes at least one delay element, a number of inverters, and a flip flop coupled in series, with an output of one inverter coupled in a... |
| US-9,954,075 |
Thyristor random access memory device and method Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased... |
| US-9,953,842 |
Methods of forming a portion of a memory array having a conductor having a
variable concentration of germanium An embodiment of a method of forming a portion of a memory array includes forming a conductor with a concentration of germanium that decreases with an... |
| US-9,953,724 |
Memory devices and methods for managing error regions Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for... |
| US-9,953,718 |
Programming memory cells to be programmed to different levels to an
intermediate level from a lowest level First memory cells are programmed to an intermediate level from a lowest level, corresponding to a lowest data state, where the first memory cells are to be... |
| US-9,953,711 |
Methods of operating memory under erase conditions Methods of operating a memory include applying a first voltage level to a first semiconductor material of a first conductivity type forming a channel region for... |
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