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Arrays of memory cells and methods of forming an array of memory cells
An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced...
Magnetic tunnel junctions
A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material. A conductive second magnetic electrode is...
Double gated fin transistors and methods of fabricating and operating the
A semiconductor device is provided that includes a fin having a first upper gate on a sidewall of the fin in a first trench and a second upper gate formed on...
Vertically base-connected bipolar transistor
Methods, devices, and systems for using and forming vertically base-connected bipolar transistors have been shown. The vertically base-connected bipolar...
Memory cell profiles
Examples of the present disclosure provide devices and methods for processing a memory cell. A method embodiment includes removing a key-hole shaped column from...
Process for improving critical dimension uniformity of integrated circuit
Methods for patterning integrated circuit (IC) device arrays employing an additional mask process for improving center-to-edge CD uniformity are disclosed. In...
Forming a memory device using sputtering to deposit silver-selenide film
A method of sputter depositing silver selenide and controlling the stoichiometry and nodular defect formations of a sputter deposited silver-selenide film. The...
Autorecovery after manufacturing/system integration
Memory devices storing particular data, systems containing such memory devices and methods of testing such memory devices. The memory devices include an array...
Methods, devices, and systems for data sensing
Methods and devices for data sensing are disclosed. One such method includes performing a number of successive sense operations on a number of memory cells...
Descending set verify for phase change memory
Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.
Apparatuses and methods for sensing using an integration component
The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include circuitry to provide a...
Semiconductor device including subword driver circuit
The present invention is provided with: subword drivers SWD for driving subword lines SWL, a selection circuit for supplying either negative potential VKK1 or...
Offset compensation for ferroelectric memory cell sensing
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Offsets in the threshold voltage of switching components (e.g.,...
STT-MRAM cell structure incorporating piezoelectric stress material
A magnetic memory cell including a piezoelectric material, and methods of operating the memory cell are provided. The memory cell includes a stack, and the...
Memory timing self-calibration
Methods for memory input timing self-calibration, apparatuses for input timing self-calibration, and systems are disclosed. One such method includes...
Method for assigning addresses to memory devices
A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an...
Memory cell coupling compensation
Methods for memory cell coupling compensation and apparatuses configured to perform the same are described. One or more methods for memory cell coupling...
Devices containing metal chalcogenides
Some embodiments include a device having a conductive material, a metal chalcogenide-containing material, and a region between the metal chalcogenide-containing...
Integrated memory and methods of forming repeating structures
Some embodiments include integrated memory having an array of repeating plates across a plurality of nodes. The array includes rows and columns. The plates...
Magnetic memory cells and methods of formation
Memory cells including cell cores having free regions are disclosed. The free regions exhibit a strain that affects a magnetization orientation within the cell...
Apparatuses and operation methods associated with resistive memory cell
arrays with separate select lines
The present disclosure includes methods and apparatuses that include resistive memory. A number of embodiments include a first memory cell coupled to a data...
Solid state lights with thermal control elements
A solid state light ("SSL"), a solid state emitter ("SSE"), and methods of manufacturing SSLs and SSEs. In one embodiment, an SSL comprises a packaging...
Systems and methods for water purification
An evaporator assembly includes an inlet member and a diffuser, and receives a mixture of a gas and a solution to vaporize a portion of a solvent from the...
Computerized apparatus with a high speed data bus
A computerized apparatus configured for high-speed data transactions between components thereof. In one embodiment, the computerized apparatus includes a...
Apparatuses and methods for duty cycle adjustment
Apparatuses and methods for duty cycle adjustment are disclosed herein. An example apparatus may include a node, a phase mixer, and a duty cycle adjuster...
Magnetic memory cells and methods of fabrication
A magnetic cell includes a magnetic tunnel junction that comprises magnetic and nonmagnetic materials exhibiting hexagonal crystal structures. The hexagonal...
Dual work function recessed access device and methods of forming
A recessed access device having a gate electrode formed of two or more gate materials having different work functions may reduce the gate-induced drain leakage...
Semiconductor device packages with improved thermal management and related
Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. The stack...
External gettering method and device
Disclosed embodiments include external gettering provided by electronic packaging. An external gettering element for a semiconductor substrate, which may be...
Memory array plane select
Memory arrays and methods of forming the same are provided. An example memory array can include at least one plane having a plurality of memory cells arranged...
Determining soft data for combinations of memory cells
The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of...
The present disclosure includes methods and systems for channel skewing. One or more methods for channel skewing includes providing a number of groups of data...
Efficient operations of components in a wireless communications device
Various embodiments comprise apparatuses and methods including a communications subsystem having an interface module and a protocol module with the...
Memory device using extended interface commands
A memory device includes a serial interface buffer that receives a hardware-decodable command and an extended interface command. The memory device also includes...
Stacked memory devices, systems, and methods
Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more...
Ear tag for recognizing livestock individual
An ear tag for recognizing livestock individual is provided. The ear tag for recognizing livestock individual according to the present invention includes a...
Structures for resistance random access memory and methods of forming the
Memory cells and methods of forming the same and devices including the same. The memory cells have first and second electrodes. An amorphous semiconductor...
Magnetic tunnel junctions
Some embodiments include a magnetic tunnel junction comprising magnetic reference material having an iridium-containing region between a multi-layer stack and a...
Semiconductor device comprising a transistor gate having multiple
vertically oriented sidewalls
A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention...
Interfacial materials for use in semiconductor structures and related
A method of forming a semiconductor structure. The method comprises forming a high-k dielectric material, forming a continuous interfacial material over the...
Conductive structures, systems and devices including conductive structures
and related methods
Conductive structures include a plurality of conductive steps and a contact extending at least partially therethrough in communication with at least one of the...
Electronic devices and methods of manufacturing electronic devices
Disclosed are a foldable and spreadable electronic device and a method of manufacturing the electronic device. The electronic device may include a flexible...
Apparatuses and methods to control body potential in memory operations
Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line...
Methods and apparatuses for determining threshold voltage shift
Apparatuses and methods for determining threshold voltage shift are described. A number of methods for determining threshold voltage shift in memory cells...
Staggered DLL clocking on N-Detect QED to minimize clock command and delay
Apparatuses and methods are described for meeting timing and latency requirements using staggered clocking within the command path. In one example, an apparatus...
Enable/disable of memory chunks during memory access
Apparatuses and methods involving accessing memory cells are described. In one such method, chunks of memory cells in a memory array are enabled to be accessed...
Conditional operation in an internal processor of a memory device
An internal processor of a memory device configured to selectively execute instructions in parallel. One such internal processor includes a plurality of...
Methods and systems for routing in a state machine
A device includes a routing buffer. The routing buffer includes a first port configured to receive a signal relating to an analysis of at least a portion of a...
Inspection apparatus and inspection method
An inspection apparatus for inspecting an inspection object. The inspection object includes a base body and wiring passing through the base body. The inspection...
Electric connecting apparatus
An apparatus includes a wiring base plate arranged on an upper side of a chuck top and having a wiring path connected to a tester, a probe card having a probe...