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| Patent # | Description |
|---|---|
| US-9,696,920 |
Systems and methods for improving efficiencies of a memory system A memory device includes a memory component that store data. The memory device also includes a processor that receives a signal indicating that the memory... |
| US-9,692,455 |
Multi channel memory with flexible code-length ECC Apparatuses and methods for error correction and detection of data from memory on a plurality of channels are described. An example apparatus includes: a first... |
| US-9,691,955 |
Solid state lighting devices with improved contacts and associated methods
of manufacturing Solid state lighting ("SSL") devices with improved contacts and associated methods of manufacturing are disclosed herein. In one embodiment, an SSL device... |
| US-9,691,817 |
Magnetic tunnel junctions and methods of forming magnetic tunnel junctions A method of forming a line of magnetic tunnel junctions includes forming magnetic recording material over a substrate, non-magnetic material over the recording... |
| US-9,691,744 |
Semiconductor memory device including output buffer A semiconductor module includes a module substrate, a line pattern provided to the module substrate, first and second semiconductor chips on the module... |
| US-9,691,465 |
Thyristors, methods of programming thyristors, and methods of forming
thyristors Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV... |
| US-9,691,443 |
Apparatuses and methods for compensating for process, voltage, and
temperature variation in a memory Systems and methods are described for compensating for variations in process, voltage, temperature, or combinations thereof in an apparatus. An example... |
| US-9,690,961 |
Systems and methods to determine kinematical parameters using RFID tags Systems and methods to determine kinematical parameters of physical objects using radio frequency identification (RFID) tags attached to the objects. In one... |
| US-9,690,653 |
Semiconductor device having error correction code (ECC) circuit An apparatus may comprise an ECC circuit configured to receive read data from a memory cell array to correct, an error bit contained in a data portion of the... |
| US-9,690,502 |
Systems and methods for segmenting data structures in a memory system A memory device may include a memory component that stores data and a processor. The processor may map one or more banks or one or more virtual banks in the... |
| US-9,685,448 |
Semiconductor device Disclosed herein is a method includes: forming first and second cavities, the first cavity having a first width, each of the second cavities having a second... |
| US-9,685,234 |
Apparatuses and methods for performing multiple memory operations The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory... |
| US-9,679,964 |
Semiconductor constructions having peripheral regions with spaced apart
mesas Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy... |
| US-9,679,852 |
Semiconductor constructions Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the... |
| US-9,676,944 |
Methods of increasing the solubility of materials in supercritical carbon
dioxide Methods of increasing the solubility of a base in supercritical carbon dioxide include forming a complex of a Lewis acid and the base, and dissolving the... |
| US-9,672,908 |
Apparatuses and methods of reading memory cells based on response to a
test pulse The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to memory arrays and methods of... |
| US-9,666,245 |
Device having multiple channels with calibration circuit shared by
multiple channels An apparatus includes a first channel, a second channel and a calibration circuit. The first channel includes a first command control circuit. The second... |
| US-9,665,301 |
Methods and devices for storing user data along with addresses
corresponding to physical pages storing valid data Methods, and corresponding devices, for storing user data along with a plurality of addresses corresponding to physical pages storing valid data corresponding... |
| US-9,665,083 |
Counter operation in a state machine lattice Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting... |
| US-9,659,630 |
Multi-mode memory device and method having stacked memory dice, a logic
die and a command processing circuit... Memory device systems, systems and methods are disclosed, such as those involving a plurality of stacked memory device dice and a logic die connected to each... |
| US-9,659,420 |
Security system of information processing apparatus and security control
apparatus In a security system, a security control apparatus 300 includes an authentication processing unit 31 for perform an authentication on whether the mobile... |
| US-9,653,647 |
Ultrathin solid state dies and methods of manufacturing the same Various embodiments of SST dies and solid state lighting ("SSL") devices with SST dies, assemblies, and methods of manufacturing are described herein. In one... |
| US-9,653,307 |
Surface modification compositions, methods of modifying silicon-based
materials, and methods of forming high... A surface modification composition comprising a silylation agent comprising a silyl acetamide, a silylation catalyst comprising a perfluoro acid anhydride, an... |
| US-9,653,171 |
Partial page memory operations Apparatuses may include a memory block with strings of memory cells formed in a plurality of tiers. The apparatus may further comprise access lines and data... |
| US-9,653,143 |
Apparatuses including memory section control circuits with global drivers Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a... |
| US-9,647,167 |
Solid-state radiation transducer devices having flip-chip mounted
solid-state radiation transducers and... Solid-state radiation transducer (SSRT) devices and methods of manufacturing and using SSRT devices are disclosed herein. One embodiment of the SSRT device... |
| US-9,646,899 |
Interconnect assemblies with probed bond pads An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The... |
| US-9,646,875 |
Methods of forming memory arrays Some embodiments include methods of forming memory arrays. An assembly is formed which has an upper level over a lower level. The lower level includes... |
| US-9,646,869 |
Semiconductor devices including a diode structure over a conductive strap
and methods of forming such... Semiconductor devices including at least one diode over a conductive strap. The semiconductor device may include at least one conductive strap over an insulator... |
| US-9,646,702 |
Operating memory devices to apply a programming potential to a memory cell
in a string coupled to a source and... Methods of biasing in memory devices facilitate memory device programming operations. In at least one embodiment, a first string of memory cells comprising a... |
| US-9,646,689 |
Refresh architecture and algorithm for non-volatile memories Methods and systems to refresh a nonvolatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device... |
| US-9,646,683 |
Memory apparatus, systems, and methods Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the... |
| US-9,646,662 |
Apparatuses, circuits, and methods for biasing signal lines Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled... |
| US-9,645,919 |
Memory systems and methods including training, data organizing, and/or
shadowing Described embodiments include memory systems that may shadow certain data stored in a first memory device (e.g. NAND flash device) onto a second memory device... |
| US-9,645,102 |
Material test structure Material test structures having cantilever portions and methods of forming the same are described herein. As an example, a method of forming a material test... |
| US-9,642,294 |
Tape feeder and method for moving a carrier tape towards a picking
position in a component mounting machine A tape feeder, including a tape feeder body and a feeder wagon/linear guide, is used to direct component tape in a linear movement towards a component pick... |
| US-9,641,068 |
Voltage generator circuit Embodiments are provided that include a circuit for generating voltage in a memory. One such circuit includes a charge pump circuit including a first... |
| US-9,640,271 |
Low-dropout regulator peak current control A low-dropout regulator includes an error amplifier to provide a control signal, a first transistor, and a second transistor. The first transistor receives the... |
| US-9,640,227 |
System and method of command based and current limit controlled memory
device power up Devices and systems for powering up a memory device, for example, are disclosed. One such memory device includes power up circuitry configured to receive an... |
| US-9,639,420 |
High performance memory controller A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an... |
| US-9,633,988 |
Apparatuses and methods of communicating differential serial signals
including charge injection Apparatuses and methods are disclosed, including an apparatus that includes a differential driver with charge injection pre-emphasis. One such apparatus... |
| US-9,633,748 |
Multi-channel testing Apparatus and methods can include an interface chip that can include a test channel to couple to a memory tester, a memory channel controller to couple with a... |
| US-9,627,251 |
Forming array contacts in semiconductor memories Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks... |
| US-9,627,067 |
Erasable block segmentation for memory Various embodiments comprise apparatuses such as those having a block of memory divided into sub-blocks that share a common data line. Each of the sub-blocks of... |
| US-9,627,052 |
Apparatuses and methods for current limitation in threshold switching
memories Apparatuses and methods are described herein for limiting current in threshold switching memories. In an example, an apparatus may include a plurality of first... |
| US-9,621,032 |
Generation of voltages Voltage generation circuits are useful in the generation of internal voltages for use in integrated circuits. Voltage generation circuits may include a stage... |
| US-9,620,675 |
Solid state lighting devices with reduced crystal lattice dislocations and
associated methods of manufacturing Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a substrate... |
| US-9,614,516 |
Devices for shielding a signal line over an active region A multi-path transistor includes an active region including a channel region and an impurity region. A gate is dielectrically separated from the channel region.... |
| US-9,614,497 |
Semiconductor device and method for adjusting impedance of output circuit An impedance adjustment circuit includes a counter circuit outputting a count value thereof as a plurality of first impedance adjustment signals, a mode... |
| US-9,614,153 |
Methods of selectively doping chalcogenide materials and methods of
forming semiconductor devices Methods of selectively forming a metal-doped chalcogenide material comprise exposing a chalcogenide material to a transition metal solution, and incorporating... |
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