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State grouping for element utilization
Embodiments of a system and method for generating an image configured to program a parallel machine from source code are disclosed. One such parallel machine...
Subject matter disclosed herein relates to techniques to perform transactions using a memory device.
Circuits, apparatuses, and methods for address scrambling
Circuits, apparatuses, and methods are disclosed for address scrambling in integrated circuits. One example apparatus includes a plurality of data regions, each...
Memory system controller
The present disclosure includes methods and devices for a memory system controller. In one or more embodiments, a memory system controller includes a host...
Wear leveling for a memory device
Memory devices and methods to facilitate wear leveling operations in a memory device. In one such method, particular blocks of memory cells are excluded from...
Substrates and methods of forming a pattern on a substrate
Substrates and methods of forming a pattern on a substrate. The pattern includes a repeating pattern region and a pattern-interrupting region adjacent to the...
Apparatus and methods for leakage current reduction in integrated circuits
This disclosure relates to leakage current reduction in integrated circuits (ICs). In one aspect, an IC can include a digital logic circuit and a polarization...
Packaged integrated circuit devices with through-body conductive vias, and
methods of making same
A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at...
Microfeature workpieces having interconnects and conductive backplanes,
and associated systems and methods
Microfeature workpieces having interconnects and conductive backplanes and associated systems and methods are disclosed herein. One such device includes a...
Semiconductor constructions, methods of forming conductive structures and
methods of forming DRAM cells
Some embodiments include methods of forming conductive structures. An electrically conductive material may be deposited with a first deposition method. The...
Semiconductor with through-substrate interconnect
Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor...
Conductive interconnect structures incorporating negative thermal
expansion materials and associated systems,...
Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device...
Polishing systems and methods for removing conductive material from
Polishing systems and methods for removing conductive material (e.g., noble metals) from microelectronic substrates are disclosed herein. Several embodiments of...
Integrated circuit structure having arrays of small, closely spaced
Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can...
Pitch multiplication spacers and methods of forming the same
Spacers in a pitch multiplication process are formed without performing a spacer etch. Rather, the mandrels are formed over a substrate and then the sides of...
Method providing an epitaxial growth having a reduction in defects and
Disclosed are methods and resulting structures which provide an opening for epitaxial growth, the opening having an associated projection for reducing the size...
Field emission devices and methods for making the same
The present disclosure includes field emission device embodiments. The present disclosure also includes method embodiments for forming field emitting devices....
Methods and devices for memory reads with precharged data lines
Methods of operating memory devices including precharging an adjacent pair of data lines to a particular voltage, isolating one data line of the adjacent pair...
Drift acceleration in resistance variable memory
The present disclosure includes apparatuses and methods including drift acceleration in resistance variable memory. A number of embodiments include applying a...
Secure compact flash
Methods and apparatus are provided, such as a memory card with a processor and nonvolatile memory coupled thereto. The nonvolatile memory has a secure area...
Chip stack device testing method, chip stack device rearranging unit, and
chip stack device testing apparatus
A plurality of chip stack devices having different external sizes can be tested accurately and efficiently with low cost. The present invention provides a chip...
Methods of utilizing block copolymer to form patterns
Some embodiments include methods of forming patterns. A block copolymer film may be formed over a substrate, with the block copolymer having an intrinsic glass...
Multilayer wiring board and method for manufacturing the same
Provided is a method for manufacturing a multi-layer wiring board and the multi-layer wiring board that are capable of suppressing variation in resistance...
Methods of forming memory cells, and methods of patterning
Some embodiments include methods of forming memory cells. Chalcogenide is formed over a plurality of bottom electrodes, and top electrode material is formed...
Incorporation of oxygen into memory cells
Electronic apparatus, systems, and methods include a resistive random access memory cell having an oxygen gradient in a variable resistive region of the...
Solid state lighting devices without converter materials and associated
methods of manufacturing
Solid state lighting devices that can produce white light without a phosphor are disclosed herein. In one embodiment, a solid state lighting device includes a...
Nonvolatile memory cells and arrays of nonvolatile memory cells
A nonvolatile memory cell includes first and second electrodes. Programmable material and a select device are received in series between and with the first and...
Methods of forming doped regions in semiconductor substrates
Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first...
Techniques for providing a semiconductor memory device
Techniques for providing a semiconductor memory device are disclosed. In one embodiment, the techniques may be realized as a semiconductor memory device...
Forming high aspect ratio isolation structures
An isolation structure, such as a trench isolation structure, may be formed by forming an aperture in a semiconductor substrate and then filling the aperture...
Sensing memory cells
The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to...
Multiple data line memory and methods
Apparatuses and methods are disclosed, including an apparatus with rows of vertical strings of memory cells coupled to a common source and multiple data lines...
Phase change memory adaptive programming including pulse transition time
Some embodiments include methods and apparatus having a module configured to program a memory cell using a signal to cause the memory cell to have a programmed...
Bus width negotiation
There is provided a method and apparatus for bus negotiation. One such method includes determining a configuration of a first bond pad, the first bond pad...
Non-volatile memory device capable of initiating transactions
A non-volatile memory may operate, not in a master/slave arrangement, but in a peer-to-peer arrangement. In some embodiments, the memory may initiate a...
Plasma processing with preionized and predissociated tuning gases and
associated systems and methods
Plasma processing systems and methods for using pre-dissociated and/or pre-ionized tuning gases are disclosed herein. In one embodiment, a plasma processing...
Optical writer for flexible foils
The technology disclosed relates to patterning of flexible substrate. One implementation can be applied for production of flexible displays and other electronic...
Reduced crosstalk sensor and method of formation
Isolation methods and devices for isolating regions of a semiconductor device are disclosed. The isolation methods and structures include forming an isolating...
System and method for updating read-only memory in smart card memory
A storage device contains a smart-card device and a memory device, both connected to a controller. The storage device may be used in the same manner as a...
Codewords that span pages of memory
The present disclosure includes apparatuses and methods for codewords that span pages of memory. A number of methods include writing a first portion of a...
GCIB-treated resistive device
The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods...
Vertical devices and methods of forming
Vertical devices and methods of forming the same are provided. One example method of forming a vertical device can include forming a trench in a semiconductor...
Methods of forming graphene-containing switches
Some embodiments include methods of forming graphene-containing switches. A bottom electrode may be formed over a base, and a first electrically conductive...
Methods of forming charge storage structures including etching diffused
regions to form recesses
Methods are disclosed that include selectively etching diffused regions to form recesses in semiconductor material, and forming charge storage structures in the...
DRAM with nanofin transistors
One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second...
Devices including fin transistors robust to gate shorts and methods of
making the same
Disclosed are methods, systems and devices, including a method that includes the acts of etching an inter-row trench in a substrate, substantially or entirely...
Methods of forming an array of openings in a substrate, and related
methods of forming a semiconductor device...
A method of forming an array of openings in a substrate. The method comprises forming a template structure comprising a plurality of parallel features and a...
Two-part programming methods
Programming a memory in two parts to reduce cell disturb is disclosed. In at least one embodiment, data is programmed in two or more sequences of programming...
Memory apparatus, systems, and methods
Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the...
Devices and methods to program a memory cell
Subject matter disclosed herein relates to memory devices and, more particularly, to programming a memory cell.