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Apparatuses, sense circuits, and methods for compensating for a wordline
Apparatuses, sense circuits, and methods for compensating for a voltage increase on a wordline in a memory is described. An example apparatus includes a...
Non-volatile memory programming
Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying voltages to data lines...
Program and read trim setting
A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device...
Reactive metal implanted oxide based memory
Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell...
Non-volatile memory including reference signal path
Some embodiments include apparatuses and methods having a first memory element and a first select component coupled to the first memory element, a second memory...
Power savings mode for memory systems
A system and method are disclosed to accomplish power savings in an electronic device, such as a memory chip, by performing selective frequency locking and...
Molding compound including a carbon nano-tube dispersion
A molding compound comprising a resin, a filler, and a carbon nano-tube dispersion is disclosed. The carbon nano-tube dispersion achieves a low average...
Integrated circuitry comprising transistors with broken up active regions
Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second...
Methods for forming a string of memory cells and apparatuses having a
vertical string of memory cells including...
Methods for forming a string of memory cells and apparatuses having a vertical string of memory cells are disclosed. One such string of memory cells can be...
Methods of forming vertical field effect transistors, vertical field
effect transistors, and DRAM cells
A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the...
Solid state lighting devices with cellular arrays and associated methods
Solid state lighting ("SSL") devices with cellular arrays and associated methods of manufacturing are disclosed herein. In one embodiment, a light emitting...
Methods of forming single crystal silicon structures and semiconductor
device structures including single...
A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon...
Semiconductor constructions and methods of forming semiconductor
Some embodiments include methods in which first insulative material is formed across a memory region and a peripheral region of a substrate. An etch stop...
Compacted air flow rapid fluid evaporation system
A total water desalination system is disclosed that includes a centrifugal separator, a feed-water device controlled by a relative humidity sensor, an air pump,...
Magnetically adjusting color-converting materials within a matrix and
associated devices, systems, and methods
Magnetically adjusting color-converting particles within a matrix and associated devices, systems, and methods are disclosed herein. A magnetic-adjustment...
Flexible circuit for an implantable neural stimulator
Code patching for non-volatile memory
Example embodiments described herein may comprise a transfer of firmware execution within a non-volatile memory device to one or more replacement instructions...
Booting in systems having devices coupled in a chained configuration
The present disclosure includes methods, devices, and systems for booting in systems having devices coupled in a chained configuration. One or more embodiments...
Password accessible microelectronic memory
A microelectronic memory may be password access protected. A controller may maintain a register with requirements for accessing particular memory locations to...
Validating persistent memory content for processor main memory
Subject matter disclosed herein relates to validating memory content in persistent main memory of a processor.
Memory cell sensing using a boost voltage
The present disclosure includes devices, methods, and systems including memory cell sensing using a boost voltage. One or more embodiments include pre-charging...
Strings of memory cells having string select gates, memory devices
incorporating such strings, and methods of...
Strings of memory cells having a string select gate configured to selectively couple ends of a string to a data line and a source line concurrently, memory...
Arrays of vertically stacked tiers of non-volatile cross point memory
An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers...
Memory cell operation
Methods, devices, and systems associated with memory cell operation are described. One or more methods of operating a memory cell include charging a capacitor...
Arrays of vertically-oriented transistors, memory arrays including
vertically-oriented transistors, and memory...
An array includes a plurality of vertically-oriented transistors, rows of access lines, and columns of data/sense lines. Individual of the rows include an...
Efficient pitch multiplication process
Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated...
Methods of selectively removing a substrate material
A method for selective removing material from a substrate without damage to copper filling a via and extending at least partially through the substrate. The...
Methods of exposing conductive vias of semiconductor devices and
Methods of exposing conductive vias of semiconductor devices may comprise conformally forming a barrier material over conductive vias extending from a backside...
Semiconductor substrate for photonic and electronic structures and method
A method of forming a substrate with isolation areas suitable for integration of electronic and photonic devices is provided. A common reticle and...
Methods of forming a nonvolatile memory cell and methods of forming an
array of nonvolatile memory cells
A method of forming a nonvolatile memory cell includes forming a first electrode and a second electrode of the memory cell. Sacrificial material is provided...
Methods of forming patterns
Some embodiments include methods of forming patterns of openings. The methods may include forming spaced features over a substrate. The features may have tops...
Active memory command engine and method
A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or...
Memory arbitration system and method having an arbitration packet protocol
A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub....
Memory device and method having on-board address protection system for
facilitating interface with multiple...
A memory device includes an address protection system that facilitates the ability of the memory device to interface with a plurality of processors operating in...
Methods of operating a memory system that include outputting a data
pattern from a sector allocation table to a...
A method of operating a memory system includes receiving a read command from a host, where the read command is associated with a logical sector of a memory,...
Programming memory cells
Methods for programming memory cells. One such method for programming memory cells includes generating an encoded stream using a data stream and programming the...
Memory device with pin register to set input/output direction and bitwidth
of data signals
A random access memory includes a data signal line, a data-synchronization signal line for a data synchronization signal which provides a synchronization signal...
Method and apparatus for pre-charging data lines in a memory cell array
Memories, pre-charge circuits, and methods for pre-charging memory are described. One such method includes providing a voltage to a data line and adjusting the...
Apparatuses and methods including memory array data line selection
Some embodiments include an apparatus having data lines coupled to memory cell strings and a selector configured to selectively couple one of the data lines to...
Adjusting program and erase voltages in a memory device
A system and apparatus for adjusting threshold program and erase voltages in a memory array, such as a floating gate memory array, for example. One such method...
Threshold voltage compensation in a multilevel memory
Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the...
Systems and methods to determine kinematical parameters using RFID tags
Systems and methods to determine kinematical parameters of physical objects using radio frequency identification (RFID) tags attached to the objects. In one...
Antiblooming imaging apparatus, systems, and methods
Apparatus, systems, and methods are described to assist in reducing dark current in an active pixel sensor. In various embodiments, a potential barrier...
Solid state lighting devices having improved color uniformity and
Solid state lighting (SSL) devices and methods of manufacturing SSL devices are disclosed herein. In one embodiment, an SSL device comprises a support having a...
Methods of forming a metal telluride material, related methods of forming
a semiconductor device structure, and...
Accordingly, a method of forming a metal chalcogenide material may comprise introducing at least one metal precursor and at least one chalcogen precursor into a...
Phase change memory including ovonic threshold switch with layered
electrode and methods for forming the same
Erosion of chalcogenides in phase change memories using ovonic threshold switch selectors can be reduced by controlling columnar morphology in electrodes used...
Semiconductor constructions and methods of planarizing across a plurality
of electrically conductive posts
Some embodiments include a planarization method. A liner is formed across a semiconductor substrate and along posts that extending upwardly from the substrate....
Charge-trap based memory
Methods of fabricating 3D charge-trap memory cells are described, along with apparatus and systems that include them. In a planar stack formed by alternate...
Memory with guard value dependent error correction
Embodiments of the present disclosure provide methods, systems, and apparatuses related to calculating an error correction code for a program page dependent on...
Physical page, logical page, and codeword correspondence
The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a...