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Managing defective areas of memory
Methods of operating a memory, and memories for performing such methods, include determining that a particular area of the memory is defective, locating a free...
Pattern-recognition processor with matching-data reporting module
Disclosed are methods and devices, among which is a device that includes a pattern-recognition processor. The pattern-recognition processor may include a...
Apparatus and methods to provide power management for memory devices
An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated...
Metallization scheme for integrated circuit
For multi-level interconnect metallization, each metal level maintains a parallel line arrangement within a region, and the lines of each adjacent metal level...
Memory device with reduced neighbor memory cell disturbance
In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes a memory cell, digit line driver, access line driver, clamping...
Method for kink compensation in a memory
This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory...
Voltage generation and adjustment in a memory device
Voltage generation devices and methods are useful in determining a data state of a selected memory cell in a memory device. Voltages can be generated in...
Block-row decoders, memory block-row decoders, memories, methods for
deselecting a decoder of a memory and...
Block-row decoders, memory block-row decoders, memories, methods for deselecting a decoder of a memory and methods of selecting a block of memory are disclosed....
Cross-point memory devices, electronic systems including cross-point
memory devices and methods of accessing a...
Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row)...
Selective self-reference read
This disclosure relates to selectively performing a read with increased accuracy, such as a self-reference read, from a memory. In one aspect, data is read from...
Vertical transistor phase change memory
Vertical transistor phase change memory and methods of processing phase change memory are described herein. One or more methods include forming a dielectric on...
Horizontally oriented and vertically stacked memory cells
Horizontally oriented and vertically stacked memory cells are described herein. One or more method embodiments include forming a vertical stack having a first...
Methods of forming a plurality of covered voids in a semiconductor
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
Methods for forming a conductive material and methods for forming a
A method of forming a conductive material comprises forming at least one opening extending through an organic material and an insulative material underlying the...
Methods for depositing material onto microfeature workpieces in reaction
chambers and systems for depositing...
Methods for depositing material onto microfeature workpieces in reaction chambers and systems for depositing materials onto microfeature workpieces are...
Memory device and method with on-board cache system for facilitating
interface with multiple processors, and...
A memory device includes an on-board cache system that facilitates the ability of the memory device to interface with a plurality of processors operating in a...
Control path I/O virtualisation
There is disclosed a data switch in combination with a proxy controller, the data switch being configured for routing data traffic and control traffic between...
Techniques for accessing memory cells
Techniques for accessing memory cells are disclosed. In one particular embodiment, the techniques may be realized as an apparatus providing voltage to a high...
Data shifting via a number of isolation devices
The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense...
Apparatus and methods for a physical layout of simultaneously
sub-accessible memory modules
A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality...
Method and system for minimizing number of programming pulses used to
program rows of non-volatile memory cells
A flash memory device programs cells in each row in a manner that minimizes the number of programming pulses that must be applied to the cells during...
Biasing system and method
Embodiments are provided that include a memory system that includes a memory system, having an access device coupled between a global line and a local line and...
Methods of operating memory devices
Methods of operating a memory device include determining whether each memory cell selected for a sense operation has any data state of a first subset of data...
Techniques for providing a semiconductor memory device
Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor...
State determination in resistance variable memory
An evaluation signal is applied to a memory cell in an array of resistance variable memory cells. The evaluation signal is configured to cause the memory cell...
Semiconductor module system having encapsulated through wire interconnect
A semiconductor module system includes a module substrate and a semiconductor substrate having a through wire interconnect bonded to an electrode on the module...
Memory devices having reduced interference between floating gates and
methods of fabricating such devices
A memory array comprising transistors having isolated inter-gate dielectric regions with respect to one another. Transistors are formed such that each of the...
Method for manufacturing probe card
A method for manufacturing a probe card includes inserting an attaching portion of each probe into one of first through holes provided on a probe substrate at...
Method for manufacturing probe card
A method for manufacturing a probe card prepares a plurality of probes, each having a metal layer on an attaching portion, and hot-melt material covering the...
Autonomous memory subsystem architecture
An autonomous sub-system receives a database downloaded from a host controller. A controller monitors bus traffic and/or allocated resources in the subsystem...
Active memory data compression system and method
An integrated circuit active memory device receives task commands from a component in a host computer system that may include the active memory device. The host...
Memory controllers, memory systems, solid state drives and methods for
processing a number of commands
The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end...
Self-calibrating continuous-time equalization
Embodiments of the invention comprise a continuous-time equalizer for reducing ISI in data received from a communication channel, and methods and circuitry for...
Sense amplifier having loop gain control
Memories, sense amplifiers, and methods for amplifying a current input are disclosed, including a sense amplifier including a bias circuit configured to provide...
Through wire interconnect (TWI) for semiconductor components having wire
in via and bonded connection with...
A through wire interconnect for a semiconductor substrate includes a via extending through the semiconductor substrate from the first side to the second side...
Methods and compositions for etching polysilicon including aqueous compositions containing nitric acid and ammonium fluoride, and apparatus formed thereby.
Gallium nitride wafer substrate for solid state lighting devices, and
associated systems and methods
Gallium nitride wafer substrate for solid state lighting devices, and associated systems and methods. A method for making an SSL device substrate in accordance...
Integrity of an address bus
A method for improving address integrity in a memory system generates error correction data corresponding to a memory address. The error correction data is...
Error correction and recovery in chained memory architectures
Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a memory unit configured to receive data...
Serial flash memory with a configurable number of dummy clock cycles
Apparatus and methods configure a serial flash memory device. A value in a configuration register configures the number of dummy clock cycles to provide prior...
Method and apparatus for field firmware updates in data storage systems
Data storage devices and methods for updating firmware are disclosed. For example, one such data storage device includes a device firmware and a controller,...
Loading trim address and trim data pairs
Methods of loading trim address and trim data pairs to a trim register array, and apparatus configured to perform such methods. The methods maintain a...
Sub-block disabling in 3D memory
Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of...
Methods for programming a memory device and memory devices
Methods for programming memory cells and memory devices are disclosed. One such method for programming includes performing a program verify operation of a group...
Memory devices with different sized blocks of memory cells and methods
In an embodiment, each block of a plurality of blocks includes a respective plurality of strings of memory cells, where each of the plurality of strings of a...
Complementary decoding for non-volatile memory
Decoding and decoder circuits in memory devices are disclosed. Array lines are biased or floated as memory device operations are performed in the memory device....
Memory cells, semiconductor device structures, systems including such
cells, and methods of fabrication
Memory cells including cell cores having free regions are disclosed. The free regions exhibit a strain that affects a magnetization orientation within the cell...
Semiconductor structures and devices
Methods of forming semiconductor structures that include bodies of a semiconductor material disposed between rails of a dielectric material are disclosed. Such...
Semiconductor structure including a zirconium oxide material
Semiconductor structures including a zirconium oxide material and methods of forming the same are described herein. As an example, a semiconductor structure can...
Memory cells, semiconductor devices including such cells, and methods of
Memory cells are disclosed, which cells include a cell material and an ion-source material over the cell material. A discontinuous interfacial material is...