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Patent # Description
US-9,129,848 Method and structure for integrating capacitor-less memory cell with logic
Methods for fabricating integrated circuits include fabricating a logic device on a substrate, forming an intermediate semiconductor substrate on a surface of...
US-9,129,847 Transistor structures and integrated circuitry comprising an array of transistor structures
This invention includes a capacitorless one transistor DRAM cell that includes a pair of spaced source/drain regions received within semiconductive material. An...
US-9,129,845 Buried low-resistance metal word lines for cross-point variable-resistance material memories
Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer...
US-9,129,837 Semiconductor device
A semiconductor device has an active region defined by a device isolation region arranged on a surface of a semiconductor substrate, a plurality of transistor...
US-9,129,798 Methods of forming semiconductor structures comprising aluminum oxide
A semiconductor structure comprising aluminum oxide. The semiconductor structure comprises a dielectric material overlying a substrate. The aluminum oxide...
US-9,129,694 Slew rate modulation
Apparatus and methods may operate so that arrival times of a data signal at gates of transistors are controlled to switch the transistors at different times to...
US-9,129,684 Dynamic program window determination in a memory device
A memory device has an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to determine a program window...
US-9,129,662 Circuits, devices, systems, and methods of operation for capturing data signals
Embodiments of the invention describe driving data onto a bus. The embodiments include a data driver circuit having a data capture circuit coupled to the bus....
US-9,128,894 Bus controller
A bus controller has a displacer, an arithmetic logic unit coupled to the displacer, and a replacer selectively coupled to the displacer and the arithmetic...
US-9,128,869 Systems and methods involving managing a problematic memory cell
Methods and apparatus are provided for identifying which symbol within a codeword corresponds to an information state read from a problematic memory cell. A...
US-9,128,762 Persistent content in nonvolatile memory
Applications may request persistent storage in nonvolatile memory. The persistent storage is maintained across power events and application instantiations....
US-9,128,637 Logical unit operation
The present disclosure includes methods and devices for logical unit operation. One device embodiment includes a number of logical units, wherein each of the...
US-9,128,383 Sub-resolution assist devices and methods
Photolithographic apparatus, systems, and methods that make use of sub-resolution assist devices are disclosed. In the various embodiments, an imaging mask...
US-9,124,301 Error correction code for unidirectional memory
A memory array and a method of writing to a unidirectional non-volatile storage cell are disclosed whereby a user data word is transformed to an internal data...
US-9,124,253 Methods and apparatuses for duty cycle preservation
Methods and apparatuses are disclosed for preserving duty cycle at voltage domain boundaries. One example apparatus includes a complement generation circuit...
US-9,124,174 DC-DC converter switching transistor current measurement technique
A method is described comprising conducting a first current through a switching transistor. The method also comprises conducting a second current through a pair...
US-9,123,891 Diode for variable-resistance material memories, processes of forming same, and methods of using same
A variable-resistance material memory (VRMM) device includes a container conductor disposed over an epitaxial semiconductive prominence that is coupled to a...
US-9,123,888 Memory cells and memory cell arrays
Some embodiments include memory cells. The memory cells may have a first electrode, and a trench-shaped programmable material structure over the first...
US-9,123,786 Interconnect line selectively isolated from an underlying contact plug
A means for selectively electrically connecting an electrical interconnect line, such as a bit line of a memory cell, with an associated contact stud and...
US-9,123,722 Semiconductor constructions and methods of forming interconnects
Some embodiments include methods of forming interconnects. A first circuitry level may be formed, and a first dielectric region may be formed over such first...
US-9,123,700 Integrated circuit constructions having through substrate vias and methods of forming integrated circuit...
An integrated circuit construction includes a stack of two or more integrated circuit substrates. At least one of the substrates includes through substrate vias...
US-9,123,552 Apparatuses enabling concurrent communication between an interface die and a plurality of dice stacks,...
Various embodiments include apparatuses, stacked devices and methods of forming dice stacks on an interface die. In one such apparatus, a dice stack includes at...
US-9,123,423 Programming operations in a memory device
Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a...
US-9,123,415 Methods of operating a phase change memory cell
A PCRAM cell has a gradated or layered resistivity bottom electrode with higher resistivity closer to a phase change material, to provide partial heating near...
US-9,123,414 Memory systems and memory programming methods
Memory systems and memory programming methods are described. According to one aspect, a memory system includes program circuitry configured to provide a program...
US-9,123,409 Memory device for a hierarchical memory architecture
A hierarchical memory device having multiple interfaces with different memory formats includes a Phase Change Memory (PCM). An input port and an output port...
US-9,123,405 Multiple device apparatus, systems, and methods
Apparatus, systems, and methods are disclosed that operate to generate a clock signal in a die in a stack and to receive the clock signal in another die in the...
US-9,122,420 Memory devices having special mode access
A memory device includes a memory array, a special mode enable register, and a controller. When the controller receives a register write command to write first...
US-9,122,168 Lithography method and device
Lithography methods and devices are shown that include a semiconductor structure such as a mask. Methods and devices are shown that include a pattern of mask...
US-9,121,869 Probe assembly, probe card including the same, and methods for manufacturing these
Quality of connection portions between respective probes and respective wires in a probe assembly is improved. Also, time required for work for connection...
US-9,120,091 Nanoparticle positioning technique
Embodiments of the present invention are generally directed to a method for disposing nanoparticles on a substrate. In one embodiment, a substrate having a...
US-9,118,327 Boolean logic in a state machine lattice
Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic...
US-9,118,004 Memory cells and methods of forming memory cells
Some embodiments include methods of forming memory cells. Programmable material may be formed directly adjacent another material. A dopant implant may be...
US-9,117,998 Nonvolatile memory cells and methods of forming nonvolatile memory cells
A method of forming a nonvolatile memory cell includes forming a first electrode having a first current conductive material and a circumferentially self-aligned...
US-9,117,928 Cross-point diode arrays and methods of manufacturing cross-point diode arrays
Methods of forming an array of memory cells and memory cells that have pillars. Individual pillars can have a semiconductor post formed of a bulk semiconductor...
US-9,117,766 Method for positioning spacers in pitch multiplication
Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers...
US-9,117,744 Methods of forming a span comprising silicon dioxide
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
US-9,117,553 Memory block quality identification in a memory device
If a memory block in a flash memory device is found to have a defect, a memory block quality indication is generated in response to the type of memory defect....
US-9,117,524 Adjusting operational parameters for memory cells
Techniques and devices relating to adjusting one or more operational parameters for memory cells are provided. One such device may include a detection unit...
US-9,117,519 Methods, devices and systems using over-reset state in a memory cell
Memory cells, devices and methods are disclosed, including those that involve applying a waveform to a resistive memory cell to program the memory cell to an...
US-9,117,504 Volume select for affecting a state of a non-selected memory volume
Apparatuses and methods of operating memory are described. One such method can include receiving a select command at a plurality of memory volumes of a memory...
US-9,117,503 Memory array plane select and methods
Memory arrays and methods of forming the same are provided. An example memory array can include at least one plane having a plurality of memory cells arranged...
US-9,116,837 Pinning content in nonvolatile memory
Systems and methods relating to pinning selected data to sectors in non-volatile memory. A graphical user interface allows a user to specify certain data (e.g.,...
US-9,116,828 Data bus inversion usable in a memory system
Implementations of Data Bus Inversion (DBI) techniques within a memory system are disclosed. In one embodiment, a set of random access memory (RAM) integrated...
US-9,116,822 Stopping criteria for layered iterative error correction
The present disclosure includes apparatuses and methods related to stopping criteria for layered iterative error correction. A number of methods can include...
US-9,116,800 Block-based storage device with a memory-mapped interface
Described herein are methods for accessing a block-based storage device having a memory-mapped interface and a block interface. In one embodiment, an apparatus...
US-9,116,625 Write command overlap detection
The present disclosure includes methods and apparatuses that include write command overlap detection. A number of embodiments include receiving an incoming...
US-9,116,174 Electrical connecting apparatus and method for assembling the same
An electrical connecting apparatus includes a wiring base plate having a first surface coupled with a reinforcing plate and provided on an opposite surface with...
US-9,116,169 Method for aligning plate-like members and method for manufacturing electrical connecting apparatus
One plate-like member and the other plate-like member to be aligned with each other are provided with guide holes and guide portions to be received in the guide...
US-9,113,546 Method for manufacturing electric film body
A method for manufacturing an electric film body is made by forming a film body to have a shape in accordance with a desired electric characteristic and...
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