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Patent # Description
US-9,093,311 Techniques for providing a semiconductor memory device
Techniques for providing a semiconductor memory device are disclosed. In one embodiment, the techniques may be realized as a semiconductor memory device...
US-9,093,266 Forming high aspect ratio isolation structures
An isolation structure, such as a trench isolation structure, may be formed by forming an aperture in a semiconductor substrate and then filling the aperture...
US-9,093,162 Sensing memory cells
The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to...
US-9,093,152 Multiple data line memory and methods
Apparatuses and methods are disclosed, including an apparatus with rows of vertical strings of memory cells coupled to a common source and multiple data lines...
US-9,093,142 Phase change memory adaptive programming including pulse transition time adjustment
Some embodiments include methods and apparatus having a module configured to program a memory cell using a signal to cause the memory cell to have a programmed...
US-9,092,388 Bus width negotiation
There is provided a method and apparatus for bus negotiation. One such method includes determining a configuration of a first bond pad, the first bond pad...
US-9,092,387 Non-volatile memory device capable of initiating transactions
A non-volatile memory may operate, not in a master/slave arrangement, but in a peer-to-peer arrangement. In some embodiments, the memory may initiate a...
US-9,090,460 Plasma processing with preionized and predissociated tuning gases and associated systems and methods
Plasma processing systems and methods for using pre-dissociated and/or pre-ionized tuning gases are disclosed herein. In one embodiment, a plasma processing...
US-9,090,095 Optical writer for flexible foils
The technology disclosed relates to patterning of flexible substrate. One implementation can be applied for production of flexible displays and other electronic...
US-RE45,633 Reduced crosstalk sensor and method of formation
Isolation methods and devices for isolating regions of a semiconductor device are disclosed. The isolation methods and structures include forming an isolating...
US-9,088,418 System and method for updating read-only memory in smart card memory modules
A storage device contains a smart-card device and a memory device, both connected to a controller. The storage device may be used in the same manner as a...
US-9,088,303 Codewords that span pages of memory
The present disclosure includes apparatuses and methods for codewords that span pages of memory. A number of methods include writing a first portion of a...
US-9,087,989 GCIB-treated resistive device
The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods...
US-9,087,895 Vertical devices and methods of forming
Vertical devices and methods of forming the same are provided. One example method of forming a vertical device can include forming a trench in a semiconductor...
US-9,087,874 Methods of forming graphene-containing switches
Some embodiments include methods of forming graphene-containing switches. A bottom electrode may be formed over a base, and a first electrically conductive...
US-9,087,737 Methods of forming charge storage structures including etching diffused regions to form recesses
Methods are disclosed that include selectively etching diffused regions to form recesses in semiconductor material, and forming charge storage structures in the...
US-9,087,730 DRAM with nanofin transistors
One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second...
US-9,087,721 Devices including fin transistors robust to gate shorts and methods of making the same
Disclosed are methods, systems and devices, including a method that includes the acts of etching an inter-row trench in a substrate, substantially or entirely...
US-9,087,699 Methods of forming an array of openings in a substrate, and related methods of forming a semiconductor device...
A method of forming an array of openings in a substrate. The method comprises forming a template structure comprising a plurality of parallel features and a...
US-9,087,600 Two-part programming methods
Programming a memory in two parts to reduce cell disturb is disclosed. In at least one embodiment, data is programmed in two or more sequences of programming...
US-9,087,594 Memory apparatus, systems, and methods
Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the...
US-9,087,583 Devices and methods to program a memory cell
Subject matter disclosed herein relates to memory devices and, more particularly, to programming a memory cell.
US-9,087,578 Configurable reference current generation for non volatile memory
This disclosure relates to generating a reference current for a memory device. In one aspect, a non-volatile memory device, such as a phase change memory...
US-9,087,570 Apparatuses and methods for controlling a clock signal provided to a clock tree
Apparatuses, sense circuits, and methods for controlling a clock signal to a clock tree is described. An example apparatus includes a consecutive write command...
US-9,087,025 Data encoding using spare channels in a memory system
Implementations of encoding techniques are disclosed. The encoding technique, such as a Data bus Inversion (DBI) technique, is implementable in a...
US-9,086,983 Apparatus and methods for providing data integrity
The present disclosure includes apparatus (e.g., computing systems, memory systems, controllers, etc.) and methods for providing data integrity. One or more...
US-9,084,360 Electronic device assemblies including conductive vias having two or more conductive elements
Electronic devices include a substrate with first and second pairs of conductive traces extending in or on the substrate. A first conductive interconnecting...
US-9,083,575 Devices having different effective series resistance states and methods for controlling such devices
Devices and methods are described, such as those including parallel paths coupled between a first power supply and a second power supply. The parallel paths...
US-9,083,358 Delay lock loop phase glitch error filter
A method and apparatus is provided for providing a phase glitch error filter for a delay lock loop. The device comprises a delay lock loop to provide an output...
US-9,082,969 Keyhole-free sloped heater for phase change memory
Subject matter disclosed herein relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of fabricating...
US-9,082,966 Methods of forming semiconductor devices and structures with improved planarization, uniformity
Semiconductor devices and structures, such as phase change memory devices, include peripheral conductive pads coupled to peripheral conductive contacts in a...
US-9,082,956 Confined cell structures and methods of forming confined cell structures
Techniques for reducing damage in memory cells are provided. Memory cell structures are typically formed using dry etch and/or planarization processes which...
US-9,082,829 Methods for forming arrays of small, closely spaced features
Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can...
US-9,082,783 Semiconductor device and fabrication method thereof
The semiconductor device fabrication method of the present invention includes: laminating a plurality of amorphous silicon films on a semiconductor substrate,...
US-9,082,772 Stair step formation using at least two masks
Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a...
US-9,082,748 Devices, systems, and methods related to removing parasitic conduction in semiconductor devices
Semiconductor devices and methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes...
US-9,082,721 Structures comprising masks comprising carbon
The critical dimension (CD) of features formed during the fabrication of a semiconductor device may be controlled through the use of a dry develop chemistry...
US-9,082,692 Engineered substrate assemblies with epitaxial templates and related systems, methods, and devices
Engineered substrates having epitaxial templates for forming epitaxial semiconductor materials and associated systems and methods are disclosed herein. In...
US-9,082,555 Structure comprising multiple capacitors and methods for forming the structure
Capacitors, apparatus including a capacitor, and methods for forming a capacitor are provided. One such capacitor may include a first conductor a second...
US-9,082,494 Memory cells having a common gate terminal
Arrays of memory cells having a common gate terminal and methods of operating and forming the same are described herein. As an example, an array of memory cells...
US-9,082,485 Apparatuses and methods including memory array and data line architecture
Some embodiments include apparatus and methods having memory cells located in different device levels of a device, at least a portion of a transistor located in...
US-9,082,477 Set pulse for phase change memory programming
A memory device and method for programming the memory device, including a method for a melting phase change memory cell by applying an electronic signal at a...
US-9,082,474 Method and apparatus for providing preloaded non-volatile memory content
An embodiment providing one or more improvements includes a memory loading system and method for at least managing testing of a memory unit using a memory test...
US-9,082,471 Power saving memory apparatus, systems, and methods
Some embodiments include a voltage generator to generate a voltage to apply to a line used to access a memory cell of a memory device in which the voltage is...
US-9,082,466 Apparatuses and methods for adjusting deactivation voltages
Apparatuses and methods for adjusting deactivation voltages are described herein. An example apparatus may include a voltage control circuit. The voltage...
US-9,081,718 Systems and methods for storing and recovering controller data in non-volatile memory devices
Systems and methods are disclosed for storing the firmware and other data of a flash memory controller, such as using a RAID configuration across multiple flash...
US-9,081,717 Memory quality monitor based compensation method and apparatus
In one embodiment, an encoder reads a set of data from memory cells to obtain retrieved data influenced by one or more distortion mechanisms as a result of...
US-9,081,674 Dual mapping between program states and data patterns
The present disclosure includes methods and apparatuses for dual mapping between program states and data patterns. One apparatus includes a memory and a...
US-9,081,042 Resistive memory element sensing using averaging
A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled...
US-9,079,436 Printing apparatus with cutter mechanism
A movable BF guide is provided in a movable-blade receiving area into which a movable blade slides along a fixed blade while being pressed against the fixed...
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