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N-type field effect transistors, arrays comprising N-type
vertically-oriented transistors, methods of forming...
An n-type field effect transistor includes silicon-comprising semiconductor material comprising a pair of source/drain regions having a channel region...
Gaseous compositions comprising hydrogen fluoride and an alkylated ammonia
A method of removing at least a portion of a silicon oxide material is disclosed. The silicon oxide is removed by exposing a semiconductor structure comprising...
Methods of forming a substrate opening
A method of forming a substrate opening includes forming a plurality of side-by-side openings in a substrate. At least some of immediately adjacent side-by-side...
Photonic device structure and method of manufacture
Disclosed method and apparatus embodiments provide a photonic device with optical isolation from a supporting substrate. A generally rectangular cavity in cross...
Methods for integrated circuit fabrication with protective coating for
Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction...
Data security for digital data storage
A computing system includes data encryption in the data path between a data source and data storage devices. The data storage devices may be local or they may...
Apparatuses and methods for adjusting a path delay of a command path
Apparatuses and method for adjusting a path delay of a command path are disclosed. In an example apparatus, a command path configured to provide a command from...
Sub-block decoding in 3D memory
Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of...
Memory cell sensing
This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first memory cell coupled to a first data line,...
Encoding program bits to decouple adjacent wordlines in a memory device
Subject matter disclosed herein relates to memory operations regarding encoding program bits to be programmed into a memory array.
Method and apparatuses for programming memory cells
Methods and apparatus for programming memory cells in a memory array are disclosed. A most recent programming time is determined, the most recent programming...
Performing forming processes on resistive memory
The present disclosure includes apparatuses and methods for performing forming processes on resistive memory. A number of embodiments include applying a...
Memory device interface methods, apparatus, and systems
Apparatus and systems for memory system are provided. In an example, an interface chip can include a memory controller configured to couple to a processor and...
Food source information transferring system and method for a meat-packing
A food source information transferring system for a livestock meat-packing facility and a related method are disclosed. In one embodiment, the food source...
Voltage generator circuit
Embodiments are provided that include a circuit for generating voltage in a memory. One such circuit includes a charge pump circuit including a first...
Apparatuses and methods for altering a forward path delay of a signal path
Apparatuses and methods related to altering the timing of command signals for executing commands is disclosed. One such method includes calculating a forward...
Select devices including a semiconductive stack having a semiconductive
Methods, devices, and systems are provided for a select device that can include a semiconductive stack of at least one semiconductive material formed on a first...
Solid state lighting devices with accessible electrodes and methods of
Various embodiments of light emitting dies and solid state lighting ("SSL") devices with light emitting dies, assemblies, and methods of manufacturing are...
Substrate mask patterns, methods of forming a structure on a substrate,
methods of forming a square lattice...
A method of forming a pattern on a substrate comprises forming spaced, upwardly-open, cylinder-like structures projecting longitudinally outward of a base....
Apparatuses including stair-step structures and methods of forming the
Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material,...
Package including an interposer having at least one topological feature
Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, having an interposer including at...
Methods and systems for releasably attaching support members to
Methods and apparatuses for releasably attaching support members to microfeature workpieces to support members are disclosed herein. In one embodiment, for...
Method to produce nanometer-sized features with directed assembly of block
Methods for fabricating stamps and systems for patterning a substrate, and devices resulting from those methods are provided.
Memory reuse for multiple endpoints in USB device
In a system in which individual memory banks may be under individual power control, a subsequent need for a memory bank that is currently in a low power state...
Determining location of error detection data
Methods, devices, and systems for determining location of error detection data are described. One method for operating a memory unit having a bad group of...
Stacked device detection and identification
Various embodiments include apparatus and methods having circuitry to detect and/or assign identification information to dice arranged in a stack and coupled by...
Multi-device memory serial architecture
Subject matter disclosed herein relates to memory devices comprising a memory array, a first port to interface with a memory controller directly or indirectly...
Method and apparatus providing a coupled photonic structure
Described embodiments include optical connections for electronic-photonic devices, such as optical waveguides and photonic detectors for receiving optical waves...
NAND memory constructions and methods of forming NAND memory constructions
Some embodiments include NAND memory constructions. The constructions may contain semiconductor material pillars extending upwardly between dielectric regions,...
Sharing support circuitry in a memory
A memory device, system, and method for operation of a memory device. In one such memory device, the memory device comprises a plurality of strings of memory...
Coarse and fine programming in a solid state memory
Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer...
Apparatus and methods to perform read-while write (RWW) operations
Subject matter disclosed herein relates to methods and apparatus, such as memory devices and systems including such memory devices. In one apparatus example, a...
Fuses, and methods of forming and using fuses
Some embodiments include a fuse having a tungsten-containing structure directly contacting an electrically conductive structure. The electrically conductive...
Apparatus and method for signal transmission over a channel
Apparatus and methods related to data transmission are disclosed. One such apparatus includes a transmitter, a receiver, and a channel. The transmitter includes...
Semiconductor structures including tight pitch contacts
Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating...
Semiconductor assemblies, stacked semiconductor devices, and methods of
manufacturing semiconductor assemblies...
Stacked semiconductor devices, semiconductor assemblies, methods of manufacturing stacked semiconductor devices, and methods of manufacturing semiconductor...
Systems and methods for lowering interconnect capacitance
Methods and apparatus for lowering the capacitance of an interconnect, are disclosed. An example apparatus may include an interconnect formed in at least one...
Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium aluminum oxynitride (ZrAlON) for use in a variety of electronic devices....
Methods of manufacturing semiconductor structures and devices including
nanotubes, and semiconductor...
A method of forming a plurality of nanotubes is disclosed. Particularly, a substrate may be provided and a plurality of recesses may be formed therein. Further,...
Phase change material gradient structures and methods
Memory cells and memory cell structures having a number of phase change material gradients, devices utilizing the same, and methods of forming the same are...
Polymeric materials in self-assembled arrays and semiconductor structures
comprising polymeric materials
Methods for fabricating sublithographic, nanoscale microstructures in line arrays utilizing self-assembling block copolymers, and films and devices formed from...
Methods of forming capacitors having dielectric regions that include
multiple metal oxide-comprising materials
Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal...
Memory devices and methods for managing error regions
Memory devices and methods include a stack of memory dies and a logic die. Method and devices include those that provide for repartitioning the stack of memory...
Apparatus and methods of programming memory cells using adjustable charge
Apparatus and methods are disclosed, including a method of programming involving determining an error rate for the memory cells, and programming the memory...
Memory prefetch systems and methods
Systems and methods are disclosed herein, including those that operate to prefetch a programmable number of data words from a selected memory vault in a...
Power interrupt management
The present disclosure includes methods for operating a memory system, and memory systems. One such method includes updating transaction log information in a...
High speed, wide frequency-range, digital phase mixer and methods of
The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output...
Circuit, system and method for controlling read latency
A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit...
Apparatuses and methods for compensating for power supply sensitivities of
a circuit in a clock path
Apparatuses and methods for compensating for differing power supply sensitivities of a circuit in a clock path. One such method includes altering signal timing...
Memories and methods for sharing a signal node for the receipt and
provision of non-data signals
Memories and methods for providing and receiving non-data signals at a signal node are disclosed. One such memory includes first and second signal nodes, and...