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Patent # Description
US-9,039,474 Magnetically adjusting color-converting materials within a matrix and associated devices, systems, and methods
Magnetically adjusting color-converting particles within a matrix and associated devices, systems, and methods are disclosed herein. A magnetic-adjustment...
US-D730,529 Flexible circuit for an implantable neural stimulator
US-9,038,044 Code patching for non-volatile memory
Example embodiments described herein may comprise a transfer of firmware execution within a non-volatile memory device to one or more replacement instructions...
US-9,037,842 Booting in systems having devices coupled in a chained configuration
The present disclosure includes methods, devices, and systems for booting in systems having devices coupled in a chained configuration. One or more embodiments...
US-9,037,824 Password accessible microelectronic memory
A microelectronic memory may be password access protected. A controller may maintain a register with requirements for accessing particular memory locations to...
US-9,037,788 Validating persistent memory content for processor main memory
Subject matter disclosed herein relates to validating memory content in persistent main memory of a processor.
US-9,036,426 Memory cell sensing using a boost voltage
The present disclosure includes devices, methods, and systems including memory cell sensing using a boost voltage. One or more embodiments include pre-charging...
US-9,036,421 Strings of memory cells having string select gates, memory devices incorporating such strings, and methods of...
Strings of memory cells having a string select gate configured to selectively couple ends of a string to a data line and a source line concurrently, memory...
US-9,036,402 Arrays of vertically stacked tiers of non-volatile cross point memory cells
An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers...
US-9,036,401 Memory cell operation
Methods, devices, and systems associated with memory cell operation are described. One or more methods of operating a memory cell include charging a capacitor...
US-9,036,391 Arrays of vertically-oriented transistors, memory arrays including vertically-oriented transistors, and memory...
An array includes a plurality of vertically-oriented transistors, rows of access lines, and columns of data/sense lines. Individual of the rows include an...
US-9,035,416 Efficient pitch multiplication process
Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated...
US-9,034,769 Methods of selectively removing a substrate material
A method for selective removing material from a substrate without damage to copper filling a via and extending at least partially through the substrate. The...
US-9,034,752 Methods of exposing conductive vias of semiconductor devices and associated structures
Methods of exposing conductive vias of semiconductor devices may comprise conformally forming a barrier material over conductive vias extending from a backside...
US-9,034,724 Semiconductor substrate for photonic and electronic structures and method of manufacture
A method of forming a substrate with isolation areas suitable for integration of electronic and photonic devices is provided. A common reticle and...
US-9,034,710 Methods of forming a nonvolatile memory cell and methods of forming an array of nonvolatile memory cells
A method of forming a nonvolatile memory cell includes forming a first electrode and a second electrode of the memory cell. Sacrificial material is provided...
US-9,034,570 Methods of forming patterns
Some embodiments include methods of forming patterns of openings. The methods may include forming spaced features over a substrate. The features may have tops...
US-9,032,185 Active memory command engine and method
A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or...
US-9,032,166 Memory arbitration system and method having an arbitration packet protocol
A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub....
US-9,032,145 Memory device and method having on-board address protection system for facilitating interface with multiple...
A memory device includes an address protection system that facilitates the ability of the memory device to interface with a plurality of processors operating in...
US-9,032,134 Methods of operating a memory system that include outputting a data pattern from a sector allocation table to a...
A method of operating a memory system includes receiving a read command from a host, where the read command is associated with a logical sector of a memory,...
US-9,030,902 Programming memory cells
Methods for programming memory cells. One such method for programming memory cells includes generating an encoded stream using a data stream and programming the...
US-9,030,895 Memory device with pin register to set input/output direction and bitwidth of data signals
A random access memory includes a data signal line, a data-synchronization signal line for a data synchronization signal which provides a synchronization signal...
US-9,030,884 Method and apparatus for pre-charging data lines in a memory cell array
Memories, pre-charge circuits, and methods for pre-charging memory are described. One such method includes providing a voltage to a data line and adjusting the...
US-9,030,882 Apparatuses and methods including memory array data line selection
Some embodiments include an apparatus having data lines coupled to memory cell strings and a selector configured to selectively couple one of the data lines to...
US-9,030,874 Adjusting program and erase voltages in a memory device
A system and apparatus for adjusting threshold program and erase voltages in a memory array, such as a floating gate memory array, for example. One such method...
US-9,030,870 Threshold voltage compensation in a multilevel memory
Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the...
US-9,030,301 Systems and methods to determine kinematical parameters using RFID tags
Systems and methods to determine kinematical parameters of physical objects using radio frequency identification (RFID) tags attached to the objects. In one...
US-9,029,924 Antiblooming imaging apparatus, systems, and methods
Apparatus, systems, and methods are described to assist in reducing dark current in an active pixel sensor. In various embodiments, a potential barrier...
US-9,029,887 Solid state lighting devices having improved color uniformity and associated methods
Solid state lighting (SSL) devices and methods of manufacturing SSL devices are disclosed herein. In one embodiment, an SSL device comprises a support having a...
US-9,029,856 Methods of forming a metal telluride material, related methods of forming a semiconductor device structure, and...
Accordingly, a method of forming a metal chalcogenide material may comprise introducing at least one metal precursor and at least one chalcogen precursor into a...
US-9,029,826 Phase change memory including ovonic threshold switch with layered electrode and methods for forming the same
Erosion of chalcogenides in phase change memories using ovonic threshold switch selectors can be reduced by controlling columnar morphology in electrodes used...
US-9,029,257 Semiconductor constructions and methods of planarizing across a plurality of electrically conductive posts
Some embodiments include a planarization method. A liner is formed across a semiconductor substrate and along posts that extending upwardly from the substrate....
US-9,029,256 Charge-trap based memory
Methods of fabricating 3D charge-trap memory cells are described, along with apparatus and systems that include them. In a planar stack formed by alternate...
US-9,026,890 Memory with guard value dependent error correction
Embodiments of the present disclosure provide methods, systems, and apparatuses related to calculating an error correction code for a program page dependent on...
US-9,026,887 Physical page, logical page, and codeword correspondence
The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a...
US-9,026,721 Managing defective areas of memory
Methods of operating a memory, and memories for performing such methods, include determining that a particular area of the memory is defective, locating a free...
US-9,026,485 Pattern-recognition processor with matching-data reporting module
Disclosed are methods and devices, among which is a device that includes a pattern-recognition processor. The pattern-recognition processor may include a...
US-9,025,407 Apparatus and methods to provide power management for memory devices
An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated...
US-9,025,398 Metallization scheme for integrated circuit
For multi-level interconnect metallization, each metal level maintains a parallel line arrangement within a region, and the lines of each adjacent metal level...
US-9,025,392 Memory device with reduced neighbor memory cell disturbance
In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes a memory cell, digit line driver, access line driver, clamping...
US-9,025,388 Method for kink compensation in a memory
This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory...
US-9,025,385 Voltage generation and adjustment in a memory device
Voltage generation devices and methods are useful in determining a data state of a selected memory cell in a memory device. Voltages can be generated in...
US-9,025,381 Block-row decoders, memory block-row decoders, memories, methods for deselecting a decoder of a memory and...
Block-row decoders, memory block-row decoders, memories, methods for deselecting a decoder of a memory and methods of selecting a block of memory are disclosed....
US-9,025,370 Cross-point memory devices, electronic systems including cross-point memory devices and methods of accessing a...
Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row)...
US-9,025,364 Selective self-reference read
This disclosure relates to selectively performing a read with increased accuracy, such as a self-reference read, from a memory. In one aspect, data is read from...
US-9,024,290 Vertical transistor phase change memory
Vertical transistor phase change memory and methods of processing phase change memory are described herein. One or more methods include forming a dielectric on...
US-9,024,283 Horizontally oriented and vertically stacked memory cells
Horizontally oriented and vertically stacked memory cells are described herein. One or more method embodiments include forming a vertical stack having a first...
US-9,023,714 Methods of forming a plurality of covered voids in a semiconductor substrate
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
US-9,023,711 Methods for forming a conductive material and methods for forming a conductive structure
A method of forming a conductive material comprises forming at least one opening extending through an organic material and an insulative material underlying the...
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