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Patent # Description
US-9,112,150 Methods of forming memory cells and arrays
Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed...
US-9,112,138 Methods of forming resistive memory elements
A method of forming a resistive memory element comprises forming an oxide material over a first electrode. The oxide material is exposed to a plasma process to...
US-9,112,104 Epitaxial devices
Epitaxial growth methods and devices are described that include a textured surface on a substrate. Geometry of the textured surface provides a reduced lattice...
US-9,112,046 Memory cells and methods of storing information
Memory cells which have channel-supporting material, dielectric material over the channel-supporting material, carrier-trapping material over the dielectric...
US-9,111,958 Threshold voltage adjustment of a transistor
A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor...
US-9,111,932 Semiconductor devices comprising interconnect structures and methods of fabrication
Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of...
US-9,111,879 Semiconductor processing methods, and methods for forming silicon dioxide
Some embodiments include methods for semiconductor processing. A semiconductor substrate may be placed within a reaction chamber. The semiconductor substrate...
US-9,111,857 Method, system and device for recessed contact in memory array
Embodiments disclosed herein may relate to forming a contact region for an interconnect between a selector transistor and a word-line electrode in a memory device.
US-9,111,856 Method for fabricating a phase-change memory cell
A method for fabricating a phase-change memory cell is described. The method includes forming a dielectric layer (228) on a metal layer (226) above a substrate....
US-9,111,853 Methods of forming doped elements of semiconductor device structures
Methods of forming doped elements of semiconductor device structures include forming trenches having undercut portions separating stem portions of a substrate....
US-9,111,798 Memory with carbon-containing silicon channel
A memory includes a first memory cell and a second memory cell formed over the first memory cell. Each of the first memory cell and the second memory cell...
US-9,111,788 Memory device constructions, memory cell forming methods, and semiconductor construction forming methods
Memory device constructions include a first column line extending parallel to a second column line, the first column line being above the second column line; a...
US-9,111,773 Forming three dimensional isolation structures
A three dimensional shallow trench isolation structure including sets of parallel trenches extending in two perpendicular directions may be formed by depositing...
US-9,111,631 Reading memory cell history during program operation for adaptive programming
Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a memory device.
US-9,111,620 Memory having memory cell string and coupling components
Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the...
US-9,111,591 Interconnections for 3D memory
Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs...
US-9,111,045 Intelligent controller system and method for smart card memory modules
A storage device contains a smart-card device and a memory device, both of which are accessed though a controller. The storage device may be used in the same...
US-9,110,832 Object oriented memory in solid state devices
The present disclosure includes methods, devices, and systems for object oriented memory in solid state devices. One embodiment of a method for object oriented...
US-9,110,794 Differential delay compensation
In one embodiment, a method includes recording, for each of a plurality of data frames, a virtual write address including a multiframe indicator and a byte...
US-9,110,098 Probe card and testing apparatus
Provided is a probe card capable of effectively placing electronic parts. A probe card according to the present invention includes a plurality of probes that...
US-9,106,222 On-die system and method for controlling termination impedance of memory device data bus terminals
A system for controlling the termination impedance of memory device data bus terminals is fabricated on the same die as the memory device. The system includes a...
US-9,105,843 Multilevel mixed valence oxide (MVO) memory
Various embodiments include a memory device and methods of forming the same. The memory device can include an electrode coupled to one or more memory elements,...
US-9,105,737 Semiconductor constructions
Some embodiments include methods of forming vertical memory strings. A trench is formed to extend through a stack of alternating electrically conductive levels...
US-9,105,701 Semiconductor devices having compact footprints
Semiconductor devices and methods for making semiconductor devices are disclosed herein. A semiconductor device configured in accordance with a particular...
US-9,105,666 Methods of fabricating semiconductor structures
Semiconductor structures including an etch stop material between a substrate and a stack of alternating insulating materials and first conductive materials,...
US-9,105,665 Gettering agents in memory charge storage structures
Methods of forming memory cells including a charge storage structure having a gettering agent therein can be useful for non-volatile memory devices. Providing...
US-9,105,636 Semiconductor constructions and methods of forming electrically conductive contacts
Some embodiments include methods of forming electrically conductive contacts. An opening is formed through an insulative material to a conductive structure. A...
US-9,105,587 Methods of forming semiconductor structures with sulfur dioxide etch chemistries
Methods of forming a semiconductor device structure and sulfur dioxide etch chemistries. The methods and chemistries, which may be plasma chemistries, include...
US-9,105,350 Apparatuses and methods of operating for memory endurance
Methods of operating an apparatus such as a computing system and/or memory device for memory endurance are provided. One example method can include receiving m...
US-9,105,337 Memories and methods of programming memories
Apparatus and methods for adjusting programming for upper pages of memories are disclosed. In at least one embodiment, a threshold voltage distribution upper...
US-9,105,330 Memory devices configured to apply different weights to different strings of memory cells coupled to a data...
Memory devices and methods are disclosed. One such method compares input data to stored data in a memory device and includes applying a first weight factor to a...
US-9,105,324 Channel skewing
Methods and systems for channel skewing are described. One or more methods for channel skewing includes providing a number of groups of data signals to a memory...
US-9,105,323 Memory device power managers and methods
Memory devices and methods are described that include a stack of memory dies and an attached logic die. Method and devices described provide for power...
US-9,105,320 Memory devices and methods of operating the same
The present disclosure includes memory devices and methods of operating the same. One such device includes an array of groups of memory cells, a group selector...
US-9,105,314 Program-disturb decoupling for adjacent wordlines of a memory device
Subject matter disclosed herein relates to memory operations regarding programming bits into a memory array.
US-9,104,828 State grouping for element utilization
Embodiments of a system and method for generating an image configured to program a parallel machine from source code are disclosed. One such parallel machine...
US-9,104,690 Transactional memory
Subject matter disclosed herein relates to techniques to perform transactions using a memory device.
US-9,104,588 Circuits, apparatuses, and methods for address scrambling
Circuits, apparatuses, and methods are disclosed for address scrambling in integrated circuits. One example apparatus includes a plurality of data regions, each...
US-9,104,555 Memory system controller
The present disclosure includes methods and devices for a memory system controller. In one or more embodiments, a memory system controller includes a host...
US-9,104,547 Wear leveling for a memory device
Memory devices and methods to facilitate wear leveling operations in a memory device. In one such method, particular blocks of memory cells are excluded from...
US-9,102,121 Substrates and methods of forming a pattern on a substrate
Substrates and methods of forming a pattern on a substrate. The pattern includes a repeating pattern region and a pattern-interrupting region adjacent to the...
US-9,100,002 Apparatus and methods for leakage current reduction in integrated circuits
This disclosure relates to leakage current reduction in integrated circuits (ICs). In one aspect, an IC can include a digital logic circuit and a polarization...
US-9,099,571 Packaged integrated circuit devices with through-body conductive vias, and methods of making same
A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at...
US-9,099,539 Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
Microfeature workpieces having interconnects and conductive backplanes and associated systems and methods are disclosed herein. One such device includes a...
US-9,099,472 Semiconductor constructions, methods of forming conductive structures and methods of forming DRAM cells
Some embodiments include methods of forming conductive structures. An electrically conductive material may be deposited with a first deposition method. The...
US-9,099,457 Semiconductor with through-substrate interconnect
Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor...
US-9,099,442 Conductive interconnect structures incorporating negative thermal expansion materials and associated systems,...
Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device...
US-9,099,431 Polishing systems and methods for removing conductive material from microelectronic substrates
Polishing systems and methods for removing conductive material (e.g., noble metals) from microelectronic substrates are disclosed herein. Several embodiments of...
US-9,099,402 Integrated circuit structure having arrays of small, closely spaced features
Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can...
US-9,099,314 Pitch multiplication spacers and methods of forming the same
Spacers in a pitch multiplication process are formed without performing a spacer etch. Rather, the mandrels are formed over a substrate and then the sides of...
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