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Patent # Description
US-9,013,942 Sense amplifier having loop gain control
Memories, sense amplifiers, and methods for amplifying a current input are disclosed, including a sense amplifier including a bias circuit configured to provide...
US-9,013,044 Through wire interconnect (TWI) for semiconductor components having wire in via and bonded connection with...
A through wire interconnect for a semiconductor substrate includes a via extending through the semiconductor substrate from the first side to the second side...
US-9,012,318 Etching polysilicon
Methods and compositions for etching polysilicon including aqueous compositions containing nitric acid and ammonium fluoride, and apparatus formed thereby.
US-9,012,253 Gallium nitride wafer substrate for solid state lighting devices, and associated systems and methods
Gallium nitride wafer substrate for solid state lighting devices, and associated systems and methods. A method for making an SSL device substrate in accordance...
US-9,009,570 Integrity of an address bus
A method for improving address integrity in a memory system generates error correction data corresponding to a memory address. The error correction data is...
US-9,009,556 Error correction and recovery in chained memory architectures
Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a memory unit configured to receive data...
US-9,009,394 Serial flash memory with a configurable number of dummy clock cycles
Apparatus and methods configure a serial flash memory device. A value in a configuration register configures the number of dummy clock cycles to provide prior...
US-9,009,357 Method and apparatus for field firmware updates in data storage systems
Data storage devices and methods for updating firmware are disclosed. For example, one such data storage device includes a device firmware and a controller,...
US-9,007,867 Loading trim address and trim data pairs
Methods of loading trim address and trim data pairs to a trim register array, and apparatus configured to perform such methods. The methods maintain a...
US-9,007,860 Sub-block disabling in 3D memory
Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of...
US-9,007,832 Methods for programming a memory device and memory devices
Methods for programming memory cells and memory devices are disclosed. One such method for programming includes performing a program verify operation of a group...
US-9,007,831 Memory devices with different sized blocks of memory cells and methods
In an embodiment, each block of a plurality of blocks includes a respective plurality of strings of memory cells, where each of the plurality of strings of a...
US-9,007,822 Complementary decoding for non-volatile memory
Decoding and decoder circuits in memory devices are disclosed. Array lines are biased or floated as memory device operations are performed in the memory device....
US-9,007,818 Memory cells, semiconductor device structures, systems including such cells, and methods of fabrication
Memory cells including cell cores having free regions are disclosed. The free regions exhibit a strain that affects a magnetization orientation within the cell...
US-9,006,859 Semiconductor structures and devices
Methods of forming semiconductor structures that include bodies of a semiconductor material disposed between rails of a dielectric material are disclosed. Such...
US-9,006,702 Semiconductor structure including a zirconium oxide material
Semiconductor structures including a zirconium oxide material and methods of forming the same are described herein. As an example, a semiconductor structure can...
US-9,006,075 Memory cells, semiconductor devices including such cells, and methods of fabrication
Memory cells are disclosed, which cells include a cell material and an ion-source material over the cell material. A discontinuous interfacial material is...
US-9,006,060 N-type field effect transistors, arrays comprising N-type vertically-oriented transistors, methods of forming...
An n-type field effect transistor includes silicon-comprising semiconductor material comprising a pair of source/drain regions having a channel region...
US-9,005,473 Gaseous compositions comprising hydrogen fluoride and an alkylated ammonia derivative
A method of removing at least a portion of a silicon oxide material is disclosed. The silicon oxide is removed by exposing a semiconductor structure comprising...
US-9,005,463 Methods of forming a substrate opening
A method of forming a substrate opening includes forming a plurality of side-by-side openings in a substrate. At least some of immediately adjacent side-by-side...
US-9,005,458 Photonic device structure and method of manufacture
Disclosed method and apparatus embodiments provide a photonic device with optical isolation from a supporting substrate. A generally rectangular cavity in cross...
US-9,003,651 Methods for integrated circuit fabrication with protective coating for planarization
Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction...
US-9,003,177 Data security for digital data storage
A computing system includes data encryption in the data path between a data source and data storage devices. The data storage devices may be local or they may...
US-9,001,594 Apparatuses and methods for adjusting a path delay of a command path
Apparatuses and method for adjusting a path delay of a command path are disclosed. In an example apparatus, a command path configured to provide a command from...
US-9,001,584 Sub-block decoding in 3D memory
Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of...
US-9,001,577 Memory cell sensing
This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first memory cell coupled to a first data line,...
US-9,001,575 Encoding program bits to decouple adjacent wordlines in a memory device
Subject matter disclosed herein relates to memory operations regarding encoding program bits to be programmed into a memory array.
US-9,001,573 Method and apparatuses for programming memory cells
Methods and apparatus for programming memory cells in a memory array are disclosed. A most recent programming time is determined, the most recent programming...
US-9,001,561 Performing forming processes on resistive memory
The present disclosure includes apparatuses and methods for performing forming processes on resistive memory. A number of embodiments include applying a...
US-9,001,548 Memory device interface methods, apparatus, and systems
Apparatus and systems for memory system are provided. In an example, an interface chip can include a memory controller configured to couple to a processor and...
US-9,000,893 Food source information transferring system and method for a meat-packing facility
A food source information transferring system for a livestock meat-packing facility and a related method are disclosed. In one embodiment, the food source...
US-9,000,836 Voltage generator circuit
Embodiments are provided that include a circuit for generating voltage in a memory. One such circuit includes a charge pump circuit including a first...
US-9,000,817 Apparatuses and methods for altering a forward path delay of a signal path
Apparatuses and methods related to altering the timing of command signals for executing commands is disclosed. One such method includes calculating a forward...
US-9,000,502 Select devices including a semiconductive stack having a semiconductive material
Methods, devices, and systems are provided for a select device that can include a semiconductive stack of at least one semiconductive material formed on a first...
US-9,000,456 Solid state lighting devices with accessible electrodes and methods of manufacturing
Various embodiments of light emitting dies and solid state lighting ("SSL") devices with light emitting dies, assemblies, and methods of manufacturing are...
US-8,999,852 Substrate mask patterns, methods of forming a structure on a substrate, methods of forming a square lattice...
A method of forming a pattern on a substrate comprises forming spaced, upwardly-open, cylinder-like structures projecting longitudinally outward of a base....
US-8,999,844 Apparatuses including stair-step structures and methods of forming the same
Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material,...
US-8,999,763 Package including an interposer having at least one topological feature
Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, having an interposer including at...
US-8,999,498 Methods and systems for releasably attaching support members to microfeature workpieces
Methods and apparatuses for releasably attaching support members to microfeature workpieces to support members are disclosed herein. In one embodiment, for...
US-8,999,492 Method to produce nanometer-sized features with directed assembly of block copolymers
Methods for fabricating stamps and systems for patterning a substrate, and devices resulting from those methods are provided.
US-RE45,457 Memory reuse for multiple endpoints in USB device
In a system in which individual memory banks may be under individual power control, a subsequent need for a memory bank that is currently in a low power state...
US-8,996,907 Determining location of error detection data
Methods, devices, and systems for determining location of error detection data are described. One method for operating a memory unit having a bad group of...
US-8,996,836 Stacked device detection and identification
Various embodiments include apparatus and methods having circuitry to detect and/or assign identification information to dice arranged in a stack and coupled by...
US-8,996,822 Multi-device memory serial architecture
Subject matter disclosed herein relates to memory devices comprising a memory array, a first port to interface with a memory controller directly or indirectly...
US-8,995,805 Method and apparatus providing a coupled photonic structure
Described embodiments include optical connections for electronic-photonic devices, such as optical waveguides and photonic detectors for receiving optical waves...
US-8,995,193 NAND memory constructions and methods of forming NAND memory constructions
Some embodiments include NAND memory constructions. The constructions may contain semiconductor material pillars extending upwardly between dielectric regions,...
US-8,995,188 Sharing support circuitry in a memory
A memory device, system, and method for operation of a memory device. In one such memory device, the memory device comprises a plurality of strings of memory...
US-8,995,182 Coarse and fine programming in a solid state memory
Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer...
US-8,995,161 Apparatus and methods to perform read-while write (RWW) operations
Subject matter disclosed herein relates to methods and apparatus, such as memory devices and systems including such memory devices. In one apparatus example, a...
US-8,994,489 Fuses, and methods of forming and using fuses
Some embodiments include a fuse having a tungsten-containing structure directly contacting an electrically conductive structure. The electrically conductive...
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