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Charge loss compensation methods and apparatus
Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss...
Erase operations with erase-verify voltages based on where in the erase
operations an erase cycle occurs
Memory devices and methods of erasing the memory devices are disclosed. One such method includes performing an erase cycle of an erase operation on a plurality...
Apparatuses and methods for performing logical operations using sensing
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an...
Method and devices for memory cell erasure with a programming monitor of
Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase...
Apparatus and methods for applying a non-zero voltage differential across
a memory cell not involved in an...
Apparatus and methods for applying a non-zero voltage differential across a memory cell not involved in an access operation can facilitate improved data...
Method of programming a multi-level memory device
Method of programming a multi-level memory cell may include transferring one or more values between an auxiliary latch of the multi-level memory cell and a most...
Methods and apparatuses for controlling memory write sequences
Subject matter disclosed herein relates to memory operations regarding changing an order of program bits to be programmed into a memory array.
Memory programming to reduce thermal disturb
A resistive memory array is programmed such that particular adjacent pairs of memory cells along a bit line having a back-to-back relationship are programmed...
Capacitorless DRAM on bulk silicon
A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of...
Semiconductor assemblies and structures
Semiconductor assemblies, structures, and methods of fabrication are disclosed. A coating is formed on an electrically conductive pillar. The coating, which may...
Transistors having a control gate and one or more conductive structures
Transistors having a dielectric over a semiconductor, a control gate over the dielectric at a particular level, and one or more conductive structures over the...
Method for forming a light conversion material
A method and system for manufacturing a light conversion structure for a light emitting diode (LED) is disclosed. The method includes forming a transparent,...
Methods of treating semiconductor substrates, methods of forming openings
during semiconductor fabrication, and...
Some embodiments include methods of treating semiconductor substrates. The substrates may be exposed to one or more conditions that vary continuously. The...
Methods of forming a pattern on a substrate
A method of forming a pattern on a substrate includes forming spaced first features derived from a first lithographic patterning step. Sidewall spacers are...
Methods for fabricating semiconductor device structures and arrays of
vertical transistor devices
A semiconductor device structure is disclosed. The semiconductor device structure includes a mesa extending above a substrate. The mesa has a channel region...
Methods of forming a mask and methods of correcting intra-field variation
across a mask design used in...
A method of forming a mask includes creating a difference map between a desired intra-field pattern that is to be formed on substrates and an intra-field...
Memory controller supporting rate-compatible punctured codes and
supporting block codes
Apparatus and methods store data in a non-volatile solid state memory device according to a rate-compatible code, such as a rate-compatible convolutional code...
Method for performing error corrections of digital information codified as
a symbol sequence
A method and system for making error corrections on digital information coded as symbol sequences, for example digital information stored in electronic memory...
The present disclosure includes methods, devices, modules, and systems for modifying commands. One device embodiment includes a memory controller including a...
Translation layer in a solid state storage device
Solid state storage devices and methods for flash translation layers are disclosed. In one such translation layer, a sector indication is translated to a memory...
Methods of providing access to I/O devices
A method of providing one or more computing devices with access to a plurality of resources. The plurality of resources are provided by at least one physical...
Apparatuses and methods for performing compare operations using sensing
The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can...
memories and methods for repair in open digit memory architectures
A memory with extra digit lines in full size end arrays with an open digit architecture, which can use the extra digit lines to form repair cells. In one...
Techniques for sensing a semiconductor memory device
Techniques for sensing a semiconductor memory device are disclosed. In one embodiment, the techniques may be realized as a semiconductor memory device...
Architecture for 3-D NAND memory
Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the...
Fractional bits in memory cells
Methods, devices, modules, and systems for programming memory cells can include storing charges corresponding to a data state that represents an integer number...
Techniques for providing a direct injection semiconductor memory device
Techniques for providing a direct injection semiconductor memory device are disclosed. In one embodiment, the techniques may be realized as a method for biasing...
Memory cells having a plurality of resistance variable materials
Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an...
Systems and methods to selectively connect antennas to receive and
backscatter radio frequency signals
Systems and methods to selectively attach and control antennas via diodes and current sources. In one embodiment, a system includes: an RFID reader having a...
Methods, apparatuses, and circuits for bimodal disable circuits
Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter...
Reference current distribution
Example reference current distribution circuitry described herein include current mirrors having resistive elements of varying sizes between gate nodes of sense...
Self-identifying solid-state transducer modules and associated systems and
Self-identifying solid-state transducer (SST) modules and associated systems and methods are disclosed herein. In several embodiments, for example, an SST...
Semiconductor constructions, semiconductor processing methods, methods of
forming contact pads, and methods of...
Some embodiments include semiconductor processing methods in which a copper barrier is formed to be laterally offset from a copper component, and in which...
Circuit structures and electronic systems
The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating...
Stacked packaged integrated circuit devices, and methods of making same
A device is disclosed which includes a first packaged integrated circuit device, a second packaged integrated circuit device positioned above the first packaged...
Semiconductor device having backside redistribution layers and method for
fabricating the same
Present embodiments relate to a semiconductor device having a backside redistribution layer and a method for forming such a layer. Specifically, one embodiment...
Semiconductor device isolation structures
Structures and methods are disclosed for the electrical isolation of semiconductor devices. A method of forming a semiconductor device may include providing a...
Shallow trench isolation for a memory
In some embodiments, a gate structure with a spacer on its side may be used as a mask o form self-aligned trenches in microelectronic memory, such as a flash...
Semiconductor devices including WiSX
Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon...
Vertical solid-state transducers and high voltage solid-state transducers
having buried contacts and associated...
Solid-state transducers ("SSTs") and vertical high voltage SSTs having buried contacts are disclosed herein. An SST die in accordance with a particular...
Multi-layer interconnect with isolation layer
An integrated circuit interconnect is fabricated by using a mask to form a via in an insulating layer for a conductive plug. After the plug is formed in the...
Methods of forming gated devices
Some embodiments include methods of forming gated devices. An upper region of a semiconductor material is patterned into a plurality of walls that extend...
Methods of selectively forming metal-doped chalcogenide materials, methods
of selectively doping chalcogenide...
Methods of selectively forming a metal-doped chalcogenide material comprise exposing a chalcogenide material to a transition metal solution, and incorporating...
Methods for processing semiconductor devices
Methods of forming a semiconductor structure include exposing a carrier substrate to a silane material to form a coating, removing a portion of the coating at...
Bonded strained semiconductor with a desired surface orientation and
According to various method embodiments, a semiconductor layer is oriented to a substrate. The semiconductor layer has a surface orientation and is oriented to...
Methods of forming oxides, methods of forming semiconductor constructions,
and methods of forming isolation regions
Some embodiments include methods of forming isolation regions in which spin-on material (for example, polysilazane) is converted to a silicon dioxide-containing...
Method of manufacture of semiconductor isolation structure
A method of formation of an isolation structure for vertical semiconductor devices, the resulting isolation structure, and a memory device to prevent leakage...
Methods of forming metal silicide-comprising material and methods of
forming metal silicide-comprising contacts
A method of forming metal silicide-comprising material includes forming a substrate which includes a first stack having second metal over first metal over...
Double gated 4F2 dram CHC cell and methods of fabricating the same
A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein...
Methods of forming memory cells
Some embodiments include methods of forming memory cells in which a metal oxide material is formed over a first electrode material, an oxygen-sink material is...