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Patent # Description
US-9,076,543 Techniques for providing a direct injection semiconductor memory device
Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as...
US-9,076,528 Apparatus including memory management control circuitry and related methods for allocation of a write block cluster
Memory system controllers can include non-volatile memory control circuitry including a plurality of channel control circuits. Each of the plurality of channel...
US-9,076,524 Method of accessing a memory device
A method is provided for accessing a memory device. The method includes programming data in a plurality of cells of the memory device in a first programming...
US-9,076,501 Apparatuses and methods for reducing current leakage in a memory
Apparatuses, sense amplifier circuits, and methods for operating a sense amplifier circuit in a memory are described. An example apparatus includes a sense...
US-9,075,814 Memory device, electronic system, and methods associated with modifying data and a file of a memory device
A memory device, system and method of editing a file in a non-volatile memory device is described. The memory device includes a controller and a memory array...
US-9,075,770 Apparatuses and methods for memory testing and repair
Some embodiments include apparatuses and methods having a first interface to communicate with a processing unit, a second interface to communicate with a memory...
US-9,075,765 State change in systems having devices coupled in a chained configuration
The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of...
US-9,075,725 Persistent memory for processor main memory
Subject matter disclosed herein relates to a system of one or more processors that includes persistent memory.
US-9,075,428 Results generation for state machine engines
A state machine engine includes a storage element, such as a (e.g., match) results memory. The storage element is configured to receive a result of an analysis...
US-9,075,317 Photomasks, methods of forming a photomask, and methods of photolithographically patterning a substrate
A photomask includes a substrate having a device region and an adjacent edge region over transparent material. The device region includes spaced primary...
US-9,075,083 Probe card
An electrode and wiring can be provided on an FPC board without restriction by a through hole. A probe card in which an FPC board of a probe assembly is fixed...
US-9,071,762 Image sensor including real-time automatic exposure control and swallowable pill including the same
An imager and a method for real-time, non-destructive monitoring of light incident on imager pixels during their exposure to light. Real-time or present pixel...
US-9,071,273 Extended single-bit error correction and multiple-bit error detection
Some embodiments include apparatus and methods to prevent at least one of misidentifying and ignoring multiple-bit errors if the multiple-bit errors include a...
US-9,071,235 Apparatuses and methods for changing signal path delay of a signal path responsive to changes in power
Apparatuses and methods for changing a signal path delay of a signal path responsive to changes in power provided to the signal path are disclosed. An example...
US-9,071,231 Apparatuses and methods for duty cycle adjustments
Apparatuses and methods have been disclosed. One such apparatus includes a plurality of gates coupled together in series. A first pull-down circuit can be...
US-9,070,874 Memory cell structures
The present disclosure includes memory cell structures and method of forming the same. One such memory cell includes a first electrode having sidewalls angled...
US-9,070,858 Method, system, and device for storage cell, such as for memory
Embodiments disclosed herein may relate to forming an interface between a selector transistor and a phase change material storage cell in a memory device.
US-9,070,767 Vertical memory devices and apparatuses
Vertical memory devices comprise vertical transistors, buried digit lines extending in a first direction in an array region, and word lines extending in a...
US-9,070,656 Underfill-accommodating heat spreaders and related semiconductor device assemblies and methods
Heat spreaders for dissipating heat from semiconductor devices comprise a contact surface located within a recess on an underside of the heat spreader, the...
US-9,070,641 Methods for forming assemblies and multi-chip modules including stacked semiconductor dice
An assembly method that includes providing a first semiconductor device and positioning a second semiconductor device at least partially over the first...
US-9,070,473 Refresh architecture and algorithm for non-volatile memories
Methods and systems to refresh a non-volatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device...
US-9,070,470 Sensing memory cells coupled to different access lines in different blocks of memory cells
In an embodiment, a target memory cell in a first block of memory cells of a memory device and a target memory cell in a second block of memory cells of the...
US-9,070,469 Digital filters with memory
A memory device that, in certain embodiments, includes a memory element coupled to a bit-line and a quantizing circuit coupled to the memory element via the...
US-9,070,459 Erase operation control sequencing apparatus, systems, and methods
Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a...
US-9,070,450 Non-volatile multilevel memory cells
The present disclosure includes methods, devices, modules, and systems for operating non-volatile multilevel memory cells. One method embodiment includes...
US-9,070,442 Memory devices with local and global devices at substantially the same level above stacked tiers of memory...
In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a...
US-9,070,425 Data line control for sense amplifiers
Some embodiments include apparatuses and methods having a first data line, a second data line, a first transistor, a sense amplifier, and a circuit. The first...
US-9,069,661 Control arrangements and methods for accessing block oriented nonvolatile memory
A memory system digitally communicates with a host device to provide data storage capacity for the host device. The memory system includes a plurality of...
US-9,069,008 Inspection apparatus for semiconductor devices and chuck stage for the inspection apparatus that is movable...
An inspection apparatus is provided, which includes probes for front side electrodes, probes for back side electrodes, and a chuck stage. The probes for front...
US-9,065,654 Parallel encryption/decryption
The present disclosure includes methods and devices for parallel encryption/decryption. In one or more embodiments, an encryption/decryption device includes an...
US-9,065,483 Determining soft data using a classification code
Apparatuses and methods for determining soft data using a classification code are provided. One example apparatus can include a classification code (CC) decoder...
US-9,065,456 Semiconductor device having DLL circuit
Disclosed herein is a device includes a first delay circuit delaying a first clock signal according to a count value to generate a second clock signal, a phase...
US-9,065,442 Adjustable data drivers and methods for driving data signals
Apparatuses and methods for driving input data signals onto signal lines as output data signals are disclosed. An example apparatus includes a detection...
US-9,065,048 Methods of forming germanium-antimony-tellurium materials and chalcogenide materials
Methods of forming a material include exposing a substrate to a first germanium-containing compound and a second, different germanium-containing compound;...
US-9,065,047 Mixed valent oxide memory and method
Memory devices and methods of forming include a mixed valent oxide located between a first electrode and a second electrode. Implantation of a metal below a...
US-9,064,984 Semiconductor devices and methods for forming patterned radiation blocking on a semiconductor device
Several embodiments for semiconductor devices and methods for forming semiconductor devices are disclosed herein. One embodiment is directed to a method for...
US-9,064,973 Die attached to a support member by a plurality of adhesive members
Methods and systems for adhering microfeature workpieces to support members are disclosed. A method in accordance with one embodiment of the invention includes...
US-9,064,970 Memory including blocking dielectric in etch stop tier
Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to...
US-9,064,935 Methods of forming a plurality of conductive lines in the fabrication of integrated circuitry, methods of...
A method of forming a pair of conductive lines in the fabrication of integrated circuitry includes forming a trench into a damascene material received over a...
US-9,064,793 Encapsulated phase change cell structures and methods
Methods and devices associated with phase change cell structures are described herein. In one or more embodiments, a method of forming a phase change cell...
US-9,064,730 Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device
Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device are disclosed. The techniques may be realized as a semiconductor...
US-9,064,728 Method and apparatus for fabricating a memory device with a dielectric etch stop layer
The present technique relates to a method and apparatus to provide a dielectric etch stop layer that prevents shorts for a buried digit layer as an...
US-9,064,692 DRAM cells and methods of forming silicon dioxide
Some embodiments include methods of forming silicon dioxide in which silicon dioxide is formed across silicon utilizing a first treatment temperature of no...
US-9,064,600 Memory controller method and system compensating for memory cell data losses
A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory...
US-9,064,587 Memory address repair without enable fuses
A memory chip design methodology is disclosed wherein fuse banks on the memory chip may be implemented without enable fuses. A fuse bank may be enabled by using...
US-9,064,578 Enable/disable of memory chunks during memory access
Chunks of memory cells in a memory array are enabled to be accessed and then one or more of the chunks are disabled from being accessed. In one such apparatus,...
US-9,064,577 Apparatuses and methods to control body potential in memory operations
Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line...
US-9,064,576 Apparatuses and methods for transposing select gates
Apparatuses and methods for transposing select gates, such as in a computing system and/or memory device, are provided. One example apparatus can include a...
US-9,064,575 Determining whether a memory cell state is in a valley between adjacent data states
The present disclosure includes apparatuses and methods related to memory cell state in a valley between adjacent data states. A number of methods can include...
US-9,064,572 Multilevel phase change memory operation
Methods, devices, and systems associated with multilevel phase change memory cells are described herein. One or more embodiments of the present disclosure...
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