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Patent # Description
US-1,017,0188 3D memory device including shared select gate connections between memory blocks
Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string...
US-1,017,0187 Apparatuses and methods using negative voltages in part of memory write read, and erase operations
Some embodiments include apparatuses and methods having a memory cell string that can include memory cells located in different levels of the apparatus. The...
US-1,017,0183 Method of storing and retrieving data for a resistive random access memory (RRAM) array with multi-memory cells...
Some embodiments include methods of storing and retrieving data for an RRAM array. The array is subdivided into a plurality of memory bits, with each memory bit...
US-1,017,0174 Apparatus and methods for refreshing memory
Apparatuses for executing row hammer refresh are described. An example apparatus includes: memory banks, each memory bank of the memory banks includes: a latch...
US-1,017,0173 Charge mirror-based sensing for ferroelectric memory
Methods, systems, and devices for a sensing scheme that extracts the full or nearly full remnant polarization charge difference between two logic states of a...
US-1,017,0169 Apparatuses and methods involving accessing distributed sub-blocks of memory cells
Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in...
US-1,017,0167 Single node power management for multiple memory devices
Some embodiments include apparatuses and methods having a node to couple to a plurality of memory devices, memory cells, and a module to perform an operation on...
US-1,016,9226 Persistent content in nonvolatile memory
Applications may request persistent storage in nonvolatile memory. The persistent storage is maintained across power events and application instantiations....
US-1,016,9144 Non-volatile memory including selective error correction
Some embodiments include apparatuses and methods using a first memory area and a second memory area included a memory device, and using control circuitry...
US-1,016,8918 Recycled version number values in flash memory
Various embodiments include methods, apparatus, and systems for assigning a plurality of version number values to instances of a logical entity of a memory...
US-1,016,8724 Apparatuses and methods for providing reference voltages
A reference voltage generator is disclosed that may provide a plurality of reference voltages. A reference voltage generator may include a voltage divider, a...
US-1,016,8233 Semiconductor device including sensor
Disclosed here is an apparatus that includes a sensor including a plurality of sense nodes, a plurality of first latch circuits including a plurality of first...
US-1,016,5683 Apparatus and methods for via connection with reduced via currents
Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first...
US-1,016,4817 Methods and apparatuses for signal translation in a buffered memory
According to one embodiment, A data buffer is described. The data buffer comprises a first input/output circuit configured to receive and provide a first signal...
US-1,016,4805 Characterization of decision feedback equalizer taps
Various embodiments, disclosed herein, can include apparatus and methods to characterize taps of a decision feedback equalizer of a data receiver. In...
US-1,016,4642 Circuits, apparatuses, and methods for frequency division
Circuits, apparatuses, and methods are disclosed for frequency division. In one such example circuit, a frequency divider is configured to alternate between...
US-1,016,4624 Apparatuses for reducing off state leakage currents
Apparatuses for reducing leakage currents during an off state for transistors is described herein. An example apparatus includes a switch having an input node...
US-1,016,4618 Jitter cancellation with automatic performance adjustment
Methods, systems, and devices for jitter cancellation with automatic performance adjustment are described. Within a clock distribution system in an electronic...
US-1,016,4187 Methods, apparatuses, and circuits for programming a memory device
Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.
US-1,016,4178 Methods for forming narrow vertical pillars and integrated circuit devices having the same
In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some...
US-1,016,4168 Magnetic memory cell structures, arrays, and semiconductor devices
Methods of forming memory cells, magnetic memory cell structures, and arrays of magnetic memory cell structures are disclosed. Embodiments of the methods...
US-1,016,4044 Gate stacks
Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten...
US-1,016,4009 Memory device including voids between control gates
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a channel to conduct current, the channel including...
US-1,016,4004 Semiconductor device having a second conductive layer partially embedded in a stacked insulating structure and...
Disclosed herein is a device that includes: a semiconductor substrate; a first insulating layer over a surface of the semiconductor substrate; first and second...
US-1,016,3978 Memory cell with independently-sized elements
Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in...
US-1,016,3977 Chalcogenide memory device components and composition
Systems, devices, and methods related to or that employ chalcogenide memory components and compositions are described. A memory device, such as a selector...
US-1,016,3928 Memory having memory cell string and coupling components
Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the...
US-1,016,3917 Cell disturb prevention using a leaker device to reduce excess charge from an electronic device
Various embodiments comprise apparatuses and methods of forming the apparatuses. In one embodiment, an exemplary apparatus includes a plurality of memory cells....
US-1,016,3909 Methods for fabricating a semiconductor memory device
A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas...
US-1,016,3908 Array of conductive lines individually extending transversally across and elevationally over a mid-portion of...
An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material...
US-1,016,3906 Circuit and layout for single gate type precharge circuit for data lines in memory device
Some embodiments include apparatus and methods using a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion...
US-1,016,3893 Apparatus containing circuit-protection devices
Apparatus including an array of memory cells may include circuit-protection devices that may include first and second circuit-protection units, a first gate...
US-1,016,3840 Methods of fluxless micro-piercing of solder balls, and resulting devices
A method of establishing conductive connections is disclosed. The method includes providing an integrated circuit die having a plurality of solder balls each of...
US-1,016,3830 Bonding pads with thermal pathways
Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal...
US-1,016,3826 Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a system comprises a...
US-1,016,3755 Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths
Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a...
US-1,016,3693 Methods for processing semiconductor dice and fabricating assemblies incorporating same
A method for processing semiconductor dice comprises removing material from a surface of a semiconductor wafer to create a pocket surrounded by a sidewall at a...
US-1,016,3685 Methods of forming one or more covered voids in a semiconductor substrate
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
US-1,016,3655 Through substrate via liner densification
Apparatuses and methods are disclosed herein for densification of through substrate insulating liners. An example method may include forming a through substrate...
US-1,016,3514 Methods of operating a memory during a programming operation
Methods of operating a memory include increasing a voltage applied to a first access line from a first voltage to a second voltage higher than the first voltage...
US-1,016,3507 Apparatuses and methods including memory access in cross point memory
Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch...
US-1,016,3506 Apparatuses including memory cells and methods of operation of same
Disclosed herein is a memory cell including a memory element and a selector device. The memory cell may be programmed with a programming pulse having a first...
US-1,016,3501 Apparatuses, memories, and methods for address decoding and selecting an access line
Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address...
US-1,016,3498 Reflow protection
Devices and techniques to reduce corruption of preloaded data during assembly are disclosed herein. A memory device can perform operations to store received...
US-1,016,3486 Command signal clock gating
A semiconductor device includes a clock gating tree comprising a first clock gating stage and a second clock gating stage. The first clock gating stage is...
US-1,016,3483 Dynamic reference voltage determination
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first value may be written to a first memory cell and a second...
US-1,016,3482 Ground reference scheme for a memory cell
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be employed in a digit line...
US-1,016,3481 Offset cancellation for latching in a memory device
Methods, systems, and devices for offset cancellation for latching in memory devices are described. A memory device may include a sense component comprising a...
US-1,016,3480 Periphery fill and localized capacitance
Methods, systems, and devices for periphery fill and localized capacitance are described. A memory array may be fabricated with certain containers connected to...
US-1,016,3472 Apparatuses and methods for memory operations having variable latencies
Apparatuses and methods for performing memory operations are described. In an example apparatus, a memory is configured to receive a memory instruction and...
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