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Patent # Description
US-1,014,7468 Accessing data in memory
The present disclosure includes apparatuses and methods related to accessing data in memory. One example method comprises storing data associated with a first...
US-1,014,7467 Element value comparison in memory
The present disclosure includes apparatuses and methods related to performing a greater vector determination in memory. An example apparatus comprises a first...
US-1,014,7466 Voltage reference computations for memory decision feedback equalizers
A device includes a combinational circuit configured to create a one or more distortion correction factors used offset inter-symbol interference from a data...
US-1,014,7465 System and method of command based and current limit controlled memory device power up
Devices and systems for powering up a memory device, for example, are disclosed. One such memory device includes power up circuitry configured to receive an...
US-1,014,6970 RFID reader
A radio frequency identification (RFID) reader includes an RFID module configured to generate a radio frequency (RF) signal, a power divider configured to...
US-1,014,6719 Semiconductor layered device with data bus
Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first die including a first switch...
US-1,014,6617 Error control in memory storage systems
A method includes calculating a first syndrome of a codeword read from a memory location under a first set of conditions and calculating a second syndrome of...
US-1,014,6614 Encoding data in a modified-memory system
In one embodiment, a set of memory circuits is separated from a logic system by a bus. The logic system can contain many of the logic functions traditionally...
US-1,014,6561 Executing applications from a semiconductor nonvolatile memory
A processor-based device (e.g., a wireless device) may include a processor and a semiconductor nonvolatile memory to directly execute an application (e.g., an...
US-1,014,6555 Adaptive routing to avoid non-repairable memory and logic defects on automata processor
Systems and methods for utilizing a defect map to configure an automata processor in order to avoid defects when configuring the automata processor. A system...
US-1,014,6537 Vector population count determination in memory
Examples of the present disclosure provide apparatuses and methods for determining a vector population count in a memory. An example method comprises...
US-1,014,6477 Command queuing
The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory...
US-1,014,6457 Systems and methods for reordering packet transmissions in a scalable memory system protocol
A memory device includes a plurality of memory components that stores data and a processor communicatively coupled to the plurality of memory components. The...
US-1,014,6292 Power management
The present disclosure includes methods and apparatuses for power management. One method includes transferring data between a memory and a controller via an...
US-1,014,4044 Treatment of trade effluent from food waste disposal systems
A bioprocess comprises regulating pH of trade effluent wastewater, adding and mixing a first bio-additive, adding and mixing a flocculant/coagulant, filtering...
US-1,014,2137 Wireless devices and systems including examples of full duplex transmission
Examples described herein include systems and methods which include wireless devices and systems with examples of full duplex compensation with a...
US-1,014,2112 Solid state storage device with command and control access
Several embodiments of memory devices and systems with command and control access are described herein. In one embodiment, a memory device includes a controller...
US-1,014,1942 Apparatuses and methods for providing frequency divided clocks
Apparatuses and methods for providing frequency divided clocks are described. An example apparatus includes a first circuit configured to provide a first...
US-1,014,1932 Wiring with external terminal
Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a pad included in a pad formation area that...
US-1,014,1508 Clamp elements for phase change memory arrays
Clamp elements, memories, apparatuses, and methods for forming the same are disclosed herein. An example memory may include an array of memory cells and a...
US-1,014,1330 Methods of forming semiconductor device structures, and related semiconductor device structures, semiconductor...
A method of forming a semiconductor device structure comprises forming a stack structure comprising stacked tiers. Each of the stacked tiers comprises a first...
US-1,014,1314 Memories and methods to provide configuration information to controllers
A memory system includes a memory controller and a memory module coupled to the memory controller. One such memory module may include a memory package of a...
US-1,014,1262 Electrically conductive laminate structures
Some embodiments include electrical interconnects. The interconnects may contain laminate structures having a graphene region sandwiched between non-graphene...
US-1,014,1259 Semiconductor devices having electrically and optically conductive vias, and associated systems and methods
Semiconductor devices having one or more vias filled with a transparent and electrically conductive material are disclosed herein. In one embodiment, a...
US-1,014,0225 Impedance adjustment in a memory device
Methods include configuring termination devices of a driver circuit of a memory device, storing a first plurality of trim values representative of the...
US-1,014,0222 Interface components
In an example, an apparatus may have a controller to be coupled to a host, an interface component coupled to the controller, and a plurality of memory devices...
US-1,014,0104 Target architecture determination
Examples of the present disclosure provide apparatuses and methods for target architecture determination. An example method comprises receiving an indication of...
US-1,014,0057 Apparatuses and methods for multiple address registers for a solid state device
The present disclosure includes apparatuses, systems, and methods related to multiple address registers for a solid state device (SSD). An example apparatus...
US-1,014,0040 Memory device with dynamic program-verify voltage calibration
A memory system includes a memory array including a plurality of memory cells; and a controller coupled to the memory array, the controller configured to:...
US-1,013,7481 Methods of removing particles from over semiconductor substrates
Some embodiments include methods of removing particles from over surfaces of semiconductor substrates. Liquid may be flowed across the surfaces and the...
US-1,013,7384 Systems and methods for water desalinization
An apparatus includes a set of atomizers, a housing and a separator. Each atomizer includes an inlet portion that receives an inlet flow of a solution and an...
US-1,013,5465 Error correction methods and apparatuses using first and second decoders
Apparatuses and methods for error correcting data are provided. A first error correction code (ECC) decoder is configured to decode a first codeword to provide...
US-1,013,4982 Array of cross point memory cells
An array of cross point memory cells comprises spaced first lines which cross spaced second lines. Two memory cells are individually between one of two...
US-1,013,4978 Magnetic cell structures, and methods of fabrication
A magnetic cell structure comprises a seed material including tantalum, platinum, and ruthenium. The seed material comprises a platinum portion overlying a...
US-1,013,4969 Vertical solid-state transducers and high voltage solid-state transducers having buried contacts and associated...
Solid-state transducers ("SSTs") and vertical high voltage SSTs having buried contacts are disclosed herein. An SST die in accordance with a particular...
US-1,013,4968 Solid state lighting devices with improved contacts and associated methods of manufacturing
Solid state lighting ("SSL") devices with improved contacts and associated methods of manufacturing are disclosed herein. In one embodiment, an SSL device...
US-1,013,4916 Transistor devices, memory cells, and arrays of memory cells
A transistor device includes a pair of source/drain regions having a channel region there-between. A first gate is proximate the channel region. A gate...
US-1,013,4810 Three dimensional memory array with select device
Three dimensional memory arrays and methods of forming the same are provided. An example three dimensional memory array can include a stack comprising a...
US-1,013,4798 Pixel with strained silicon layer for improving carrier mobility and blue response in imagers
An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag,...
US-1,013,4742 Semiconductor device including a semiconductor substrate, a pillar, and a beam
The semiconductor storage device includes a lower electrode that are vertically extended from a semiconductor substrate, a beam including a first portion...
US-1,013,4741 Methods of forming an elevationally extending conductor laterally between a pair of conductive lines
A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from...
US-1,013,4738 Low power memory device with JFET device structures
There is provided a low power memory device with JFET device structures. Specifically, a low power memory device is provided that includes a plurality memory...
US-1,013,4712 Methods and systems for improving power delivery and signaling in stacked semiconductor devices
Semiconductor die assemblies including stacked semiconductor dies having parallel plate capacitors formed between adjacent pairs of semiconductor dies in the...
US-1,013,4671 3D interconnect multi-die inductors with through-substrate via cores
A semiconductor device having a first die and a second die is provided. The first die of the device includes a first surface and a through-substrate via (TSV)...
US-1,013,4655 Semiconductor device packages with direct electrical connections and related methods
Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. An...
US-1,013,4647 Methods for forming interconnect assemblies with probed bond pads
An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The...
US-1,013,4597 Apparatuses including memory cells with gaps comprising low dielectric constant materials
Various embodiments include apparatuses and electronic devices. One such apparatus can include a first dielectric material and a second dielectric material, and...
US-1,013,4482 Apparatuses and methods for high speed writing test mode for memories
Apparatuses and methods are provided for a high speed writing test mode for memories. An example apparatus includes a memory core, a data terminal coupled to a...
US-1,013,4481 Pre-compensation of memory threshold voltage
Methods of operating a memory include storing a first target data state of multiple possible data states of a first memory cell to be programmed in a target...
US-1,013,4478 Apparatuses and methods for reducing read disturb
Apparatuses and methods for reducing read disturb are described herein. An example apparatus may include a first memory subblock including a first select gate...
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