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Patent # Description
US-9,734,284 Hardware acceleration of short read mapping for genomic and other types of analyses
A scalable FPGA-based solution to the short read mapping problem in DNA sequencing is disclosed which greatly accelerates the task of aligning short length...
US-9,734,097 Apparatuses and methods for variable latency memory operations
Apparatuses and methods for variable latency memory operations are disclosed herein. An example apparatus may include a memory configured to receive an activate...
US-9,734,029 Cooperative memory error detection and repair
Some embodiments include apparatuses and methods having a memory structure included in a memory device and a control unit included in the memory device. The...
US-9,733,908 Dynamic arrays and overlays with bounds policies
Systems and methods are provided for writing code to access data arrays. One aspect provides a method of accessing a memory array. Data is provided within a...
US-9,733,847 Systems and methods for transmitting packets in a scalable memory system protocol
A memory device includes a memory component that store data and a processor. The processor may generate one or more data packets associated with the memory...
US-9,733,304 Semiconductor device test apparatuses
Apparatus for testing semiconductor devices comprising die stacks, the apparatus comprising a substrate having an array of pockets in a surface thereof arranged...
US-D794,774 Stylet handle
US-9,728,538 Three-dimensional devices having reduced contact length
Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with...
US-9,723,672 Self-identifying solid-state transducer modules and associated systems and methods
Self-identifying solid-state transducer (SST) modules and associated systems and methods are disclosed herein. In several embodiments, for example, an SST...
US-9,721,923 Semiconductor package with multiple coplanar interposers
A semiconductor package includes a first interposer, a second interposer, and a gap between the first interposer and the second interposer. The first interposer...
US-9,721,622 Systems with memory segmentation and systems with biasing lines to receive same voltages during accessing
Memory devices, memory arrays, and methods of operation of memory arrays with segmentation. Segmentation elements can scale with the memory cells, and may be...
US-9,717,157 Computer modules with small thicknesses and associated methods of manufacturing
Computer modules with small thicknesses and associated methods of manufacturing are disclosed. In one embodiment, the computer modules can include a module...
US-9,716,225 Memory cells including dielectric materials, memory devices including the memory cells, and methods of forming same
A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold...
US-9,716,023 Methods for temporarily bonding a device wafer to a carrier wafer, and related assemblies
A method of bonding a device wafer to a carrier wafer includes disposing a first adhesive over a central portion of a carrier wafer, the first adhesive having a...
US-9,715,070 Apparatus providing simplified alignment of optical fiber in photonic integrated circuits
A structure for optically aligning an optical fiber to a photonic device and method of fabrication of same. The structure optically aligns an optical fiber to...
US-9,711,228 Apparatus and methods of operating memory with erase de-bias
Methods of operating a memory include developing first and second voltage levels in first and second semiconductor materials, respectively, forming channel...
US-9,711,223 Apparatus and methods including a bipolar junction transistor coupled to a string of memory cells
Some embodiments include apparatus and methods having a string of memory cells, a conductive line and a bipolar junction transistor configured to selectively...
US-9,711,214 Methods, articles and devices for pulse adjustments to program a memory cell
Embodiments disclosed herein may relate to adjusting an aspect of a programming pulse for one or more memory cells, such as based at least in part on one or...
US-9,711,206 Performing logical operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an...
US-9,710,364 Method of detecting false test alarms using test step failure analysis
Identifying false test alarms to a developer. A code build is executed in a test system that includes computing functionality and computing infrastructure that...
US-9,705,028 Light emitting diodes with N-polarity and associated methods of manufacturing
Light emitting diodes ("LEDs") with N-polarity and associated methods of manufacturing are disclosed herein. In one embodiment, a method for forming a light...
US-9,704,876 Semiconductor apparatus with multiple tiers, and methods
Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one...
US-9,704,781 Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods
The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package...
US-9,704,597 Apparatuses and methods for outputting addresses of defective memory cells of a semiconductor device including...
A semiconductor device that includes a plurality of memory cells assigned with addresses that are different from each other, a redundant memory cell replacing a...
US-9,704,561 Device having multiple switching buffers for data paths controlled based on IO configuration modes
A device includes a first data terminal, a second data terminal, a first switching buffer coupled between a data node and the first data terminal and a second...
US-9,704,542 Automatic word line leakage measurement circuitry
The present invention is a circuit and method for measuring leakage on the plurality of word lines in a memory device. In one embodiment, a memory device may...
US-9,703,574 Overflow detection and correction in state machine engines
State machine engines are disclosed, including those having an inter-rank bus control system, which may include a register. The state machine engine may include...
US-9,697,907 Apparatuses and methods using dummy cells programmed to different states
Apparatuses and methods for reducing capacitive loading are described. One apparatus includes a first memory string including first and second dummy memory...
US-9,697,876 Vertical bit vector shift in memory
Examples of the present disclosure provide apparatuses and methods for vertical bit vector shift in a memory. An example method comprises storing a vertical bit...
US-9,696,920 Systems and methods for improving efficiencies of a memory system
A memory device includes a memory component that store data. The memory device also includes a processor that receives a signal indicating that the memory...
US-9,692,455 Multi channel memory with flexible code-length ECC
Apparatuses and methods for error correction and detection of data from memory on a plurality of channels are described. An example apparatus includes: a first...
US-9,691,955 Solid state lighting devices with improved contacts and associated methods of manufacturing
Solid state lighting ("SSL") devices with improved contacts and associated methods of manufacturing are disclosed herein. In one embodiment, an SSL device...
US-9,691,817 Magnetic tunnel junctions and methods of forming magnetic tunnel junctions
A method of forming a line of magnetic tunnel junctions includes forming magnetic recording material over a substrate, non-magnetic material over the recording...
US-9,691,744 Semiconductor memory device including output buffer
A semiconductor module includes a module substrate, a line pattern provided to the module substrate, first and second semiconductor chips on the module...
US-9,691,465 Thyristors, methods of programming thyristors, and methods of forming thyristors
Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV...
US-9,691,443 Apparatuses and methods for compensating for process, voltage, and temperature variation in a memory
Systems and methods are described for compensating for variations in process, voltage, temperature, or combinations thereof in an apparatus. An example...
US-9,690,961 Systems and methods to determine kinematical parameters using RFID tags
Systems and methods to determine kinematical parameters of physical objects using radio frequency identification (RFID) tags attached to the objects. In one...
US-9,690,653 Semiconductor device having error correction code (ECC) circuit
An apparatus may comprise an ECC circuit configured to receive read data from a memory cell array to correct, an error bit contained in a data portion of the...
US-9,690,502 Systems and methods for segmenting data structures in a memory system
A memory device may include a memory component that stores data and a processor. The processor may map one or more banks or one or more virtual banks in the...
US-9,685,448 Semiconductor device
Disclosed herein is a method includes: forming first and second cavities, the first cavity having a first width, each of the second cavities having a second...
US-9,685,234 Apparatuses and methods for performing multiple memory operations
The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory...
US-9,679,964 Semiconductor constructions having peripheral regions with spaced apart mesas
Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy...
US-9,679,852 Semiconductor constructions
Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the...
US-9,676,944 Methods of increasing the solubility of materials in supercritical carbon dioxide
Methods of increasing the solubility of a base in supercritical carbon dioxide include forming a complex of a Lewis acid and the base, and dissolving the...
US-9,672,908 Apparatuses and methods of reading memory cells based on response to a test pulse
The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to memory arrays and methods of...
US-9,666,245 Device having multiple channels with calibration circuit shared by multiple channels
An apparatus includes a first channel, a second channel and a calibration circuit. The first channel includes a first command control circuit. The second...
US-9,665,301 Methods and devices for storing user data along with addresses corresponding to physical pages storing valid data
Methods, and corresponding devices, for storing user data along with a plurality of addresses corresponding to physical pages storing valid data corresponding...
US-9,665,083 Counter operation in a state machine lattice
Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting...
US-9,659,630 Multi-mode memory device and method having stacked memory dice, a logic die and a command processing circuit...
Memory device systems, systems and methods are disclosed, such as those involving a plurality of stacked memory device dice and a logic die connected to each...
US-9,659,420 Security system of information processing apparatus and security control apparatus
In a security system, a security control apparatus 300 includes an authentication processing unit 31 for perform an authentication on whether the mobile...
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