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Patent # Description
US-9,865,859 Stacked-type secondary battery
A structure with suppressed thickness and high-density when battery cells of a thin-film-solid secondary battery are stacked. Adjacent battery cells are stacked...
US-9,865,812 Methods of forming conductive elements of semiconductor devices and of forming memory cells
Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first...
US-9,865,611 Multi-tiered semiconductor devices and associated methods
Methods of fabricating multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, a first...
US-9,865,578 Methods of manufacturing multi-die semiconductor device packages and related assemblies
Methods of making semiconductor device packages may involve attaching a first semiconductor die to a carrier wafer, an inactive surface of the first...
US-9,865,516 Wafers having a die region and a scribe-line region adjacent to the die region
A wafer and a forming method thereof are provided. The wafer has a die region and a scribe-line region adjacent to the die region, and includes a conductive...
US-9,865,456 Methods of forming silicon nitride by atomic layer deposition and methods of forming semiconductor structures
Methods of forming silicon nitride. Silicon nitride is formed on a substrate by atomic layer deposition at a temperature of less than or equal to about...
US-9,865,359 Semiconductor device including fuse circuit
Disclosed here is a semiconductor device that comprises a plurality of input nodes configured to be supplied with input signals, a decoder coupled to the input...
US-9,865,355 Apparatuses and methods for transistor protection by charge sharing
Apparatuses and methods for protecting transistors through charge sharing are disclosed herein. An example apparatus includes a transistor comprising a gate...
US-9,865,339 Memory devices with reduced operational energy in phase change material and methods of operation
Methods of forming and operating phase change memory devices include adjusting an activation energy barrier between a metastable phase and a stable phase of a...
US-9,865,324 Method and apparatus for decoding commands
Method and Apparatuses for of decoding commands for a semiconductor device are described. An example method includes receiving a portion of a command at first...
US-9,865,317 Methods and apparatuses including command delay adjustment circuit
Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that...
US-9,865,311 Memory device including current generator plate
Some embodiments include an apparatus and methods using a first conductive material located in a first level of an apparatus (e.g., a memory device); a second...
US-9,864,879 Secure subsystem
An apparatus for performing secure operations with a dedicated secure processor is described in one embodiment. The apparatus includes security firmware...
US-9,864,697 Memory having a static cache and a dynamic cache
The present disclosure includes memory having a static cache and a dynamic cache. A number of embodiments include a memory, wherein the memory includes a first...
US-9,864,362 Method for setting and/or monitoring operating parameters of a workpiece processing machine
A method for setting or monitoring operating parameters of a workpiece processing machine having a tool holder and means for moving a workpiece and the holder...
US-9,853,212 Resistive switching in memory cells
Methods, devices, and systems associated with oxide based memory can include a method of forming a resistive switching region of a memory cell. Forming a...
US-9,853,211 Array of cross point memory cells individually comprising a select device and a programmable device
A method of forming an array of cross point memory cells comprises forming spaced conductive lower electrode pillars for individual of the memory cells being...
US-9,853,046 Apparatuses and methods for forming multiple decks of memory cells
Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck...
US-9,853,037 Integrated assemblies
Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with...
US-9,853,027 Methods of forming patterns, and apparatuses comprising FinFETs
Some embodiments include a method of forming a pattern. A semiconductor substrate has first and second rows extending along a first direction, and which...
US-9,852,953 CMOS fabrication
A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second...
US-9,852,813 Methods, apparatus, and systems to repair memory
Methods, apparatus and systems pertain to performing READ, WRITE functions in a memory which is coupled to a repair controller. One such repair controller could...
US-9,852,809 Test mode circuit for memory apparatus
Apparatuses for error detection and correction for a semiconductor device are described. An example apparatus includes: at least one memory cell array including...
US-9,852,794 Systems, methods and devices for programming a multilevel resistive memory cell
Embodiments disclosed herein may relate to programming a multi-level memory cell with programming pulse sequences that comprise forward-biased and...
US-9,851,913 Methods for operating a memory array
Methods of operating memory arrays are described. In various embodiments, a method includes determining a pattern to be written to a memory array, the pattern...
US-9,851,249 Method for enabling system operation based on a spectral fingerprint
A sensor system is disclosed, wherein the sensor system provides output data only when the error between a plurality of measured absorption wavelengths of a gas...
US-9,847,117 Dynamic reference voltage determination
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first value may be written to a first memory cell and a second...
US-9,842,976 Vertical light emitting devices with nickel silicide bonding and methods of manufacturing
Various embodiments of light emitting devices, assemblies, and methods of manufacturing are described herein. In one embodiment, a method for manufacturing a...
US-9,842,965 Textured devices
Epitaxial growth methods and devices are described that include a textured surface on a substrate in a liquid crystal device. Geometry of the textured surface...
US-9,842,847 Drain select gate formation methods and apparatus
Some embodiments include a string of charge storage devices formed along a vertical channel of semiconductor material; a gate region of a drain select gate...
US-9,842,840 Transistors and memory arrays
Some embodiments include a transistor having a semiconductor material with a trench extending downwardly therein. The semiconductor material has a first post...
US-9,842,839 Memory cell, an array of memory cells individually comprising a capacitor and a transistor with the array...
A method of forming an array of capacitors and access transistors there-above comprises forming access transistor trenches partially into insulative material....
US-9,842,661 Ferroelectric memory cell recovery
Methods, systems, and devices for recovering fatigued ferroelectric memory cells are described. Recovery voltages may be applied to a ferroelectric memory cell...
US-9,842,652 Memory array with power-efficient read architecture
Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings...
US-9,842,649 Resistance variable element methods and apparatuses
Apparatus and methods are disclosed, including a method that performs a first operation on a first resistance variable element using a common source voltage, a...
US-9,842,633 Tracking and correction of timing signals
Various embodiments include apparatus and methods to track and/or correct timing signals. Timing signals generated from an interface can be compared to the...
US-9,842,058 Locking entries into translation lookaside buffers
Two translation lookaside buffers may be provided for simpler operation in some embodiments. A hardware managed lookaside buffer may handle traditional...
US-9,838,624 Anti-eclipse circuitry with tracking of floating diffusion reset level
Imagers and associated devices and systems are disclosed herein. In one embodiment, an imager includes a pixel array and control circuitry operably coupled to...
US-9,837,383 Interconnect structure with improved conductive properties and associated systems and methods
Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive...
US-9,831,428 Memory cell with independently-sized electrode
Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle...
US-9,831,287 Memory devices and memory device forming methods
Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive...
US-9,831,246 JFET device structures and methods for fabricating the same
In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a...
US-9,831,002 Apparatuses and methods for operating a memory device
Subject matter described pertains to apparatuses and methods for operating a memory device.
US-9,830,999 Comparison operations in memory
Examples of the present disclosure provide apparatuses and methods related to performing comparison operations in a memory. An example apparatus might include a...
US-9,830,970 Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming...
Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and...
US-9,830,955 Data shifting
The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense...
US-9,830,267 Continuous page read for memory
Subject matter disclosed herein relates to techniques to read memory in a continuous fashion.
US-9,830,087 Memory wear leveling
Systems and methods for intra-sector re-ordered wear leveling include: detecting, in a memory device, a high wear sub-sector having a high wear level, the...
US-9,824,770 Apparatuses and methods for flexible fuse transmission
Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each...
US-9,824,725 Semiconductor device with single ended main I/O line
Apparatuses included a single-ended main input/output line in a semiconductor device are described. An example apparatus includes: a pair of differential data...
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