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Patent # Description
US-8,963,156 Semiconductor devices including WiSX
Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon...
US-8,963,121 Vertical solid-state transducers and high voltage solid-state transducers having buried contacts and associated...
Solid-state transducers ("SSTs") and vertical high voltage SSTs having buried contacts are disclosed herein. An SST die in accordance with a particular...
US-8,962,482 Multi-layer interconnect with isolation layer
An integrated circuit interconnect is fabricated by using a mask to form a via in an insulating layer for a conductive plug. After the plug is formed in the...
US-8,962,465 Methods of forming gated devices
Some embodiments include methods of forming gated devices. An upper region of a semiconductor material is patterned into a plurality of walls that extend...
US-8,962,460 Methods of selectively forming metal-doped chalcogenide materials, methods of selectively doping chalcogenide...
Methods of selectively forming a metal-doped chalcogenide material comprise exposing a chalcogenide material to a transition metal solution, and incorporating...
US-8,962,449 Methods for processing semiconductor devices
Methods of forming a semiconductor structure include exposing a carrier substrate to a silane material to form a coating, removing a portion of the coating at...
US-8,962,447 Bonded strained semiconductor with a desired surface orientation and conductance direction
According to various method embodiments, a semiconductor layer is oriented to a substrate. The semiconductor layer has a surface orientation and is oriented to...
US-8,962,446 Methods of forming oxides, methods of forming semiconductor constructions, and methods of forming isolation regions
Some embodiments include methods of forming isolation regions in which spin-on material (for example, polysilazane) is converted to a silicon dioxide-containing...
US-8,962,445 Method of manufacture of semiconductor isolation structure
A method of formation of an isolation structure for vertical semiconductor devices, the resulting isolation structure, and a memory device to prevent leakage...
US-8,962,431 Methods of forming metal silicide-comprising material and methods of forming metal silicide-comprising contacts
A method of forming metal silicide-comprising material includes forming a substrate which includes a first stack having second metal over first metal over...
US-8,962,401 Double gated 4F2 dram CHC cell and methods of fabricating the same
A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein...
US-8,962,387 Methods of forming memory cells
Some embodiments include methods of forming memory cells in which a metal oxide material is formed over a first electrode material, an oxygen-sink material is...
US-8,962,384 Memory cells having heaters with angled sidewalls
Memory cells having heaters with angled sidewalls and methods of forming the same are described herein. As an example, a method of forming an array of resistive...
US-8,959,759 Method for assembling computer modules small in thickness
Computer modules with small thicknesses and associated methods of manufacturing are disclosed. In one embodiment, the computer modules can include a module...
US-8,959,326 Memory device initiate and terminate boot commands
Methods of operating memory devices and electronic systems having memory devices include initiating a boot mode of operation of the memory device in response to...
US-8,959,295 Bit inversion in memory devices
Bit inversions occurring in memory systems and apparatus are provided. Data is acquired from a source destined for a target. As the data is acquired from the...
US-8,958,260 Systems and methods for voltage sensing and reporting
Semiconductor devices comprising at least one voltage sensor for sensing an operating voltage associated with an operational circuit of the semiconductor...
US-8,958,256 Apparatuses and methods for improved memory operation times
Apparatuses and methods for improved memory cycle times are disclosed. An example apparatus may include first and second lines and a sense amplifier. The sense...
US-8,958,242 Thermal treatment of flash memories
A memory controller can provide current to a heater in a flash memory to reduce cycling induced errors. If necessary, after heating, the memory may be...
US-8,958,233 Stabilization of resistive memory
The present disclosure includes apparatuses and methods including stabilization of resistive memory. A number of embodiments include applying a programming...
US-8,958,052 Multi-method and device with an advanced acousto-optic deflector (AOD) and a dense brush of flying spots
The technology disclosed relates to improved acousto-optic deflectors (AODs). In particular, it relates to compensation for subtle effects not previously...
US-8,957,495 Memory cell profiles
Examples of the present disclosure provide devices and methods for processing a memory cell. A method embodiment includes removing a key-hole shaped column from...
US-8,957,483 Electrically conductive lines and integrated circuitry comprising a line of recessed access devices
A method of forming an electrically conductive buried line and an electrical contact thereto includes forming of a longitudinally elongated conductive line...
US-8,957,403 Select devices including an open volume, and related methods, memory devices, and electronic systems
Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a...
US-8,956,981 Methods of eliminating pattern collapse on photoresist patterns
A stabilizing solution for treating photoresist patterns and methods of preventing profile abnormalities, toppling and resist footing are disclosed. The...
US-8,956,976 Methods of processing semiconductor substrates in forming scribe line alignment marks
A method of processing a semiconductor substrate in forming scribe line alignment marks includes forming pitch multiplied non-circuitry features within scribe...
US-8,956,974 Devices, systems, and methods related to planarizing semiconductor devices after forming openings
Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a stop layer and...
US-8,956,713 Methods of forming a stamp and a stamp
A method of patterning a substrate is disclosed. An ink material is chemisorbed to at least one region of a stamp and the chemisorbed ink material is...
US-8,956,498 Apparatuses facilitating fluid flow into via holes, vents, and other openings communicating with surfaces of...
A method for removing material from surfaces of at least a portion of at least one recess or at least one aperture extending into a surface of a substrate...
US-8,954,825 Apparatuses and methods including error correction code organization
Some embodiments include apparatuses and methods having first memory cells, a first access line configured to access the first memory cells, second memory...
US-8,954,824 Error detection or correction of stored signals after one or more heat events in one or more memory devices
In some embodiments, a non-volatile memory device comprises an error correction component to re-program at least a portion of a non-volatile memory array at...
US-8,954,818 Error detection and correction scheme for a memory device
An embodiment of a method of operating a memory device includes reading data from a memory array into a data buffer, checking the data using a first checker,...
US-8,954,687 Memory hub and access method having a sequencer and internal row caching
A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices. The...
US-8,954,660 Execute-in-place mode configuration for serial non-volatile memory
Example embodiments for configuring a serial non-volatile memory device for an execute-in-place mode may comprise a non-volatile configuration register to store...
US-8,953,396 NAND interface
A NAND interface having a reduced pin count configuration, in which all command and address functions and operations of the NAND are provided serially on a...
US-8,953,387 Apparatuses and methods for efficient write in a cross-point array
A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and...
US-8,953,379 Apparatuses and methods of reprogramming memory cells
Apparatuses and methods for reprogramming memory cells are described. One or more methods for memory cell operation includes programming a number of memory...
US-8,953,364 Voltage rail noise sensing circuit and method
Apparatus and methods level shift a direct current (DC) component of a voltage rail signal from a first DC level to a second DC level such that voltage rail...
US-8,953,360 Apparatus and method for reading a phase-change memory cell
An apparatus and a method for reading a phase-change memory cell are described. A circuit includes a current ramp circuit. A current forcing module is coupled...
US-8,953,355 Memory dies, stacked memories, memory devices and methods
Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One...
US-8,953,056 Method, apparatus and system for dynamic range estimation of imaged scenes
A method, apparatus, and system for dynamic range estimation of imaged scenes for automatic exposure control. For a given exposure time setting, certain areas...
US-8,952,515 Signal shifting to allow independent control of identical stacked memory modules
Apparatus and methods are disclosed to allow independent control of stacked memory modules. In one embodiment, an apparatus may comprise first, second, and...
US-8,952,485 Isolation trench fill using oxide liner and nitride etch back technique with dual trench depth capability
An oxide layer is formed over a substrate having a smaller isolation trench and a large isolation trench. A nitride layer is formed over the oxide layer such...
US-8,952,482 Three-dimensional devices having reduced contact length
Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with...
US-8,952,437 DRAM cell design with folded digitline sense amplifier
The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a...
US-8,952,418 Gated bipolar junction transistors
Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a...
US-8,952,413 Etched trenches in bond materials for die singulation, and associated systems and methods
Etched trenches in a bond material for die singulation, and associated systems and methods are disclosed. A method for solid state transducer device singulation...
US-8,952,406 Lighting devices including patterned optical components and associated devices, systems, and methods
Lighting devices including light-emitting diodes and associated devices, systems, and methods are disclosed herein. A lighting device configured in accordance...
US-8,952,402 Solid-state radiation transducer devices having flip-chip mounted solid-state radiation transducers and...
Solid-state radiation transducer (SSRT) devices and methods of manufacturing and using SSRT devices are disclosed herein. One embodiment of the SSRT device...
US-8,952,399 Light emitting device comprising a wavelength conversion layer having indirect bandgap energy and made of an...
Various embodiments of light emitting devices with efficient wavelength conversion and associated methods of manufacturing are described herein. In one...
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