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Patent # Description
US-8,956,974 Devices, systems, and methods related to planarizing semiconductor devices after forming openings
Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a stop layer and...
US-8,956,713 Methods of forming a stamp and a stamp
A method of patterning a substrate is disclosed. An ink material is chemisorbed to at least one region of a stamp and the chemisorbed ink material is...
US-8,956,498 Apparatuses facilitating fluid flow into via holes, vents, and other openings communicating with surfaces of...
A method for removing material from surfaces of at least a portion of at least one recess or at least one aperture extending into a surface of a substrate...
US-8,954,825 Apparatuses and methods including error correction code organization
Some embodiments include apparatuses and methods having first memory cells, a first access line configured to access the first memory cells, second memory...
US-8,954,824 Error detection or correction of stored signals after one or more heat events in one or more memory devices
In some embodiments, a non-volatile memory device comprises an error correction component to re-program at least a portion of a non-volatile memory array at...
US-8,954,818 Error detection and correction scheme for a memory device
An embodiment of a method of operating a memory device includes reading data from a memory array into a data buffer, checking the data using a first checker,...
US-8,954,687 Memory hub and access method having a sequencer and internal row caching
A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices. The...
US-8,954,660 Execute-in-place mode configuration for serial non-volatile memory
Example embodiments for configuring a serial non-volatile memory device for an execute-in-place mode may comprise a non-volatile configuration register to store...
US-8,953,396 NAND interface
A NAND interface having a reduced pin count configuration, in which all command and address functions and operations of the NAND are provided serially on a...
US-8,953,387 Apparatuses and methods for efficient write in a cross-point array
A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and...
US-8,953,379 Apparatuses and methods of reprogramming memory cells
Apparatuses and methods for reprogramming memory cells are described. One or more methods for memory cell operation includes programming a number of memory...
US-8,953,364 Voltage rail noise sensing circuit and method
Apparatus and methods level shift a direct current (DC) component of a voltage rail signal from a first DC level to a second DC level such that voltage rail...
US-8,953,360 Apparatus and method for reading a phase-change memory cell
An apparatus and a method for reading a phase-change memory cell are described. A circuit includes a current ramp circuit. A current forcing module is coupled...
US-8,953,355 Memory dies, stacked memories, memory devices and methods
Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One...
US-8,953,056 Method, apparatus and system for dynamic range estimation of imaged scenes
A method, apparatus, and system for dynamic range estimation of imaged scenes for automatic exposure control. For a given exposure time setting, certain areas...
US-8,952,515 Signal shifting to allow independent control of identical stacked memory modules
Apparatus and methods are disclosed to allow independent control of stacked memory modules. In one embodiment, an apparatus may comprise first, second, and...
US-8,952,485 Isolation trench fill using oxide liner and nitride etch back technique with dual trench depth capability
An oxide layer is formed over a substrate having a smaller isolation trench and a large isolation trench. A nitride layer is formed over the oxide layer such...
US-8,952,482 Three-dimensional devices having reduced contact length
Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with...
US-8,952,437 DRAM cell design with folded digitline sense amplifier
The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a...
US-8,952,418 Gated bipolar junction transistors
Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a...
US-8,952,413 Etched trenches in bond materials for die singulation, and associated systems and methods
Etched trenches in a bond material for die singulation, and associated systems and methods are disclosed. A method for solid state transducer device singulation...
US-8,952,406 Lighting devices including patterned optical components and associated devices, systems, and methods
Lighting devices including light-emitting diodes and associated devices, systems, and methods are disclosed herein. A lighting device configured in accordance...
US-8,952,402 Solid-state radiation transducer devices having flip-chip mounted solid-state radiation transducers and...
Solid-state radiation transducer (SSRT) devices and methods of manufacturing and using SSRT devices are disclosed herein. One embodiment of the SSRT device...
US-8,952,399 Light emitting device comprising a wavelength conversion layer having indirect bandgap energy and made of an...
Various embodiments of light emitting devices with efficient wavelength conversion and associated methods of manufacturing are described herein. In one...
US-8,952,395 Wafer-level solid state transducer packaging transducers including separators and associated systems and methods
Wafer-level packaging of solid-state transducers ("SSTs") is disclosed herein. A method in accordance with a particular embodiment includes forming a transducer...
US-8,952,299 Dual resistance heater for phase change devices and manufacturing method thereof
A dual resistance heater for a phase change material region is formed by depositing a resistive material. The heater material is then exposed to an implantation...
US-8,951,910 Methods for fabricating and forming semiconductor device structures including damascene structures
A method and apparatus for providing a conductive structure adjacent to a damascene conductive structure in a semiconductor device structure. The semiconductor...
US-8,951,903 Graded dielectric structures
Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of...
US-8,951,880 Dielectrics containing at least one of a refractory metal or a non-refractory metal
Electronic apparatus and methods of forming the electronic apparatus may include one or more insulator layers having a refractory metal and a non-refractory...
US-8,951,865 Memory arrays where a distance between adjacent memory cells at one end of a substantially vertical portion is...
Memory arrays and their formation are disclosed. One such memory array has a string of series-coupled memory cells with a substantially vertical portion. A...
US-8,951,858 Imager device with electric connections to electrical device
An imager device is disclosed including a first substrate having an array of photo-sensitive elements formed thereon, a first conductive layer formed above the...
US-8,951,842 Semiconductor growth substrates and associated systems and methods for die singulation
Semiconductor growth substrates and associated systems and methods for die singulation are disclosed. A representative method for manufacturing semiconductor...
US-8,951,832 Variable-resistance material memories and methods
Variable-resistance memory material cells are contacted by vertical bottom spacer electrodes. Variable-resistance material memory spacer cells are contacted...
US-8,951,829 Resistive switching in memory cells
Methods, devices, and systems associated with oxide based memory can include a method of forming a resistive switching region of a memory cell. Forming a...
US-8,951,433 Compositions for use in semiconductor devices
An improved composition and method for cleaning a surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k...
US-8,951,354 Megasonic cleaning with controlled boundary layer thickness and associated systems and methods
Megasonic cleaning systems and methods of using megasonic pressure waves to impart cavitation energy proximate a surface of a microelectronic substrate are...
US-8,949,626 Protection of security parameters in storage devices
Security parameters used to encrypt data stored on a storage device may be protected using embodiments of systems and methods described herein. During a resize...
US-8,949,574 Low power, hash-content addressable memory architecture
A method is comprised of inputting a comparand word to a plurality of hash circuits, each hash circuit being responsive to a different portion of the comparand...
US-8,949,538 Interface device accessing a stack of memory dice and a solid state disk
Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more...
US-8,949,492 Apparatus including buffer allocation management and related methods
Memory system controllers can include hardware masters, first buffers, and a switch coupled to the hardware masters and to the first buffers. The switch can...
US-8,948,192 Data switch
A data switch for an integrated circuit comprising at least one link for receiving input data packets from an independently modulated spread spectrum clock...
US-8,947,965 Techniques for providing a direct injection semiconductor memory device
Techniques for providing a direct injection semiconductor memory device are disclosed. In one exemplary embodiment, the techniques may be realized as a direct...
US-8,947,952 Input-output line sense amplifier having adjustable output drive capability
An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line...
US-8,947,946 Leakage measurement systems
Described examples include leakage measurement systems and methods for measuring leakage current between a word line at a boosted voltage and a word line at a...
US-8,947,934 Sharing local control lines across multiple planes in a memory device
Memory devices, methods for accessing a memory cell, and memory systems are disclosed. One such memory device includes a plurality of planes of memory cells....
US-8,947,570 Method, apparatus, and system providing a rectilinear pixel grid with radially scaled pixels
Pixels in an imaging device pixel array are sized according to their geographic location in the pixel array to compensate for various optical ...
US-8,947,144 Apparatuses and methods for duty cycle adjustment
Apparatuses and methods for duty cycle adjustment are disclosed herein. An example apparatus may include a node, a phase mixer, and a duty cycle adjuster...
US-8,947,141 Differential amplifiers, clock generator circuits, delay lines and methods
A differential amplifier may be configured to have a duty cycle and/or gain that is adjustable, such as by adjusting the switch points of circuitry in the...
US-8,946,907 Self-aligned nano-structures
A method for creating structures in a semiconductor assembly is provided. The method includes etching apertures into a dielectric layer and applying a polymer...
US-8,946,903 Electrically conductive laminate structure containing graphene region
Some embodiments include electrical interconnects. The interconnects may contain laminate structures having a graphene region sandwiched between non-graphene...
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