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Patent # Description
US-9,021,176 Memory device and method with on-board cache system for facilitating interface with multiple processors, and...
A memory device includes an on-board cache system that facilitates the ability of the memory device to interface with a plurality of processors operating in a...
US-9,021,125 Control path I/O virtualisation
There is disclosed a data switch in combination with a proxy controller, the data switch being configured for routing data traffic and control traffic between...
US-9,019,788 Techniques for accessing memory cells
Techniques for accessing memory cells are disclosed. In one particular embodiment, the techniques may be realized as an apparatus providing voltage to a high...
US-9,019,785 Data shifting via a number of isolation devices
The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense...
US-9,019,779 Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules
A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality...
US-9,019,774 Method and system for minimizing number of programming pulses used to program rows of non-volatile memory cells
A flash memory device programs cells in each row in a manner that minimizes the number of programming pulses that must be applied to the cells during...
US-9,019,766 Biasing system and method
Embodiments are provided that include a memory system that includes a memory system, having an access device coupled between a global line and a local line and...
US-9,019,762 Methods of operating memory devices
Methods of operating a memory device include determining whether each memory cell selected for a sense operation has any data state of a first subset of data...
US-9,019,759 Techniques for providing a semiconductor memory device
Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor...
US-9,019,754 State determination in resistance variable memory
An evaluation signal is applied to a memory cell in an array of resistance variable memory cells. The evaluation signal is configured to cause the memory cell...
US-9,018,751 Semiconductor module system having encapsulated through wire interconnect (TWI)
A semiconductor module system includes a module substrate and a semiconductor substrate having a through wire interconnect bonded to an electrode on the module...
US-9,018,059 Memory devices having reduced interference between floating gates and methods of fabricating such devices
A memory array comprising transistors having isolated inter-gate dielectric regions with respect to one another. Transistors are formed such that each of the...
US-9,015,935 Method for manufacturing probe card
A method for manufacturing a probe card includes inserting an attaching portion of each probe into one of first through holes provided on a probe substrate at...
US-9,015,934 Method for manufacturing probe card
A method for manufacturing a probe card prepares a plurality of probes, each having a metal layer on an attaching portion, and hot-melt material covering the...
US-9,015,440 Autonomous memory subsystem architecture
An autonomous sub-system receives a database downloaded from a host controller. A controller monitors bus traffic and/or allocated resources in the subsystem...
US-9,015,390 Active memory data compression system and method
An integrated circuit active memory device receives task commands from a component in a host computer system that may include the active memory device. The host...
US-9,015,356 Memory controllers, memory systems, solid state drives and methods for processing a number of commands
The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end...
US-9,014,318 Self-calibrating continuous-time equalization
Embodiments of the invention comprise a continuous-time equalizer for reducing ISI in data received from a communication channel, and methods and circuitry for...
US-9,013,942 Sense amplifier having loop gain control
Memories, sense amplifiers, and methods for amplifying a current input are disclosed, including a sense amplifier including a bias circuit configured to provide...
US-9,013,044 Through wire interconnect (TWI) for semiconductor components having wire in via and bonded connection with...
A through wire interconnect for a semiconductor substrate includes a via extending through the semiconductor substrate from the first side to the second side...
US-9,012,318 Etching polysilicon
Methods and compositions for etching polysilicon including aqueous compositions containing nitric acid and ammonium fluoride, and apparatus formed thereby.
US-9,012,253 Gallium nitride wafer substrate for solid state lighting devices, and associated systems and methods
Gallium nitride wafer substrate for solid state lighting devices, and associated systems and methods. A method for making an SSL device substrate in accordance...
US-9,009,570 Integrity of an address bus
A method for improving address integrity in a memory system generates error correction data corresponding to a memory address. The error correction data is...
US-9,009,556 Error correction and recovery in chained memory architectures
Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a memory unit configured to receive data...
US-9,009,394 Serial flash memory with a configurable number of dummy clock cycles
Apparatus and methods configure a serial flash memory device. A value in a configuration register configures the number of dummy clock cycles to provide prior...
US-9,009,357 Method and apparatus for field firmware updates in data storage systems
Data storage devices and methods for updating firmware are disclosed. For example, one such data storage device includes a device firmware and a controller,...
US-9,007,867 Loading trim address and trim data pairs
Methods of loading trim address and trim data pairs to a trim register array, and apparatus configured to perform such methods. The methods maintain a...
US-9,007,860 Sub-block disabling in 3D memory
Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of...
US-9,007,832 Methods for programming a memory device and memory devices
Methods for programming memory cells and memory devices are disclosed. One such method for programming includes performing a program verify operation of a group...
US-9,007,831 Memory devices with different sized blocks of memory cells and methods
In an embodiment, each block of a plurality of blocks includes a respective plurality of strings of memory cells, where each of the plurality of strings of a...
US-9,007,822 Complementary decoding for non-volatile memory
Decoding and decoder circuits in memory devices are disclosed. Array lines are biased or floated as memory device operations are performed in the memory device....
US-9,007,818 Memory cells, semiconductor device structures, systems including such cells, and methods of fabrication
Memory cells including cell cores having free regions are disclosed. The free regions exhibit a strain that affects a magnetization orientation within the cell...
US-9,006,859 Semiconductor structures and devices
Methods of forming semiconductor structures that include bodies of a semiconductor material disposed between rails of a dielectric material are disclosed. Such...
US-9,006,702 Semiconductor structure including a zirconium oxide material
Semiconductor structures including a zirconium oxide material and methods of forming the same are described herein. As an example, a semiconductor structure can...
US-9,006,075 Memory cells, semiconductor devices including such cells, and methods of fabrication
Memory cells are disclosed, which cells include a cell material and an ion-source material over the cell material. A discontinuous interfacial material is...
US-9,006,060 N-type field effect transistors, arrays comprising N-type vertically-oriented transistors, methods of forming...
An n-type field effect transistor includes silicon-comprising semiconductor material comprising a pair of source/drain regions having a channel region...
US-9,005,473 Gaseous compositions comprising hydrogen fluoride and an alkylated ammonia derivative
A method of removing at least a portion of a silicon oxide material is disclosed. The silicon oxide is removed by exposing a semiconductor structure comprising...
US-9,005,463 Methods of forming a substrate opening
A method of forming a substrate opening includes forming a plurality of side-by-side openings in a substrate. At least some of immediately adjacent side-by-side...
US-9,005,458 Photonic device structure and method of manufacture
Disclosed method and apparatus embodiments provide a photonic device with optical isolation from a supporting substrate. A generally rectangular cavity in cross...
US-9,003,651 Methods for integrated circuit fabrication with protective coating for planarization
Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction...
US-9,003,177 Data security for digital data storage
A computing system includes data encryption in the data path between a data source and data storage devices. The data storage devices may be local or they may...
US-9,001,594 Apparatuses and methods for adjusting a path delay of a command path
Apparatuses and method for adjusting a path delay of a command path are disclosed. In an example apparatus, a command path configured to provide a command from...
US-9,001,584 Sub-block decoding in 3D memory
Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of...
US-9,001,577 Memory cell sensing
This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first memory cell coupled to a first data line,...
US-9,001,575 Encoding program bits to decouple adjacent wordlines in a memory device
Subject matter disclosed herein relates to memory operations regarding encoding program bits to be programmed into a memory array.
US-9,001,573 Method and apparatuses for programming memory cells
Methods and apparatus for programming memory cells in a memory array are disclosed. A most recent programming time is determined, the most recent programming...
US-9,001,561 Performing forming processes on resistive memory
The present disclosure includes apparatuses and methods for performing forming processes on resistive memory. A number of embodiments include applying a...
US-9,001,548 Memory device interface methods, apparatus, and systems
Apparatus and systems for memory system are provided. In an example, an interface chip can include a memory controller configured to couple to a processor and...
US-9,000,893 Food source information transferring system and method for a meat-packing facility
A food source information transferring system for a livestock meat-packing facility and a related method are disclosed. In one embodiment, the food source...
US-9,000,836 Voltage generator circuit
Embodiments are provided that include a circuit for generating voltage in a memory. One such circuit includes a charge pump circuit including a first...
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