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NAND architecture memory with voltage sensing
A NAND architecture non-volatile memory voltage sensing data read/verify process and sense amplifier has been described that senses data in floating gate or...
Electronic devices formed of two or more substrates connected together,
electronic systems comprising...
Electronic devices comprise a first substrate and a second substrate. The first substrate comprises circuitry including a plurality of conductive traces at...
Lithographic printing system with placement corrections
The technology disclosed relates to methods and devices that compensate for displacements in a pattern or deformations of a workpiece. In particular, this...
Pattern generators, calibration systems and methods for patterning
A pattern generator includes: a writing tool and a calibration system. The writing tool is configured to generate a pattern on a workpiece arranged on a stage....
Circuits and methods for clock signal duty-cycle correction
Duty-cycle correction circuits, clock distribution networks, and methods for correcting duty-cycle distortion are disclosed, including methods and apparatus for...
Fast measurement initialization for memory
Systems and methods for synchronization of clock signals are disclosed. In a feedback system such as a delay-lock loop circuit, delays to be applied can be...
Methods and apparatuses including an adjustable termination impedance
Methods of adjusting a centerline voltage of a data signal are described, along with apparatuses to adjust the centerline voltage. In one such method, portions...
Self-aligned, integrated circuit contact
This document discusses, among other things, example systems including integrated circuit contacts configured to reduce the likelihood of shorting to unrelated...
Forming array contacts in semiconductor memories
Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks...
Voltage-controlled semiconductor inductor and method
A voltage-controlled semiconductor inductor and method is provided. According to various embodiments, the voltage-controlled inductor includes a conductor...
Integrated circuit arrays and semiconductor constructions
Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting...
Forming resistive random access memories together with fuse arrays
A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same...
Ambient infrared detection in solid state sensors
A solid state imaging device includes an array of active pixels and an infrared cut filter formed over the sensor. Optionally, a slot in the infrared cut filter...
Methods for forming a semiconductor structure
Methods of forming a Ni material on a bond pad are disclosed. The methods include forming a dielectric material over a bond pad, forming an opening within the...
Semiconductor device with copper wirebond sites and methods of making same
Semiconductor devices with external wirebond sites that include copper and methods for fabricating such semiconductor devices are disclosed. One embodiment of a...
Method of treating a semiconductor device
A method of treating a semiconductor device wherein there is provided a semiconductor device, the semiconductor device being at least in part chemically bonded...
Forming air gaps in memory arrays and memory arrays with air gaps thus
Methods of forming air gaps in memory arrays and memory arrays with air gaps thus formed are disclosed. One such method may include forming an isolation region,...
Selective polymer growth on a semiconductor substrate
Method and systems provide growth of polymer structures at a high rate in a selective manner. In various embodiments, the method or system can expose the growth...
Microelectronic devices and methods for manufacturing microelectronic
Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. In one embodiment, a method includes constructing a...
Methods for forming an enriched metal oxide surface
Methods of forming a metal oxide surface that is enriched with metal oxide in its higher oxidation state are provided. A metal oxide surface that is enriched...
Systems and methods for exposing semiconductor workpieces to vapors for
through-hole cleaning and/or other...
Systems and methods for exposing semiconductor workpieces to vapors for through-hole cleaning and/or other processes are disclosed. A representative method...
Authenticated operations and event counters
Apparatus and methods protect a memory device from a security attack. A security attack may lead to an unusually high number of security events, such as power...
System and method for configuring drivers
Driver systems and methods are provided, such as those that include identifying a process corner of a driver; and configuring the driver based on the identified...
Decoding and optimized implementation of SECDED codes over GF(q)
A plurality of columns for a check matrix that implements a distance d linear error correcting code are populated by providing a set of vectors from which to...
Extended single-bit error correction and multiple-bit error detection
Some embodiments include apparatus and methods to prevent at least one of misidentifying and ignoring multiple-bit errors if the multiple-bit errors include a...
Methods and apparatus to facilitate determining or selecting a depth of error detection and/or error correction coverage, and detecting and/or correcting errors...
Symmetrically operating single-ended input buffer devices and methods
Embodiments are described including those pertaining to an input buffer having first and second complementary input terminals. One example buffer has a...
Sensing memory cells
The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to...
Reducing effects of erase disturb in a memory device
A method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the...
System having improved surface planarity for bit material deposition
The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is...
Reference voltage generation for single-ended communication channels
An improved reference voltage (Vref) generator useable, for example, in sensing data on single-ended channels is disclosed. The Vref generator can be placed on...
Wafer level packaging
Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of...
Capacitors including a rutile titanium dioxide material and semiconductor
devices incorporating same
Methods of forming a capacitor including forming at least one aperture in a support material, forming a titanium nitride material within the at least one...
Capacitors including at least two portions of a metal nitride material,
methods of forming such structures, and...
Metal-insulator-metal capacitors with a bottom electrode including at least two portions of a metal nitride material. At least one of the portions of the metal...
Memory arrays having substantially vertical, adjacent semiconductor
structures and the formation thereof
Memory arrays and methods of their formation are disclosed. One such memory array has memory-cell strings are formed adjacent to separated substantially...
Semiconductor devices including gate structures comprising colossal
Semiconductor devices include a transistor having a gate structure located close to a channel region that comprises a colossal magnetocapacitive material. The...
Method of reducing damage to an electron beam inspected semiconductor
substrate, and methods of inspecting a...
Methods for reducing electron beam induced damage on semiconductor substrates employ compositions such as small chain organic solvents and non-neutral pH...
Process of semiconductor fabrication with mask overlay on pitch multiplied
features and associated structures
Spacers are formed by pitch multiplication and a layer of negative photoresist is deposited on and over the spacers to form additional mask features. The...
Methods of forming patterns on substrates
A method of forming a pattern on a substrate includes forming spaced first features over a substrate. The spaced first features have opposing lateral sidewalls....
Methods using block co-polymer self-assembly for sub-lithographic
Block copolymers can be self-assembled and used in methods as described herein for sub-lithographic patterning, for example. The block copolymers can be diblock...
Method for statistical analysis of images for automatic white balance of
color channel gains for image sensors
A process for performing white balancing of an image is performed by subdividing an image into a plurality of subframes, and then analyzing each subframe to...
Spin torque transfer memory cell structures and methods
Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures include a tunneling barrier material...
An embodiment of a probe card comprising: a probe base plate including a ceramic base plate and a plurality of conductive paths; and a plurality of contacts...
Some embodiments include methods of forming capacitors. A first section of a capacitor may be formed to include a first storage node, a first dielectric...
Method and apparatus providing air-gap insulation between adjacent
conductors using nanoparticles
A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is...
Phase change memory cell structures and methods
Phase change memory cell structures and methods are described herein. A number of methods of forming a phase change memory cell structure include forming a...
Transparent conductor based pinned photodiode
A pinned photodiode with improved short wavelength light response. In exemplary embodiments of the invention, a gate oxide is formed over a doped, buried region...
Microlithography masks including image reversal assist features,
microlithography systems including such masks,...
Microlithography masks are disclosed, such as those that include one or more image reversal assist features disposed between at least two primary mask features....
Read strobe feedback in a memory system
A controller circuit is coupled to a memory device over a data/IO bus and a control bus. The controller circuit generates a read enable signal that is...
Method and apparatus for detecting communication errors on a bus
A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on...