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Patent # Description
US-8,587,354 Control of a variable delay line using line entry point to modify line power supply voltage
Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input...
US-8,587,340 Apparatuses including scalable drivers and methods
Apparatuses and methods are described that include a plurality of drivers corresponding to a single via. A number of drivers can be selected to operate...
US-8,587,109 Stacked microelectronic dies and methods for stacking microelectronic dies
An assembly of microelectronic devices and method for forming an assembly of microelectronic devices. In one embodiment, an assembly comprises a support member...
US-8,586,483 Semiconductor device structures and compositions for forming same
A method of removing a metal nitride material is disclosed. The method comprises forming a semiconductor device structure comprising an exposed metal material...
US-8,586,429 Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors,...
A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall...
US-8,585,915 Methods for fabricating sub-resolution alignment marks on semiconductor structures
A method of fabricating semiconductor structures comprising sub-resolution alignment marks is disclosed. The method comprises forming a dielectric material on a...
US-8,584,058 Methods for defining evaluation points for optical proximity correction and optical proximity correction...
Methods are disclosed for defining evaluation points for use in optical proximity correction of a rectangular target geometry. A method for defining evaluation...
US-8,583,987 Method and apparatus to perform concurrent read and write memory operations
Subject matter disclosed herein relates to read and write processes of a memory device. During a write process to a particular partition in a memory array, a...
US-8,583,870 Stacked memory devices, systems, and methods
Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more...
US-8,582,390 Wordline voltage transfer apparatus, systems, and methods
The apparatus and systems described herein may comprise a plurality of memory cells coupled to a local wordline, and a wordline drive circuit that includes a...
US-8,582,380 Systems, circuits, and methods for charge sharing
Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage...
US-8,582,377 Redundant memory array for replacing memory sections of main memory
Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory...
US-8,582,375 Methods for sensing memory elements in semiconductor devices
A memory device that, in certain embodiments, includes a plurality of memory elements connected to a bit-line and a delta-sigma modulator with a digital output...
US-8,582,373 Buffer die in stacks of memory dies and methods
Memory devices and methods of making and operating them are shown. Memory devices shown include stacked memory dies with one or more buffer dies included. In...
US-8,582,364 Fast programming memory device
In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one...
US-8,582,357 Reducing effects of program disturb in a memory device
The programming disturb effects in a semiconductor non-volatile memory device can be mitigated by biasing unselected memory cells with a negative voltage while...
US-8,582,356 Providing a ready-busy signal from a non-volatile memory device to a memory controller
A common standard may be used for both dynamic random access memories and non volatile memories, despite the fact that the non-volatile memory generally needs...
US-8,582,350 Capacitor-less memory cell, device, system and method of making same
A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of...
US-8,582,005 Method, apparatus and system providing adjustment of pixel defect map
A method, apparatus and system that allows for the identification of defective pixels, for example, defective pixel clusters, in an imager device. The method,...
US-8,581,651 Duty cycle based phase interpolators and methods for use
Duty cycle based phase interpolators, and methods for implementing duty cycle based phase interpolators are disclosed. One such phase interpolator includes a...
US-8,581,630 Signal driver circuit having adjustable output voltage for a high logic level output signal
A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured...
US-8,581,387 Through wire interconnect (TWI) having bonded connection and encapsulating polymer layer
A through wire interconnect for a semiconductor substrate includes a via extending through the semiconductor substrate from a first side to a second side...
US-8,581,352 Electronic devices including barium strontium titanium oxide films
Apparatus and methods of forming the apparatus include a dielectric layer containing barium strontium titanium oxide layer, an erbium-doped barium strontium...
US-8,581,224 Memory cells
Some embodiments include memory cells which contain, in order; a first electrode material, a first metal oxide material, a second metal oxide material, and a...
US-8,580,666 Methods of forming conductive contacts
Methods for forming memory devices and integrated circuitry, for example, DRAM (dynamic random access memory) circuitry, structures and devices resulting from...
US-8,580,645 Memory devices and methods of forming memory devices
Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes...
US-8,580,593 Epitaxial formation structures and associated methods of manufacturing solid state lighting devices
Epitaxial formation structures and associated methods of manufacturing solid state lighting ("SSL") devices with target thermal expansion characteristics are...
US-8,580,158 Methods of removing silicon dioxide
Some embodiments include methods of removing silicon dioxide in which the silicon dioxide is exposed to a mixture that includes activated hydrogen and at least...
US-8,578,591 Method for manufacturing a stacked device conductive path connectivity
Various embodiments include apparatus and methods having circuitry to test continuity of conductive paths coupled to dice arranged in a stack. In at least one...
US-8,578,331 Command line output redirection
In one embodiment the invention provides a method to provide command line utility output to an application without the need of temporary files. The method...
US-8,578,244 Programming error correction code into a solid state memory device with varying bits per cell
Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to...
US-8,578,208 Determining location of error detection data
Methods, devices, and systems for determining location of error detection data are described. One method for operating a memory unit having a bad group of...
US-8,578,115 Temporary mirroring, logical segregation, and redundant programming or addressing for solid state drive operation
The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes mirroring programming operations such that...
US-8,578,095 Hierarchical memory architecture using a concentrator device
A hierarchical memory storage using a concentrator device that is located between a processor and memory devices. The concentrator device includes a page...
US-8,578,070 Host controller
The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes...
US-8,576,646 Control voltage tracking circuits, methods for recording a control voltage for a clock synchronization circuit...
Memories, clock synchronization circuits, clock synchronization controller circuits, and methods for setting a voltage controlled delay of a clock...
US-8,576,632 Methods, devices, and systems for dealing with threshold voltage change in memory devices
The present disclosure includes methods, devices, and systems for dealing with threshold voltage change in memory devices. A number of embodiments include an...
US-8,576,631 Techniques for sensing a semiconductor memory device
Techniques for sensing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the technique(s) may be realized as a semiconductor...
US-8,576,627 Memory array with inverted data-lines pairs
At least one data-line pair has a first data line aligned with a first column of memory cells and a second data line aligned with a second column of memory...
US-8,575,958 Programmable on-chip logic analyzer apparatus, systems, and methods
Apparatus, systems, and methods disclosed herein may cause an event trigger state machine associated with a programmable on-chip logic analyzer (POCLA) to...
US-8,575,716 Integrated circuit devices and methods of forming memory array and peripheral circuitry isolation
A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of...
US-8,575,040 Low temperature process for polysilazane oxidation/densification
Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are...
US-8,575,032 Methods of forming a pattern on a substrate
A method of forming a pattern on a substrate includes forming a repeating pattern of four first lines elevationally over an underlying substrate. A repeating...
US-8,574,954 Phase change memory structures and methods
Methods, devices, and systems associated with phase change material memory are described herein. In one or more embodiments, a method of forming a phase change...
US-8,572,466 Apparatuses, systems, devices, and methods of replacing at least partially non-functional portions of memory
Subject matter disclosed herein relates to determining that a portion of a memory is at least partially non-functional, replacing the portion of at least...
US-8,572,361 Configuration of a multilevel flash memory device
A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the...
US-8,572,358 Meta predictor restoration upon detecting misprediction
Methods and apparatus for restoring a meta predictor system upon detecting a branch or binary misprediction, are disclosed. An example apparatus may include a...
US-8,572,333 Non-volatile memory with extended operating temperature range
A method and apparatus are described for measuring a temperature within a non-volatile memory and refreshing at least a portion of the non-volatile memory when...
US-8,572,292 Command interface systems and methods
Apparatus, systems, and methods are disclosed that operate within a memory to execute internal commands, to suspend the execution of commands during a transfer...
US-8,570,860 Redundant signal transmission
Signal transmission apparatus, systems, and methods are disclosed. In various embodiments, a signal transmission system includes a transmission network having...
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