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Patent # Description
US-8,575,958 Programmable on-chip logic analyzer apparatus, systems, and methods
Apparatus, systems, and methods disclosed herein may cause an event trigger state machine associated with a programmable on-chip logic analyzer (POCLA) to...
US-8,575,716 Integrated circuit devices and methods of forming memory array and peripheral circuitry isolation
A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of...
US-8,575,040 Low temperature process for polysilazane oxidation/densification
Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are...
US-8,575,032 Methods of forming a pattern on a substrate
A method of forming a pattern on a substrate includes forming a repeating pattern of four first lines elevationally over an underlying substrate. A repeating...
US-8,574,954 Phase change memory structures and methods
Methods, devices, and systems associated with phase change material memory are described herein. In one or more embodiments, a method of forming a phase change...
US-8,572,466 Apparatuses, systems, devices, and methods of replacing at least partially non-functional portions of memory
Subject matter disclosed herein relates to determining that a portion of a memory is at least partially non-functional, replacing the portion of at least...
US-8,572,361 Configuration of a multilevel flash memory device
A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the...
US-8,572,358 Meta predictor restoration upon detecting misprediction
Methods and apparatus for restoring a meta predictor system upon detecting a branch or binary misprediction, are disclosed. An example apparatus may include a...
US-8,572,333 Non-volatile memory with extended operating temperature range
A method and apparatus are described for measuring a temperature within a non-volatile memory and refreshing at least a portion of the non-volatile memory when...
US-8,572,292 Command interface systems and methods
Apparatus, systems, and methods are disclosed that operate within a memory to execute internal commands, to suspend the execution of commands during a transfer...
US-8,570,860 Redundant signal transmission
Signal transmission apparatus, systems, and methods are disclosed. In various embodiments, a signal transmission system includes a transmission network having...
US-8,570,826 Memory device having data paths facilitating array/contact consolidation and/or swapping
Apparatus and methods are disclosed, such as those involving array/port consolidation and/or swapping. One such apparatus includes a plurality of port pads...
US-8,570,807 NAND architecture memory with voltage sensing
A NAND architecture non-volatile memory voltage sensing data read/verify process and sense amplifier has been described that senses data in floating gate or...
US-8,570,798 Electronic devices formed of two or more substrates connected together, electronic systems comprising...
Electronic devices comprise a first substrate and a second substrate. The first substrate comprises circuitry including a plurality of conductive traces at...
US-8,570,613 Lithographic printing system with placement corrections
The technology disclosed relates to methods and devices that compensate for displacements in a pattern or deformations of a workpiece. In particular, this...
US-8,570,535 Pattern generators, calibration systems and methods for patterning workpieces
A pattern generator includes: a writing tool and a calibration system. The writing tool is configured to generate a pattern on a workpiece arranged on a stage....
US-8,570,084 Circuits and methods for clock signal duty-cycle correction
Duty-cycle correction circuits, clock distribution networks, and methods for correcting duty-cycle distortion are disclosed, including methods and apparatus for...
US-8,570,081 Fast measurement initialization for memory
Systems and methods for synchronization of clock signals are disclosed. In a feedback system such as a delay-lock loop circuit, delays to be applied can be...
US-8,570,063 Methods and apparatuses including an adjustable termination impedance ratio
Methods of adjusting a centerline voltage of a data signal are described, along with apparatuses to adjust the centerline voltage. In one such method, portions...
US-8,569,893 Self-aligned, integrated circuit contact
This document discusses, among other things, example systems including integrated circuit contacts configured to reduce the likelihood of shorting to unrelated...
US-8,569,891 Forming array contacts in semiconductor memories
Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks...
US-8,569,863 Voltage-controlled semiconductor inductor and method
A voltage-controlled semiconductor inductor and method is provided. According to various embodiments, the voltage-controlled inductor includes a conductor...
US-8,569,831 Integrated circuit arrays and semiconductor constructions
Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting...
US-8,569,734 Forming resistive random access memories together with fuse arrays
A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same...
US-8,569,681 Ambient infrared detection in solid state sensors
A solid state imaging device includes an array of active pixels and an infrared cut filter formed over the sensor. Optionally, a slot in the infrared cut filter...
US-8,569,167 Methods for forming a semiconductor structure
Methods of forming a Ni material on a bond pad are disclosed. The methods include forming a dielectric material over a bond pad, forming an opening within the...
US-8,569,161 Semiconductor device with copper wirebond sites and methods of making same
Semiconductor devices with external wirebond sites that include copper and methods for fabricating such semiconductor devices are disclosed. One embodiment of a...
US-8,569,149 Method of treating a semiconductor device
A method of treating a semiconductor device wherein there is provided a semiconductor device, the semiconductor device being at least in part chemically bonded...
US-8,569,130 Forming air gaps in memory arrays and memory arrays with air gaps thus formed
Methods of forming air gaps in memory arrays and memory arrays with air gaps thus formed are disclosed. One such method may include forming an isolation region,...
US-8,569,103 Selective polymer growth on a semiconductor substrate
Method and systems provide growth of polymer structures at a high rate in a selective manner. In various embodiments, the method or system can expose the growth...
US-8,569,093 Microelectronic devices and methods for manufacturing microelectronic devices
Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. In one embodiment, a method includes constructing a...
US-8,568,900 Methods for forming an enriched metal oxide surface
Methods of forming a metal oxide surface that is enriched with metal oxide in its higher oxidation state are provided. A metal oxide surface that is enriched...
US-8,568,535 Systems and methods for exposing semiconductor workpieces to vapors for through-hole cleaning and/or other...
Systems and methods for exposing semiconductor workpieces to vapors for through-hole cleaning and/or other processes are disclosed. A representative method...
US-8,566,940 Authenticated operations and event counters
Apparatus and methods protect a memory device from a security attack. A security attack may lead to an unusually high number of security events, such as power...
US-8,566,846 System and method for configuring drivers
Driver systems and methods are provided, such as those that include identifying a process corner of a driver; and configuring the driver based on the identified...
US-8,566,684 Decoding and optimized implementation of SECDED codes over GF(q)
A plurality of columns for a check matrix that implements a distance d linear error correcting code are populated by providing a set of vectors from which to...
US-8,566,677 Extended single-bit error correction and multiple-bit error detection
Some embodiments include apparatus and methods to prevent at least one of misidentifying and ignoring multiple-bit errors if the multiple-bit errors include a...
US-8,566,675 Data handling
Methods and apparatus to facilitate determining or selecting a depth of error detection and/or error correction coverage, and detecting and/or correcting errors...
US-8,565,037 Symmetrically operating single-ended input buffer devices and methods
Embodiments are described including those pertaining to an input buffer having first and second complementary input terminals. One example buffer has a...
US-8,565,024 Sensing memory cells
The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to...
US-8,565,018 Reducing effects of erase disturb in a memory device
A method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the...
US-8,565,016 System having improved surface planarity for bit material deposition
The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is...
US-8,564,274 Reference voltage generation for single-ended communication channels
An improved reference voltage (Vref) generator useable, for example, in sensing data on single-ended channels is disclosed. The Vref generator can be placed on...
US-8,564,106 Wafer level packaging
Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of...
US-8,564,095 Capacitors including a rutile titanium dioxide material and semiconductor devices incorporating same
Methods of forming a capacitor including forming at least one aperture in a support material, forming a titanium nitride material within the at least one...
US-8,564,094 Capacitors including at least two portions of a metal nitride material, methods of forming such structures, and...
Metal-insulator-metal capacitors with a bottom electrode including at least two portions of a metal nitride material. At least one of the portions of the metal...
US-8,564,045 Memory arrays having substantially vertical, adjacent semiconductor structures and the formation thereof
Memory arrays and methods of their formation are disclosed. One such memory array has memory-cell strings are formed adjacent to separated substantially...
US-8,564,039 Semiconductor devices including gate structures comprising colossal magnetocapacitive materials
Semiconductor devices include a transistor having a gate structure located close to a channel region that comprises a colossal magnetocapacitive material. The...
US-8,563,435 Method of reducing damage to an electron beam inspected semiconductor substrate, and methods of inspecting a...
Methods for reducing electron beam induced damage on semiconductor substrates employ compositions such as small chain organic solvents and non-neutral pH...
US-8,563,229 Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures
Spacers are formed by pitch multiplication and a layer of negative photoresist is deposited on and over the spacers to form additional mask features. The...
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