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Storage capacity status
In one embodiment of the present invention, a memory device is disclosed to include memory organized into blocks, each block having a status associated...
Secure memory device erase
Subject matter disclosed herein relates to an erasable memory device, and more particularly to a securely erasable flash memory device.
Replacing defective columns of memory cells in response to external
Controllers and memory devices are provided. In an embodiment, a controller is configured to address a non-defective column of memory cells of a memory device...
Local sensing in a memory device
Methods for sensing, memory devices, and memory systems are disclosed. In one such memory device, a local sense circuit provides sensing of an upper group of...
Programming methods for a memory device
Methods for programming, memory devices, and memory systems are disclosed. In one such method for programming, a target memory cell is partially programmed to a...
NAND architecture memory with voltage sensing
A NAND architecture non-volatile memory voltage sensing data read/verify process and sense amplifier has been described that senses data in floating gate or...
Semiconductor memory cell and array using punch-through to program and
An integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including a punch-through mode transistor, wherein the...
Vertically stacked fin transistors and methods of fabricating and
operating the same
A semiconductor device is disclosed having vertically stacked (also referred to as vertically offset) transistors in a semiconductor fin. The semiconductor fin...
Methods for fabricating and filling conductive vias and conductive vias so
Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with protective...
Semiconductor structures including square cuts in single crystal silicon
and method of forming same
A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a...
Devices and methods to improve carrier mobility
Electronic apparatus and methods of forming the electronic apparatus include a silicon oxynitride layer on a semiconductor device for use in a variety of...
Erasable non-volatile memory device using hole trapping in high-K
A non-volatile memory is described having memory cells with a gate dielectric. The gate dielectric is a multilayer charge trapping dielectric between a control...
Use of dilute steam ambient for improvement of flash devices
A flash memory integrated circuit and a method for fabricating the same. A gate stack includes an initial oxide layer directly in contact with a silicon layer,...
Multilayer antireflection coatings, structures and devices including the
same and methods of making the same
Multi-layer antireflection coatings, devices including multi-layer antireflection coatings and methods of forming the same are disclosed. A block copolymer is...
Among various methods, devices, and apparatuses, a number of methods are provided for forming a gap between circuitry. One such method includes depositing a...
Implantation processes for straining transistor channels of semiconductor
device structures and semiconductor...
The present invention includes methods for stressing transistor channels of semiconductor device structures. Such methods include the formation of so-called...
Method of fabricating a finFET having cross-hair cells
Systems and methods are disclosed for manufacturing grounded gate cross-hair cells and standard cross-hair cells of fin field-effect transistors (finFETs). In...
Semiconductor device including a temperature sensor circuit
A semiconductor device including a temperature sensor includes a pull up circuit, a pull down circuit, a first additional current path, and a second additional...
Microelectronic devices with improved heat dissipation and methods for
cooling microelectronic devices
Microelectronic devices with improved heat dissipation, methods of making microelectronic devices, and methods of cooling microelectronic devices are disclosed...
Macro and command execution from memory array
Methods and apparatus for executing internal operations of memory devices utilizing instructions stored in the memory array of the memory device are disclosed....
Programming error correction code into a solid state memory device with
varying bits per cell
Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to...
Temporary mirroring, logical segregation, and redundant programming or
addressing for solid state drive operation
The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes mirroring programming operations such that...
Memory device and method having on-board address protection system for
facilitating interface with multiple...
A memory device includes an address protection system that facilitates the ability of the memory device to interface with a plurality of processors operating in...
Apparatus and method for data bypass for a bi-directional data bus in a
hub-based memory sub-system
A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and...
Asymmetric chip-to-chip interconnect
The use of asymmetric signalling over channels is disclosed. Pursuant to one or more embodiments of the invention, the channels in the parallel bus operate as...
Data transfer management
Methods, controllers, and systems for managing data transfer, such as those in solid state drives (SSDs), are described. In some embodiments, the data transfer...
Systems configured to identify an operating mode
Systems having a host computer system, a memory device coupled to the host computer system, and identification circuitry. The identification circuitry is...
Selective edge phase mixing
Electronic apparatus, systems, and methods to implement selective edge phase mixing are disclosed. A selective edge phase mixing system includes a processor and...
Multiple device apparatus, systems, and methods
Apparatus, systems, and methods are disclosed that operate to generate a clock signal in a die in a stack and to receive the clock signal in another die in the...
Power source and power source control circuit
Power sources, backup power circuits, power source control circuits, data storage devices, and methods relating to controlling application of power to a node...
Sense amplifier having loop gain control
Memories, sense amplifiers, and methods for amplifying a current input are disclosed, including a sense amplifier including a bias circuit configured to provide...
Memory repair systems and methods for a memory having redundant memory
Memories, memory repair logic, and methods for repairing a memory having redundant memory are disclosed. One such memory includes programmable elements...
Memory cell sensing device equipped with a ramp voltage generator using a
digital-to-analog converter (DAC) and...
The present disclosure includes methods, devices, and systems for sensing memory cells. One or more embodiments include providing an output of a first counter...
Expanded programming window for non-volatile multilevel memory cells
Embodiments of the present disclosure provide methods, devices, modules, and systems for utilizing an expanded programming window for non-volatile multilevel...
Memory with correlated resistance
Methods, systems, and devices include a system for sequentially writing to a data locations coupled to one another in series. The system includes a plurality of...
Providing a ready-busy signal from a non-volatile memory device to a
A common standard may be used for both dynamic random access memories and non-volatile memories, despite the fact that the non-volatile memory generally needs...
Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines...
Multi-mode memory device and method having stacked memory dice, a logic
die and a command processing circuit...
Memory device systems, systems and methods are disclosed, such as those involving a plurality of stacked memory device dice and a logic die connected to each...
Method, apparatus and system providing imager vertical binning and scaling
using column parallel sigma-delta...
A method, apparatus and system are disclosed for digitizing a plurality of analog pixel signals of a pixel array in a manner which produces a digital signal...
Analog delay lines and adaptive biasing
Examples of analog delay lines and analog delay systems, such as DLLs incorporating analog delay lines are described, as are circuits and methods for adaptive...
Circuits and methods for clock signal duty-cycle correction
Duty-cycle correction circuits, clock distribution networks, and methods for correcting duty-cycle distortion are disclosed, including methods and apparatus for...
Switching circuits, latches and methods
Switching circuits, latches and methods are provided, such as those that may respond to an input signal that transitions from a first binary level to a second...
Stackable semiconductor assemblies and methods of manufacturing such
Stacked semiconductor devices and assemblies including attached lead frames are disclosed herein. One embodiment of a method of manufacturing a semiconductor...
Some embodiments include semiconductor processing methods in which a copper barrier is formed to be laterally offset from a copper component, and in which...
Semiconductor device packages including a semiconductor device and a
A method for fabricating a chip-scale board-on-chip substrate, or redistribution element, includes forming conductive planes on opposite sides of a substrate. A...
Semiconductor devices including a layer of polycrystalline silicon having
a smooth morphology
A method for controlling the morphology of deposited silicon on a layer of silicon dioxide and semiconductor devices incorporating such deposited silicon are...
Devices with nanocrystals and methods of formation
Devices can be fabricated using a method of growing nanoscale structures on a semiconductor substrate. According to various embodiments, nucleation sites are...
Semiconductor constructions for transistor gates and NAND cell units
Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at...
Fortification of charge-storing material in high-K dielectric environments
and resulting apparatuses
Memories, systems, and methods for forming memory cells are disclosed. One such memory cell includes a charge storage node that includes nanodots over a tunnel...
Zirconium-doped tantalum oxide films
Dielectric layers containing a zirconium-doped tantalum oxide layer, where the zirconium-doped tantalum oxide layer is formed of one or more monolayers of...