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Patent # Description
US-8,569,161 Semiconductor device with copper wirebond sites and methods of making same
Semiconductor devices with external wirebond sites that include copper and methods for fabricating such semiconductor devices are disclosed. One embodiment of a...
US-8,569,149 Method of treating a semiconductor device
A method of treating a semiconductor device wherein there is provided a semiconductor device, the semiconductor device being at least in part chemically bonded...
US-8,569,130 Forming air gaps in memory arrays and memory arrays with air gaps thus formed
Methods of forming air gaps in memory arrays and memory arrays with air gaps thus formed are disclosed. One such method may include forming an isolation region,...
US-8,569,103 Selective polymer growth on a semiconductor substrate
Method and systems provide growth of polymer structures at a high rate in a selective manner. In various embodiments, the method or system can expose the growth...
US-8,569,093 Microelectronic devices and methods for manufacturing microelectronic devices
Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. In one embodiment, a method includes constructing a...
US-8,568,900 Methods for forming an enriched metal oxide surface
Methods of forming a metal oxide surface that is enriched with metal oxide in its higher oxidation state are provided. A metal oxide surface that is enriched...
US-8,568,535 Systems and methods for exposing semiconductor workpieces to vapors for through-hole cleaning and/or other...
Systems and methods for exposing semiconductor workpieces to vapors for through-hole cleaning and/or other processes are disclosed. A representative method...
US-8,566,940 Authenticated operations and event counters
Apparatus and methods protect a memory device from a security attack. A security attack may lead to an unusually high number of security events, such as power...
US-8,566,846 System and method for configuring drivers
Driver systems and methods are provided, such as those that include identifying a process corner of a driver; and configuring the driver based on the identified...
US-8,566,684 Decoding and optimized implementation of SECDED codes over GF(q)
A plurality of columns for a check matrix that implements a distance d linear error correcting code are populated by providing a set of vectors from which to...
US-8,566,677 Extended single-bit error correction and multiple-bit error detection
Some embodiments include apparatus and methods to prevent at least one of misidentifying and ignoring multiple-bit errors if the multiple-bit errors include a...
US-8,566,675 Data handling
Methods and apparatus to facilitate determining or selecting a depth of error detection and/or error correction coverage, and detecting and/or correcting errors...
US-8,565,037 Symmetrically operating single-ended input buffer devices and methods
Embodiments are described including those pertaining to an input buffer having first and second complementary input terminals. One example buffer has a...
US-8,565,024 Sensing memory cells
The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to...
US-8,565,018 Reducing effects of erase disturb in a memory device
A method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the...
US-8,565,016 System having improved surface planarity for bit material deposition
The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is...
US-8,564,274 Reference voltage generation for single-ended communication channels
An improved reference voltage (Vref) generator useable, for example, in sensing data on single-ended channels is disclosed. The Vref generator can be placed on...
US-8,564,106 Wafer level packaging
Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of...
US-8,564,095 Capacitors including a rutile titanium dioxide material and semiconductor devices incorporating same
Methods of forming a capacitor including forming at least one aperture in a support material, forming a titanium nitride material within the at least one...
US-8,564,094 Capacitors including at least two portions of a metal nitride material, methods of forming such structures, and...
Metal-insulator-metal capacitors with a bottom electrode including at least two portions of a metal nitride material. At least one of the portions of the metal...
US-8,564,045 Memory arrays having substantially vertical, adjacent semiconductor structures and the formation thereof
Memory arrays and methods of their formation are disclosed. One such memory array has memory-cell strings are formed adjacent to separated substantially...
US-8,564,039 Semiconductor devices including gate structures comprising colossal magnetocapacitive materials
Semiconductor devices include a transistor having a gate structure located close to a channel region that comprises a colossal magnetocapacitive material. The...
US-8,563,435 Method of reducing damage to an electron beam inspected semiconductor substrate, and methods of inspecting a...
Methods for reducing electron beam induced damage on semiconductor substrates employ compositions such as small chain organic solvents and non-neutral pH...
US-8,563,229 Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures
Spacers are formed by pitch multiplication and a layer of negative photoresist is deposited on and over the spacers to form additional mask features. The...
US-8,563,228 Methods of forming patterns on substrates
A method of forming a pattern on a substrate includes forming spaced first features over a substrate. The spaced first features have opposing lateral sidewalls....
US-8,562,844 Methods using block co-polymer self-assembly for sub-lithographic patterning
Block copolymers can be self-assembled and used in methods as described herein for sub-lithographic patterning, for example. The block copolymers can be diblock...
US-8,300,930 Method for statistical analysis of images for automatic white balance of color channel gains for image sensors
A process for performing white balancing of an image is performed by subdividing an image into a plurality of subframes, and then analyzing each subframe to...
US-8,300,454 Spin torque transfer memory cell structures and methods
Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures include a tunneling barrier material...
US-8,299,812 Probe card
An embodiment of a probe card comprising: a probe base plate including a ceramic base plate and a plurality of conductive paths; and a plurality of contacts...
US-8,299,574 Semiconductor constructions
Some embodiments include methods of forming capacitors. A first section of a capacitor may be formed to include a first storage node, a first dielectric...
US-8,298,964 Method and apparatus providing air-gap insulation between adjacent conductors using nanoparticles
A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is...
US-8,298,938 Phase change memory cell structures and methods
Phase change memory cell structures and methods are described herein. A number of methods of forming a phase change memory cell structure include forming a...
US-8,298,846 Transparent conductor based pinned photodiode
A pinned photodiode with improved short wavelength light response. In exemplary embodiments of the invention, a gate oxide is formed over a doped, buried region...
US-8,298,729 Microlithography masks including image reversal assist features, microlithography systems including such masks,...
Microlithography masks are disclosed, such as those that include one or more image reversal assist features disposed between at least two primary mask features....
US-8,296,692 Read strobe feedback in a memory system
A controller circuit is coupled to a memory device over a data/IO bus and a control bus. The controller circuit generates a read enable signal that is...
US-8,296,639 Method and apparatus for detecting communication errors on a bus
A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on...
US-8,296,545 Storage capacity status
In one embodiment of the present invention, a memory device is disclosed to include memory organized into blocks, each block having a status associated...
US-8,296,508 Secure memory device erase
Subject matter disclosed herein relates to an erasable memory device, and more particularly to a securely erasable flash memory device.
US-8,295,109 Replacing defective columns of memory cells in response to external addresses
Controllers and memory devices are provided. In an embodiment, a controller is configured to address a non-defective column of memory cells of a memory device...
US-8,295,098 Local sensing in a memory device
Methods for sensing, memory devices, and memory systems are disclosed. In one such memory device, a local sense circuit provides sensing of an upper group of...
US-8,295,095 Programming methods for a memory device
Methods for programming, memory devices, and memory systems are disclosed. In one such method for programming, a target memory cell is partially programmed to a...
US-8,295,088 NAND architecture memory with voltage sensing
A NAND architecture non-volatile memory voltage sensing data read/verify process and sense amplifier has been described that senses data in floating gate or...
US-8,295,078 Semiconductor memory cell and array using punch-through to program and read same
An integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including a punch-through mode transistor, wherein the...
US-8,294,511 Vertically stacked fin transistors and methods of fabricating and operating the same
A semiconductor device is disclosed having vertically stacked (also referred to as vertically offset) transistors in a semiconductor fin. The semiconductor fin...
US-8,294,273 Methods for fabricating and filling conductive vias and conductive vias so formed
Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with protective...
US-8,294,246 Semiconductor structures including square cuts in single crystal silicon and method of forming same
A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a...
US-8,294,224 Devices and methods to improve carrier mobility
Electronic apparatus and methods of forming the electronic apparatus include a silicon oxynitride layer on a semiconductor device for use in a variety of...
US-8,294,196 Erasable non-volatile memory device using hole trapping in high-K dielectrics
A non-volatile memory is described having memory cells with a gate dielectric. The gate dielectric is a multilayer charge trapping dielectric between a control...
US-8,294,192 Use of dilute steam ambient for improvement of flash devices
A flash memory integrated circuit and a method for fabricating the same. A gate stack includes an initial oxide layer directly in contact with a silicon layer,...
US-8,294,139 Multilayer antireflection coatings, structures and devices including the same and methods of making the same
Multi-layer antireflection coatings, devices including multi-layer antireflection coatings and methods of forming the same are disclosed. A block copolymer is...
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