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Patent # Description
US-8,274,849 Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of...
An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each...
US-8,274,835 Mitigation of runaway programming of a memory device
Methods for mitigating runaway programming in a memory device, methods for program verifying a memory device, a memory device, and a memory system are provided....
US-8,274,833 Mitigation of data corruption from back pattern and program disturb in a non-volatile memory device
A write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program disturb in memory cells. Original data to...
US-8,274,832 Dynamic polarization for reducing stress induced leakage current
Subject matter disclosed herein relates to non-volatile flash memory, and more particularly to a method of reducing stress induced leakage current.
US-8,274,823 Methods and apparatus utilizing expected coupling effect in the programming of memory cells
Methods and memory devices configured to utilize predicted coupling effects of neighboring memory cells in the programming of target memory cells can be...
US-8,274,777 High aspect ratio openings
A capacitor forming method includes forming an electrically conductive support material over a substrate, with the support material containing at least 25 at %...
US-8,274,221 Plasma-generating structures, display devices, and methods of forming plasma-generating structures
Some embodiments include methods of forming plasma-generating microstructures. Aluminum may be anodized to form an aluminum oxide body having a plurality of...
US-8,274,163 Method and apparatus providing integrated circuit having redistribution layer with recessed connectors
A method of making a semiconductor die includes forming a trench around a conductive stud extending from the first side to a second side of a substrate to...
US-8,274,110 Vertically-oriented semiconductor selection device providing high drive current in cross-point array memory
A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first...
US-8,274,106 DRAM layout with vertical FETs and method of formation
DRAM cell arrays having a cell area of about 4F.sup.2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The...
US-8,274,081 Semiconductor constructions
Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection...
US-8,273,647 Methods of forming patterns, and methods of forming integrated circuits
Some embodiments include methods of forming patterns in substrates by utilizing block copolymer assemblies as patterning materials. A block copolymer assembly...
US-8,273,643 Diodes, and methods of forming diodes
Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is...
US-8,273,635 Semiconductor fabrication method and system
A method for manufacturing a semiconductor device is disclosed. In one embodiment, the method includes attaching a carrier to a substrate including a via to...
US-8,273,634 Methods of fabricating substrates
A method of fabricating a substrate includes forming first and second spaced features over a substrate. The first spaced features have elevationally outermost...
US-8,273,619 Methods of implanting dopant into channel regions
The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger...
US-8,273,589 Light emitting diodes and methods for manufacturing light emitting diodes
Light emitting diodes and methods for manufacturing light emitting diodes are disclosed herein. In one embodiment, a method for manufacturing a light emitting...
US-8,273,261 Methods of forming semiconductor constructions
The invention includes methods in which silicon is removed from titanium-containing container structures with an etching composition having a...
US-8,273,177 Titanium-doped indium oxide films
An apparatus and methods of forming the apparatus include a film of transparent conductive titanium-doped indium oxide for use in a variety of configurations...
US-8,273,165 Compacted air flow rapid fluid evaporation system
A total water desalination system is disclosed that includes a centrifugal separator, a feed-water device controlled by a relative humidity sensor, an air pump,...
US-8,271,823 DLL phase detection using advanced phase equalization
A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL)....
US-8,271,697 State change in systems having devices coupled in a chained configuration
The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of...
US-8,271,239 Generation and manipulation of realistic signals for circuit and system verification
Methods for generating realistic waveforms with controllable voltage noise and timing jitter in a computer-based simulation environment and the simulation of a...
US-8,270,224 Voltage discharge circuits and methods
Memory devices, memory systems, discharge circuits, and methods for discharging a capacitance are disclosed. In one such memory device, a discharge circuit is...
US-8,270,205 Variable resistance memory device with an interfacial adhesion heating layer, systems using the same and...
A variable resistance memory element and method of forming the same. The memory element includes a first electrode, a resistivity interfacial layer having a...
US-8,269,540 Circuitry and methods for improving differential signals that cross power domains
Disclosed herein are circuitry and methods for improving differential signals that cross power domains. In an example embodiment, the power supply domain...
US-8,269,328 Stacked die package for peripheral and center device pad layout device
An assembly method is disclosed that includes providing a substrate, securing a first semiconductor device on a first surface thereof, and superimposing at...
US-8,269,326 Semiconductor device assemblies
An interposer includes a substrate, a conductive structure configured to contact the back side of a semiconductor device and contact pads. The interposer may...
US-8,269,306 Isolation regions
A dielectric liner is formed in first and second trenches respectively in first and second portions of a substrate. A layer of material is formed overlying the...
US-8,269,254 Silicon on germanium
The use of atomic layer deposition (ALD) to form a semiconductor structure of a silicon film on a germanium substrate is disclosed. An example embodiment...
US-8,268,732 Methods of utilizing block copolymers to form patterns
Some embodiments include methods of forming patterns utilizing copolymer. A copolymer composition is formed across a substrate. The composition includes...
US-8,268,730 Methods of masking semiconductor device structures
A method for fabricating semiconductor device structures includes forming a non-conformal mask over a surface of a substrate. Non-conformal mask material with a...
US-8,268,723 Methods for forming semiconductor device structures
The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a...
US-8,268,715 Multi-component integrated circuit contacts
An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a...
US-8,268,695 Methods of making capacitors
Some embodiments include methods of making stud-type capacitors utilizing carbon-containing support material. Openings may be formed through the ...
US-8,268,692 Non-volatile memory cell devices and methods
A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming an intergate dielectric layer over the nanodots,...
US-8,268,543 Methods of forming patterns on substrates
A method of forming a pattern on a substrate includes forming spaced first features over a substrate. The spaced first features have opposing lateral sidewalls....
US-8,266,818 Pixel optimization for color
A macro pixel is provided. The macro pixel includes at least two color pixel elements. Each color pixel element includes a photoreceptor that in response to...
US-RE43,665 Reading non-volatile multilevel memory cells
Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile multilevel memory cells. One method includes...
US-8,266,558 Methods for forming arrays of small, closely spaced features
Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can...
US-8,266,501 Stripe based memory operation
The present disclosure includes methods and devices for stripe-based memory operation. One method embodiment includes writing data in a first stripe across a...
US-8,266,063 Software distribution method and apparatus
The present invention provides for a method and apparatus for distributing digital information, such as software applications, to application users. By...
US-8,264,886 Delayed activation of selected wordlines in memory
Apparatus, systems, and methods may operate to receive an external read command at a control circuit coupled to a memory array. Individual wordline activation...
US-8,264,885 Method for memory cell erasure with a programming monitor of reference cells
Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase...
US-8,264,882 Charge loss compensation during programming of a memory device
In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is...
US-8,264,879 Sensing memory cells
Methods, devices, modules, and systems for operating memory cells are taught. A method for operating memory cells includes programming at least one of the...
US-8,264,041 Semiconductor device with electrically floating body
A semiconductor device along with circuits including the same and methods of operating the same are described. The device includes an electrically floating body...
US-8,263,988 Solid state lighting devices with reduced crystal lattice dislocations and associated methods of manufacturing
Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a substrate...
US-8,263,962 Inverted variable resistance memory cell and method of making the same
An inverted variable resistance memory cell and a method of fabricating the same. The memory cell is fabricated by forming an opening in an insulating layer...
US-8,263,958 Layered resistance variable memory device and method of fabrication
The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics....
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