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Patent # Description
US-8,288,817 Semiconductor constructions for transistor gates and NAND cell units
Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at...
US-8,288,811 Fortification of charge-storing material in high-K dielectric environments and resulting apparatuses
Memories, systems, and methods for forming memory cells are disclosed. One such memory cell includes a charge storage node that includes nanodots over a tunnel...
US-8,288,809 Zirconium-doped tantalum oxide films
Dielectric layers containing a zirconium-doped tantalum oxide layer, where the zirconium-doped tantalum oxide layer is formed of one or more monolayers of...
US-8,288,795 Thyristor based memory cells, devices and systems including the same and methods for forming the same
Semiconductor devices including a plurality of thyristor-based memory cells, each having a cell size of 4F.sup.2, and methods for forming the same are provided....
US-8,288,264 Scalable multi-function and multi-level nano-crystal non-volatile memory device
A multi-functional and multi-level memory cell comprises a tunnel layer formed over a substrate. In one embodiment, the tunnel layer comprises two layers such...
US-8,288,213 Methods of forming memory arrays
Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces....
US-8,288,083 Methods of forming patterned masks
Some embodiments include methods in which spaced-apart first features are formed from a first material having a reflow temperature. Second material is formed...
US-8,286,883 System and method for updating read-only memory in smart card memory modules
A storage device contains a smart-card device and a memory device, both connected to a controller. The storage device may be used in the same manner as a...
US-8,286,066 Non-volatile memory with bi-directional error correction protection
Embodiments of the present disclosure provide methods and apparatuses related to NVM devices with bi-directional error correction protection. In some...
US-8,285,976 Method and apparatus for predicting branches using a meta predictor
A branch predicting apparatus is disclosed that reduces branch mispredictions in a processor. The branch prediction apparatus includes a base misprediction...
US-8,284,623 Electronic device comprising non volatile memory cells and corresponding programming method
A device with non volatile memory cells, with optimized programming, of the type comprising a sector of matrix memory cells organized in rows and columns, with...
US-8,284,617 Circuits, devices, systems, and methods of operation for capturing data signals
Embodiments of the invention describe driving data onto a bus. The embodiments include a data driver circuit having a data capture circuit coupled to the bus....
US-8,284,616 Trench memory structure operation
Memory cells utilizing dielectric charge carrier trapping sites formed in trenches provide for non-volatile storage of data. The memory cells of the various...
US-8,284,613 Semiconductor memory device having bit line pre-charge unit separated from data register
A semiconductor memory device is described that can, in certain embodiments, reduce a delay in access time and/or an area of a memory cell array. In one or more...
US-8,283,961 Delay line circuit
Delay circuitry is described that includes clock mixing circuitry to provide a selectable propagation time. Output signals from the mixing circuitry are...
US-8,283,950 Delay lines, amplifier systems, transconductance compensating systems and methods of compensating
Embodiments of delay lines may include a plurality of delay stages coupled to each other in series from a first stage to a last stage. Each delay stage may...
US-8,283,946 Signaling systems, preamplifiers, memory devices and methods
Signaling systems, preamplifiers, memory devices and methods are disclosed, such as a signaling system that includes a transmitter configured to receive a first...
US-8,283,785 Interconnect regions
Some embodiments include interconnect regions. The regions may contain, along a cross section, a closed-shape interior region having an electrically conductive...
US-8,283,761 Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged...
US-8,283,744 Molybdenum-doped indium oxide structures and methods
Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain indium and monolayers that contain...
US-8,283,710 Low dark current image sensors with epitaxial SiC and/or carbonated channels for array transistors
A pixel cell having a substrate with a isolation channel formed of higher carbon concentrate such as SiC or carbonated silicon. The channel comprising SiC or...
US-8,283,708 Semiconductor devices and methods of forming semiconductor devices having diffusion regions of reduced width
Semiconductor devices and methods for forming semiconductor devices are provided, including semiconductor devices that comprise one or more diffusion region in...
US-8,283,648 Resistance variable memory cell
Methods, devices, and systems associated with phase change memory structures are described herein. One or more embodiments of the present disclosure can reduce...
US-8,283,503 Methods of forming a tellurium alkoxide and methods of forming a mixed halide-alkoxide of tellurium
A method of forming a tellurium alkoxide includes providing a tellurium halide and a non-tellurium alkoxide in a liquid organic solvent. The liquid organic...
US-8,283,259 Methods of removing a metal nitride material
A method of removing a metal nitride material is disclosed. The method comprises forming a semiconductor device structure comprising an exposed metal material...
US-8,283,258 Selective wet etching of hafnium aluminum oxide films
Methods and etchant compositions for wet etching to selectively remove a hafnium aluminum oxide (HfAlO.sub.x) material relative to silicon oxide (SiO.sub.x) are...
US-8,283,257 Systems and methods for oscillating exposure of a semiconductor workpiece to multiple chemistries
Systems and methods for oscillating exposure of a semiconductor workpiece to multiple chemistries are disclosed. A method in accordance with one embodiment...
US-8,283,236 Methods of forming capacitors
Some embodiments include capacitors. The capacitors may include container-shaped storage node structures that have, along a cross-section, a pair of...
US-8,283,203 Methods utilizing microwave radiation during formation of semiconductor constructions
Some embodiments include methods in which microwave radiation is used to activate dopant and/or increase crystallinity of semiconductor material during...
US-8,283,198 Resistive memory and methods of processing resistive memory
Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include forming...
US-8,283,112 Photoresist processing methods
A photoresist processing method includes treating a substrate with a sulfur-containing substance. A positive-tone photoresist is applied on and in contact with...
US-8,282,999 Spin-on film processing using acoustic radiation pressure
An apparatus and process operate to impose sonic pressure upon a spin-on film liquid mass that exhibits a liquid topography and in a solvent vapor overpressure...
US-8,282,988 Methods of making crystalline tantalum pentoxide
There is disclosed a method of forming crystalline tantalum pentoxide on a ruthenium-containing material having an oxygen-containing surface wherein the...
US-8,281,395 Pattern-recognition processor with matching-data reporting module
Disclosed are methods and devices, among which is a device that includes a pattern-recognition processor. The pattern-recognition processor may include a...
US-8,281,193 Method of protecting a test circuit
A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. The test vector decode circuit is driven by an...
US-8,281,074 Interface device for memory in a stack, storage devices and a processor
Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more...
US-8,281,061 Data conditioning to improve flash memory reliability
Methods and apparatus for managing data storage in memory devices utilizing memory arrays of varying density memory cells. Data can be initially stored in lower...
US-8,279,683 Digit line comparison circuits
A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during...
US-8,279,682 Determining memory page status
The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. One method embodiment includes determining a status...
US-8,279,314 Apparatus and method for eliminating artifacts in active pixel sensor (APS) imagers
An active pixel sensor (APS) that includes circuitry to eliminate artifacts in digital images. The APS includes a comparator for comparing a signal level from a...
US-8,278,993 Clock distribution network
Some embodiments include apparatus and methods having a clock path with a combination of current-mode logic (CML) based and complementary metal-oxide...
US-8,278,965 Inspection apparatus
The inspection apparatus includes a probe having a contact for contacting an electrode of an inspected object and having a built-in heater for correcting...
US-8,278,751 Methods of adhering microfeature workpieces, including a chip, to a support member
Methods and systems for adhering microfeature workpieces to support members are disclosed. A method in accordance with one embodiment of the invention includes...
US-8,278,703 Cross-hair cell based floating body device
A non-planar transistor having floating body structures and methods for fabricating the same are disclosed. In certain embodiments, the transistor includes a...
US-8,278,691 Low power memory device with JFET device structures
There is provided a low power memory device with JFET device structures. Specifically, a low power memory device is provided that includes a plurality memory...
US-8,278,653 Nanoparticle positioning technique
Embodiments of the present invention are generally directed to a method for disposing nanoparticles on a substrate. In one embodiment, a substrate having a...
US-8,278,225 Hafnium tantalum oxide dielectrics
A dielectric layer containing a hafnium tantalum oxide film and a method of fabricating such a dielectric layer produce a dielectric layer for use in a variety...
US-8,278,182 Isolation structure for a memory cell using Al.sub.1O.sub.3 dielectric
The invention provides, in one exemplary embodiment, an isolation gate formed over a substrate for biasing the substrate and providing isolation between...
US-8,278,167 Method and structure for integrating capacitor-less memory cell with logic
Methods for fabricating integrated circuits include fabricating a logic device on a substrate, forming an intermediate semiconductor substrate on a surface of...
US-8,278,131 Method and apparatus for dark current and blooming supression in 4T CMOS imager pixel
A method and apparatus for operating an imager pixel that includes the act of applying a relatively small first polarity voltage and a plurality of pulses of a...
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