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Patent # Description
US-RE43,665 Reading non-volatile multilevel memory cells
Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile multilevel memory cells. One method includes...
US-8,266,558 Methods for forming arrays of small, closely spaced features
Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can...
US-8,266,501 Stripe based memory operation
The present disclosure includes methods and devices for stripe-based memory operation. One method embodiment includes writing data in a first stripe across a...
US-8,266,063 Software distribution method and apparatus
The present invention provides for a method and apparatus for distributing digital information, such as software applications, to application users. By...
US-8,264,886 Delayed activation of selected wordlines in memory
Apparatus, systems, and methods may operate to receive an external read command at a control circuit coupled to a memory array. Individual wordline activation...
US-8,264,885 Method for memory cell erasure with a programming monitor of reference cells
Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase...
US-8,264,882 Charge loss compensation during programming of a memory device
In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is...
US-8,264,879 Sensing memory cells
Methods, devices, modules, and systems for operating memory cells are taught. A method for operating memory cells includes programming at least one of the...
US-8,264,041 Semiconductor device with electrically floating body
A semiconductor device along with circuits including the same and methods of operating the same are described. The device includes an electrically floating body...
US-8,263,988 Solid state lighting devices with reduced crystal lattice dislocations and associated methods of manufacturing
Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a substrate...
US-8,263,962 Inverted variable resistance memory cell and method of making the same
An inverted variable resistance memory cell and a method of fabricating the same. The memory cell is fabricated by forming an opening in an insulating layer...
US-8,263,958 Layered resistance variable memory device and method of fabrication
The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics....
US-8,263,457 Methods of forming a plurality of capacitors
A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area...
US-8,260,987 Methods and systems to accomplish variable width data input
Disclosed are methods and systems for variable width data input to a pattern-recognition processor. A variable width data input method may include receiving...
US-8,260,973 Memory controllers, memory systems, solid state drives and methods for processing a number of commands
The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end...
US-8,260,449 Photolithography systems and associated methods of overlay error correction
Several embodiments of photolithography systems and associated methods of overlay error correction are disclosed herein. In one embodiment, a method for...
US-8,259,512 Low voltage sensing scheme having reduced active power down standby current
A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a Psense amplifier...
US-8,259,508 Erase operation control sequencing apparatus, systems, and methods
Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a...
US-8,259,491 Coarse and fine programming in a solid state memory
Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer...
US-8,259,488 Phase-change memory temperature sensitive detector
A Phase-Change Memory (PCM) having a temperature detector with a dedicated PCM bit programmed to an amorphous state and a circuit to determine that the...
US-8,259,461 Apparatus for bypassing faulty connections
Apparatus are disclosed, such as those involving a 3-D integrated circuit. One such apparatus includes a first die including a plurality of vertical connectors...
US-8,258,854 Devices and methods for reducing effects of device mismatch in temperature sensor circuits
A temperature sensor having one or more mirror circuits output temperature dependent output signals is disclosed in one embodiment. The temperature sensor...
US-8,258,836 Locked loops, bias generators, charge pumps and methods for generating control voltages
Locked loops, bias generators, charge pumps and methods for generating control voltages are disclosed, such as a bias generator that generates bias voltages for...
US-8,258,816 Integrated circuit comparator or amplifier
An integrated circuit comparator comprises a differential amplifier, a source follower circuit coupled to a gate terminal of a first transistor in the...
US-8,258,518 Flash memory device having a graded composition, high dielectric constant gate insulator
A graded composition, high dielectric constant gate insulator is formed between a substrate and floating gate in a flash memory cell transistor. The gate...
US-8,258,034 Charge-trap based memory
Methods of fabricating 3D charge-trap memory cells are described, along with apparatus and systems that include them. In a planar stack formed by alternate...
US-8,258,006 Method for fabricating stacked semiconductor components
A semiconductor component includes a carrier and multiple semiconductor substrates stacked and interconnected on the carrier. The carrier includes conductive...
US-8,257,497 Insitu post atomic layer deposition destruction of active species
Systems and methods for insitu post atomic layer deposition (ALD) destruction of active species are provided. ALD processes deposit multiple atomic layers on a...
US-8,256,695 Method for purification of semiconducting single wall nanotubes
A process of forming a semiconductive carbon nanotube structure includes imposing energy on a mixture that contains metallic carbon nanotubes and semiconductive...
US-8,256,293 Devices comprising nanotubes for use as sensors and/or transducers, and related methods
Devices usable as sensors, as transducers, or as both sensors and transducers include one or more nanotubes or nanowires. In some embodiments, the devices may...
US-8,255,788 Method and apparatus for facilitating substitution of digital images with line drawings
One embodiment of the present invention provides a system that facilitates substitution of a full bitmap version of a graphical image with a line drawing...
US-8,255,771 Memory device repair apparatus, systems, and methods
Operations within a memory device to replace one or more selected failing memory cells with one or more repair memory cells and to correct data digits read from...
US-8,254,199 Multi-channel memory and power supply-driven channel selection
Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels...
US-8,254,191 Switched interface stacked-die memory architecture
Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request...
US-8,254,182 Analog sensing of memory cells with a source follower driver in a semiconductor memory device
Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line....
US-8,254,180 Methods of operating memories including characterizing memory cell signal lines
Methods of operating memories facilitate compensating for memory cell signal line propagation delays, such as to increase the overall threshold voltage range...
US-8,254,174 Memory segment accessing in a memory device
Methods for programming memory devices, a memory device, and memory systems are provided. According to at least one such method, bit lines a memory segment are...
US-8,254,173 NAND memory constructions
Some embodiments include NAND memory constructions. The constructions may contain semiconductor material pillars extending upwardly between dielectric regions,...
US-8,253,442 Apparatus and method for signal transmission over a channel
Apparatus and methods are disclosed, such as those involving data transmission. One such apparatus includes a transmitter, a receiver, and a channel. The...
US-8,253,433 Testing apparatus for integrated circuit
An apparatus for testing an integrated circuit comprises: a chip unit with a plurality of electronic parts such as chip units arranged on the upside of a chip...
US-8,253,396 Voltage regulator system
The present disclosure includes circuits, systems and methods for regulating voltage. One voltage regulator system embodiment includes a voltage regulator...
US-8,253,230 Disabling electrical connections using pass-through 3D interconnects and associated systems and methods
Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are...
US-8,253,203 Electrostatic discharge (ESD) protection circuit
An electrostatic discharge (ESD) protection circuit that includes a parallel connection of parasitic vertical and lateral bipolar junction transistors (BJTs)...
US-8,253,198 Devices for shielding a signal line over an active region
A multi-path transistor includes an active region including a channel region and an impurity region. A gate is dielectrically separated from the channel region....
US-8,253,191 Vertically-oriented semiconductor selection device for cross-point array memory
A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first...
US-8,252,697 Zinc-tin oxide thin-film transistors
Methods of forming transparent zinc-tin oxide structures are described. Devices that include transparent zinc-tin oxide structures as at least one of a channel...
US-8,252,658 Methods of etching trenches into silicon of a semiconductor substrate, methods of forming trench isolation in...
A method of etching trenches into silicon of a semiconductor substrate includes forming a mask over silicon of a semiconductor substrate, with the mask...
US-8,252,646 Peripheral gate stacks and recessed array gates
Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic...
US-8,252,622 Phase change current density control structure
A phase change memory element and method of forming the same. The memory element includes first and second electrodes. A first layer of phase change material is...
US-8,252,194 Methods of removing silicon oxide
A method of removing at least a portion of a silicon oxide material is disclosed. The silicon oxide is removed by exposing a semiconductor structure comprising...
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