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Patent # Description
US-8,281,061 Data conditioning to improve flash memory reliability
Methods and apparatus for managing data storage in memory devices utilizing memory arrays of varying density memory cells. Data can be initially stored in lower...
US-8,279,683 Digit line comparison circuits
A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during...
US-8,279,682 Determining memory page status
The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. One method embodiment includes determining a status...
US-8,279,314 Apparatus and method for eliminating artifacts in active pixel sensor (APS) imagers
An active pixel sensor (APS) that includes circuitry to eliminate artifacts in digital images. The APS includes a comparator for comparing a signal level from a...
US-8,278,993 Clock distribution network
Some embodiments include apparatus and methods having a clock path with a combination of current-mode logic (CML) based and complementary metal-oxide...
US-8,278,965 Inspection apparatus
The inspection apparatus includes a probe having a contact for contacting an electrode of an inspected object and having a built-in heater for correcting...
US-8,278,751 Methods of adhering microfeature workpieces, including a chip, to a support member
Methods and systems for adhering microfeature workpieces to support members are disclosed. A method in accordance with one embodiment of the invention includes...
US-8,278,703 Cross-hair cell based floating body device
A non-planar transistor having floating body structures and methods for fabricating the same are disclosed. In certain embodiments, the transistor includes a...
US-8,278,691 Low power memory device with JFET device structures
There is provided a low power memory device with JFET device structures. Specifically, a low power memory device is provided that includes a plurality memory...
US-8,278,653 Nanoparticle positioning technique
Embodiments of the present invention are generally directed to a method for disposing nanoparticles on a substrate. In one embodiment, a substrate having a...
US-8,278,225 Hafnium tantalum oxide dielectrics
A dielectric layer containing a hafnium tantalum oxide film and a method of fabricating such a dielectric layer produce a dielectric layer for use in a variety...
US-8,278,182 Isolation structure for a memory cell using Al.sub.1O.sub.3 dielectric
The invention provides, in one exemplary embodiment, an isolation gate formed over a substrate for biasing the substrate and providing isolation between...
US-8,278,167 Method and structure for integrating capacitor-less memory cell with logic
Methods for fabricating integrated circuits include fabricating a logic device on a substrate, forming an intermediate semiconductor substrate on a surface of...
US-8,278,131 Method and apparatus for dark current and blooming supression in 4T CMOS imager pixel
A method and apparatus for operating an imager pixel that includes the act of applying a relatively small first polarity voltage and a plurality of pulses of a...
US-8,276,185 Enhanced security memory access method and architecture
A memory device includes: at least one storage area for storing data; a protection control structure adapted to selectively allow an external device access to...
US-8,276,042 Determining sector status in a memory device
The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. A number of method embodiments include reading data...
US-8,275,926 Filtered register architecture to generate actuator signals
In various embodiments, apparatus and systems, as well as methods, may include an enhanced register to provide actuator signals to a memory array, the enhanced...
US-8,274,849 Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of...
An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each...
US-8,274,835 Mitigation of runaway programming of a memory device
Methods for mitigating runaway programming in a memory device, methods for program verifying a memory device, a memory device, and a memory system are provided....
US-8,274,833 Mitigation of data corruption from back pattern and program disturb in a non-volatile memory device
A write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program disturb in memory cells. Original data to...
US-8,274,832 Dynamic polarization for reducing stress induced leakage current
Subject matter disclosed herein relates to non-volatile flash memory, and more particularly to a method of reducing stress induced leakage current.
US-8,274,823 Methods and apparatus utilizing expected coupling effect in the programming of memory cells
Methods and memory devices configured to utilize predicted coupling effects of neighboring memory cells in the programming of target memory cells can be...
US-8,274,777 High aspect ratio openings
A capacitor forming method includes forming an electrically conductive support material over a substrate, with the support material containing at least 25 at %...
US-8,274,221 Plasma-generating structures, display devices, and methods of forming plasma-generating structures
Some embodiments include methods of forming plasma-generating microstructures. Aluminum may be anodized to form an aluminum oxide body having a plurality of...
US-8,274,163 Method and apparatus providing integrated circuit having redistribution layer with recessed connectors
A method of making a semiconductor die includes forming a trench around a conductive stud extending from the first side to a second side of a substrate to...
US-8,274,110 Vertically-oriented semiconductor selection device providing high drive current in cross-point array memory
A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first...
US-8,274,106 DRAM layout with vertical FETs and method of formation
DRAM cell arrays having a cell area of about 4F.sup.2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The...
US-8,274,081 Semiconductor constructions
Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection...
US-8,273,647 Methods of forming patterns, and methods of forming integrated circuits
Some embodiments include methods of forming patterns in substrates by utilizing block copolymer assemblies as patterning materials. A block copolymer assembly...
US-8,273,643 Diodes, and methods of forming diodes
Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is...
US-8,273,635 Semiconductor fabrication method and system
A method for manufacturing a semiconductor device is disclosed. In one embodiment, the method includes attaching a carrier to a substrate including a via to...
US-8,273,634 Methods of fabricating substrates
A method of fabricating a substrate includes forming first and second spaced features over a substrate. The first spaced features have elevationally outermost...
US-8,273,619 Methods of implanting dopant into channel regions
The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger...
US-8,273,589 Light emitting diodes and methods for manufacturing light emitting diodes
Light emitting diodes and methods for manufacturing light emitting diodes are disclosed herein. In one embodiment, a method for manufacturing a light emitting...
US-8,273,261 Methods of forming semiconductor constructions
The invention includes methods in which silicon is removed from titanium-containing container structures with an etching composition having a...
US-8,273,177 Titanium-doped indium oxide films
An apparatus and methods of forming the apparatus include a film of transparent conductive titanium-doped indium oxide for use in a variety of configurations...
US-8,273,165 Compacted air flow rapid fluid evaporation system
A total water desalination system is disclosed that includes a centrifugal separator, a feed-water device controlled by a relative humidity sensor, an air pump,...
US-8,271,823 DLL phase detection using advanced phase equalization
A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL)....
US-8,271,697 State change in systems having devices coupled in a chained configuration
The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of...
US-8,271,239 Generation and manipulation of realistic signals for circuit and system verification
Methods for generating realistic waveforms with controllable voltage noise and timing jitter in a computer-based simulation environment and the simulation of a...
US-8,270,224 Voltage discharge circuits and methods
Memory devices, memory systems, discharge circuits, and methods for discharging a capacitance are disclosed. In one such memory device, a discharge circuit is...
US-8,270,205 Variable resistance memory device with an interfacial adhesion heating layer, systems using the same and...
A variable resistance memory element and method of forming the same. The memory element includes a first electrode, a resistivity interfacial layer having a...
US-8,269,540 Circuitry and methods for improving differential signals that cross power domains
Disclosed herein are circuitry and methods for improving differential signals that cross power domains. In an example embodiment, the power supply domain...
US-8,269,328 Stacked die package for peripheral and center device pad layout device
An assembly method is disclosed that includes providing a substrate, securing a first semiconductor device on a first surface thereof, and superimposing at...
US-8,269,326 Semiconductor device assemblies
An interposer includes a substrate, a conductive structure configured to contact the back side of a semiconductor device and contact pads. The interposer may...
US-8,269,306 Isolation regions
A dielectric liner is formed in first and second trenches respectively in first and second portions of a substrate. A layer of material is formed overlying the...
US-8,269,254 Silicon on germanium
The use of atomic layer deposition (ALD) to form a semiconductor structure of a silicon film on a germanium substrate is disclosed. An example embodiment...
US-8,268,732 Methods of utilizing block copolymers to form patterns
Some embodiments include methods of forming patterns utilizing copolymer. A copolymer composition is formed across a substrate. The composition includes...
US-8,268,730 Methods of masking semiconductor device structures
A method for fabricating semiconductor device structures includes forming a non-conformal mask over a surface of a substrate. Non-conformal mask material with a...
US-8,268,723 Methods for forming semiconductor device structures
The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a...
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