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Bonding pads with thermal pathways
Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal...
Trench isolation implantation
Embodiments of the disclosure include a shallow trench isolation structure having a dielectric material with energetic species implanted to a predetermined...
Semiconductor with through-substrate interconnect
Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor...
Fuses, and methods of forming and using fuses
Some embodiments include a fuse having a tungsten-containing structure directly contacting an electrically conductive structure. The electrically conductive...
Apparatus including memory system controllers and related methods for
memory management using block tables
Memory controllers can include a switch and non-volatile memory control circuitry including channel control circuits coupled to the switch. The channel control...
Access line management in a memory device
Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device...
Memory array plane select
Memory arrays and methods of forming the same are provided. An example memory array can include at least one plane having a plurality of memory cells arranged...
Secure compact flash
Methods and apparatus are provided, such as a memory card with a processor and nonvolatile memory coupled thereto. The nonvolatile memory has a secure area...
Method and apparatus to perform concurrent read and write memory
Subject matter disclosed herein relates to read and write processes of a memory device. During a write process to a particular partition in a memory array, a...
Methods and controllers for executing an instruction set are provided. In one such method, executing an instruction set includes executing an instruction of one...
Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits....
Boolean logic in a state machine lattice
Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic...
Memory cells and methods of forming memory cells
Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the...
Methods and apparatuses having strings of memory cells and select gates
with double gates
An apparatus, a method, and a system are disclosed. The apparatus includes a string of memory cells coupled to a select gate drain transistor that has a front...
Semiconductor device assembly with package interconnect extending into
overlying spacer material, and...
Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material...
Semiconductor substrates with unitary vias and via terminals, and
associated systems and methods
Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a...
Stair step formation using at least two masks
Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a...
Program and read trim setting
A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device...
Apparatuses and methods including supply current in memory
Some embodiments include apparatuses and methods having first conductive lines, second conductive lines, a memory array including memory cells, each of the...
Program-disturb management for phase change memory
Methods, systems, and devices related to memory, including read or write performance of a phase change memory, are described. A plurality of memory cells of a...
Methods and apparatuses for controlling timing paths and latency based on
a loop delay
Apparatuses and methods for controlling timing circuit locking and/or latency during a change in clock frequency (e.g. gear down mode) are described herein. An...
Apparatuses and methods for implementing masked write commands
Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and...
Wiring configuration of a bus system and power wires in a memory chip
Devices and circuits for wiring configurations of a bus system and power supply wires in a memory chip with improved power efficiencies. The effective...
Apparatus providing simplified alignment of optical fiber in photonic
A structure for optically aligning an optical fiber to a photonic device and method of fabrication of same. The structure optically aligns an optical fiber to...
Apparatuses and methods for phase interpolating clock signals and for
providing duty cycle corrected clock signals
Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes...
Apparatuses and methods for providing oscillation signals
Apparatuses and methods are disclosed for oscillators that are substantially insensitive to supply voltage variations. In one such example apparatus, a...
Memory including a selector switch on a variable resistance memory cell
Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a...
Magnetic tunnel junctions, methods used while forming magnetic tunnel
junctions, and methods of forming...
A method used while forming a magnetic tunnel junction comprises forming non-magnetic tunnel insulator material over magnetic electrode material. The tunnel...
Recessed access devices and gate electrodes
Recessed access transistor devices used with semiconductor devices may include gate electrodes having materials with multiple work functions, materials that are...
Semiconductor devices and packages
Semiconductor device packages include first and second semiconductor dice in a facing relationship. At least one group of solder bumps is substantially along a...
Method for manufacturing tested apparatus and method for manufacturing
system including tested apparatus
Disclosed herein is a method for manufacturing a tested apparatus that includes forming a stacked structure that includes a plurality of first semiconductor...
Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium aluminum oxynitride (ZrAlON) for use in a variety of electronic devices....
Concurrently reading first and second pages of memory cells having
different page addresses
In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The...
Two-part programming methods
A first memory cell is programmed to a first level using a first set of program pulses within a first programming voltage range. A second memory cell to be...
Output buffer circuit with low sub-threshold leakage current
A device includes a cutting circuit that is coupled between power supply lines in series with first and second output circuits which drive an output terminal in...
Methods and apparatuses for reducing power consumption in a pattern
Apparatuses and methods are provided for reducing power consumption in a pattern-recognition processor. A power control circuit may be coupled to a block of...
Protection zones in virtualized physical addresses for reconfigurable
memory systems using a memory abstraction
Systems and methods define a memory system using an abstracted memory protocol that enables virtual to physical mapping of memory address requests at an...
Methods and systems for power management in a pattern recognition
A device includes a state machine. The state machine includes a plurality of blocks, where each of the blocks includes a plurality of rows. Each of these rows...
Methods of forming material over a substrate and methods of forming
A method of forming a material over a substrate includes performing at least one iteration of the following temporally separated ALD-type sequence. First, an...
Memory cells and methods of forming memory cells
Some embodiments include a memory cell having a first electrode, and an intermediate material over and directly against the first electrode. The intermediate...
Methods of forming a metal chalcogenide material and related methods of
forming a memory cell
A method of forming a metal chalcogenide material. The method comprises introducing a metal precursor and a chalcogenide precursor into a chamber, and reacting...
Solid state optoelectronic device with plated support substrate
A vertical solid state lighting (SSL) device is disclosed. In one embodiment, the SSL device includes a light emitting structure formed on a growth substrate....
Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge storage units in...
Methods and apparatuses for stacked device testing
Various embodiments include apparatus, systems, and methods having multiple dies arranged in a stack in which the dies or a logic chip in communication with the...
Comparison operations on logical representations of values in memory
One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first...
Over-limit electrical condition protection circuits and methods
Apparatuses and methods for protecting a circuit from an over-limit electrical condition are disclosed. One example apparatus includes a protection circuit...
Semiconductor constructions and memory arrays
Some embodiments include semiconductor constructions having an electrically conductive interconnect with an upper surface, and having an electrically conductive...
Solid state transducers with state detection, and associated systems and
Solid state transducers with state detection, and associated systems and methods are disclosed. A solid state transducer system in accordance with a particular...
Redistribution structures for microfeature workpieces
Microfeature dies with redistribution structures that reduce or eliminate line interference are disclosed. The microfeature dies can include a substrate having...
Methods of programming memory devices
Methods of programming memory devices include biasing each data line of a plurality of data lines to a program inhibit voltage; discharging a first portion of...