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Patent # Description
US-1,007,4724 Apparatus including gettering agents in memory charge storage structures
Apparatus having a processor and a memory device in communication with the processor, the memory device including an array of memory cells and a control logic...
US-1,007,4693 Connections for memory electrode lines
Subject matter disclosed herein relates to an integrated circuit device having a socket interconnect region for connecting a plurality of conductive lines at a...
US-1,007,4662 Memory cell and an array of memory cells
A memory cell includes a first electrode and a second electrode. A select device and a programmable device are in series with each other between the first and...
US-1,007,4633 Semiconductor die assemblies having molded underfill structures and related technology
A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies and a package substrate...
US-1,007,4603 Methods of forming a semiconductor device comprising first and second nitride layers
A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well...
US-1,007,4599 Semiconductor dies with recesses, associated leadframes, and associated systems and methods
Semiconductor dies with recesses, associated leadframes, and associated systems and methods are disclosed. A semiconductor system in accordance with one...
US-1,007,4443 Semiconductor device including fuse circuit
Disclosed here is a semiconductor device that comprises plurality of input nodes configured to be supplied with input signals, a decoder coupled to the input...
US-1,007,4442 Semiconductor device and control method of the same
A semiconductor device comprises a bit determination circuit to count the number of bits at a first level in an input address signal formed of a plurality of...
US-1,007,4432 Programming of memory devices
Methods of operating a memory device include programming a page of a memory block of the memory device using a particular starting programming voltage,...
US-1,007,4431 3D NAND memory Z-decoder
Apparatus and methods are disclosed, including an apparatus having first and second units of vertically arranged strings of memory cells, each unit including...
US-1,007,4430 Multi-deck memory device with access line and data line segregation between decks and method of operation thereof
Some embodiments include apparatuses and methods using a substrate, a first memory cell block including first memory cell strings located over the substrate,...
US-1,007,4419 Refresh architecture and algorithm for non-volatile memories
Methods and systems to refresh a nonvolatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device...
US-1,007,4416 Apparatuses and methods for data movement
The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays...
US-1,007,4415 Boosting a digit line voltage for a write operation
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. The magnitude of a voltage applied across a ferroelectric...
US-1,007,4414 Apparatuses and methods including ferroelectric memory and for operating ferroelectric memory
Apparatuses and methods are disclosed that in ferroelectric memory and for operating ferroelectric memory. An example apparatus includes a capacitor having a...
US-1,007,4407 Apparatuses and methods for performing invert operations using sensing circuitry
Apparatuses and methods related to performing logical operations using sensing circuitry are disclosed. One example apparatus comprises an array of memory cells...
US-1,007,4406 Apparatuses and methods for performing logical operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an...
US-1,007,3786 Apparatuses and methods for compute enabled cache
The present application includes apparatuses and methods for compute enabled cache. An example apparatus includes a compute component, a memory and a controller...
US-1,007,3725 Distributed input/output virtualization
The present disclosure includes apparatuses and methods related to distributed input/output (I/O) virtualization. A number of embodiments include an apparatus...
US-1,007,3635 Multiple endianness compatibility
Examples of the present disclosure provide apparatuses and methods for multiple endianness compatibility. An example method comprises receiving a plurality of...
US-1,007,3477 Apparatuses and methods for temperature independent current generations
Apparatuses and methods for providing a current independent of temperature are described. An example apparatus includes a current generator that includes two...
US-1,007,3342 Method of forming patterns
A substrate having a target material layer is provided. A first hard mask layer, a second hard mask layer, and a photoresist layer are formed on the target...
US-1,007,0432 Wireless devices and systems including examples of configuration modes for baseband units and remote radio heads
Examples described herein include systems and methods which include wireless devices and systems with examples of configuration modes for baseband units (BBU)...
US-1,006,9069 Apparatuses including electrodes having a conductive barrier material and methods of forming same
Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus...
US-1,006,9067 Memory arrays and methods of forming memory cells
Some embodiments include methods of forming memory cells. A series of rails is formed to include bottom electrode contact material. Sacrificial material is...
US-1,006,8947 Arrays of memory cells and methods of forming an array of memory cells
An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced...
US-1,006,8875 Apparatuses and methods for heat transfer from packaged semiconductor die
Apparatuses and methods for heat transfer from packaged semiconductor die are described. For example, an apparatus may include a plurality of die in a stack,...
US-1,006,8664 Column repair in memory
Apparatuses and methods related to column repair in memory are described. An apparatus can include sensing circuitry. The sensing circuitry can include a first...
US-1,006,8662 Semiconductor device including a roll call circuit for outputting addresses of defective memory cells
A semiconductor device that includes a plurality of memory cells assigned with addresses that are different from each other, a redundant memory cell replacing a...
US-1,006,8655 Inferring threshold voltage distributions associated with memory cells via interpolation
Apparatuses and methods for inferring threshold voltage distributions associated with memory cells via interpolation are described herein. A number of...
US-1,006,8653 Methods of operating memory
Methods of operating memory include generating a data value indicative of a level of a property sensed from a data line while applying potentials to control...
US-1,006,8652 Apparatuses and methods for determining population count
The present disclosure includes apparatuses and methods related to determining population count. An example apparatus comprises an array of memory cells coupled...
US-1,006,8649 Apparatuses and methods for performing multiple memory operations
The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory...
US-1,006,8648 Distributed mode registers in memory devices
A semiconductor device may include a plurality of memory banks, a plurality of mode registers that may control an operational mode associated with each of the...
US-1,006,8629 Ferroelectric memory cell sensing
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may maintain a digit line voltage at a ground...
US-1,006,8623 Apparatuses and methods for compensating for process, voltage, and temperature variation in a memory
Systems and methods are described for compensating for variations in process, voltage, temperature, or combinations thereof in an apparatus. An example...
US-1,006,8109 Secure subsystem
An apparatus for performing secure operations with a dedicated secure processor is described in one embodiment. The apparatus includes security firmware...
US-1,006,7901 Methods and apparatuses for providing data received by a state machine engine
An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine...
US-1,006,7890 Apparatuses and methods for variable latency memory operations
Apparatuses and methods for variable latency memory operations are disclosed herein. An example apparatus may include a memory configured to provide first...
US-1,006,7827 Error correction code event detection
Methods, systems, and devices for operating a memory cell or cells are described. An error in stored data may be detected by an error correction code (ECC)...
US-1,006,7764 Apparatuses and methods for memory operations having variable latencies
Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation...
US-1,006,7676 Hybrid memory drives, computer system, and related method for operating a multi-mode hybrid drive
A multi-mode hybrid memory drive comprises a bulk memory device and a removable cache memory device. A controller of the bulk memory device may be configured to...
US-1,006,5193 Processing of grains and the like
Methods for processing of grains and the like and products produced by such processing, the invention in preferred embodiments subjects whole grains or portions...
US-1,006,5186 Fluidic circuits and related manufacturing methods
Fluidic cartridges, and manufacture thereof, having a plurality of circuit element subtypes containing pneumatically operated diaphragm members, where the...
US-1,006,3799 Apparatus and method for eliminating artifacts in active pixel sensor (APS) imagers
An active pixel sensor (APS) that includes circuitry to eliminate artifacts in digital images. The APS includes a comparator for comparing a signal level from a...
US-1,006,3241 Die location compensation
Embodiments are described that compensate for a difference in a characteristic (e.g., of performance or operation) of a semiconductor device that is a function...
US-1,006,3240 Apparatuses with an embedded combination logic circuit for high speed operations
Apparatuses for performing combination logic operations with an combination logic circuit are disclosed. According to one embodiment, the apparatus comprises a...
US-1,006,3234 Half-frequency command path
A semiconductor device includes a clock divider that receives a clock signal and generates even and odd clock signals. The clock signal includes a first...
US-1,006,2844 Apparatuses including electrodes having a conductive barrier material and methods of forming same
Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus...
US-1,006,2835 Magnetic tunnel junctions
A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material, a conductive second magnetic electrode spaced...
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