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Patent # Description
US-1,017,6858 Adjusting instruction delays to the latch path in DDR5 DRAM
Memory devices may provide a communication interface that is configured to receive control signals, and/or address signals from user circuitry, such as a...
US-1,017,6851 Loop structure for operations in memory
Examples of the present disclosure provide apparatuses and methods related to performing a loop structure for operations performed in memory. An example...
US-1,017,6328 Self-measuring nonvolatile memory device systems and methods
One embodiment describes a computing system that includes a boot device. The boot device includes nonvolatile memory that stores startup routine instructions...
US-1,017,6091 Methods of operating a memory system including data collection and compression
Methods of operating a storage device include reading first data from a first storage location of a first memory of the storage device, storing the first data...
US-1,017,6040 Error correction code (ECC) operations in memory
The present disclosure includes apparatuses and methods for ECC operation associated with memory. One example apparatus comprises a controller configured to...
US-1,017,6039 Self-accumulating exclusive OR program
Methods and apparatus for Exclusive OR (XOR) programming of a memory device include a program internal to a device calculates parity or other values using an...
US-1,017,5915 Data randomization for flash memory
Data words written to an SSD device, or other device or output data stream, may be randomized using a seed based on physical addressing information, such as a...
US-1,017,5908 Systems and methods for providing file information in a memory system protocol
A controller of a memory device controls placement of data blocks by receiving, from a host electronic device, one or more commands of a memory system protocol....
US-1,017,5902 Managing host communication with a regulator in a low power mode
A solid-state drive (SSD) includes a connector communicatively coupling the SSD to a host device, a controller coupled to the connector, and a memory device....
US-1,017,1032 Apparatuses and methods for temperature independent oscillators
Apparatuses and methods for temperature independent oscillator circuits are disclosed herein. An example apparatus may include a pulse generator circuit...
US-1,017,0668 Solid state lighting devices with improved current spreading and light extraction and associated methods
Solid state lighting ("SSL") devices with improved current spreading and light extraction and associated methods are disclosed herein. In one embodiment, an SSL...
US-1,017,0639 3D memory
Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional...
US-1,017,0545 Memory arrays
The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom...
US-1,017,0493 Assemblies having vertically-stacked conductive structures
Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of...
US-1,017,0491 Memory including blocking dielectric in etch stop tier
Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to...
US-1,017,0490 Memory device including pass transistors in memory tiers
Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes a semiconductor material, a pillar extending through...
US-1,017,0448 Apparatus and method of power transmission sensing for stacked devices
Apparatuses for supplying power supply voltage in a plurality of dies are described. An example apparatus includes: a circuit board; a regulator on the circuit...
US-1,017,0389 Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods
Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die...
US-1,017,0248 Structure and methods of forming the structure
Capacitors, apparatus including a capacitor, and methods for forming a capacitor are provided. One such capacitor may include a first conductor a second...
US-1,017,0196 Apparatuses and methods to control body potential in 3D non-volatile memory operations
Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line...
US-1,017,0194 Asymmetrical multi-gate string driver for memory device
Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a first group of conductive materials...
US-1,017,0193 Apparatus and methods of operating memory for negative gate to body conditions
Methods of operating a memory, and apparatus so configured, include applying a first voltage level to a first voltage node connected to a first end of a string...
US-1,017,0191 Electronic memory device having two portions that can be decoupled
A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory...
US-1,017,0189 Apparatus and methods including source gates
Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor...
US-1,017,0188 3D memory device including shared select gate connections between memory blocks
Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string...
US-1,017,0187 Apparatuses and methods using negative voltages in part of memory write read, and erase operations
Some embodiments include apparatuses and methods having a memory cell string that can include memory cells located in different levels of the apparatus. The...
US-1,017,0183 Method of storing and retrieving data for a resistive random access memory (RRAM) array with multi-memory cells...
Some embodiments include methods of storing and retrieving data for an RRAM array. The array is subdivided into a plurality of memory bits, with each memory bit...
US-1,017,0174 Apparatus and methods for refreshing memory
Apparatuses for executing row hammer refresh are described. An example apparatus includes: memory banks, each memory bank of the memory banks includes: a latch...
US-1,017,0173 Charge mirror-based sensing for ferroelectric memory
Methods, systems, and devices for a sensing scheme that extracts the full or nearly full remnant polarization charge difference between two logic states of a...
US-1,017,0169 Apparatuses and methods involving accessing distributed sub-blocks of memory cells
Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in...
US-1,017,0167 Single node power management for multiple memory devices
Some embodiments include apparatuses and methods having a node to couple to a plurality of memory devices, memory cells, and a module to perform an operation on...
US-1,016,9226 Persistent content in nonvolatile memory
Applications may request persistent storage in nonvolatile memory. The persistent storage is maintained across power events and application instantiations....
US-1,016,9144 Non-volatile memory including selective error correction
Some embodiments include apparatuses and methods using a first memory area and a second memory area included a memory device, and using control circuitry...
US-1,016,8918 Recycled version number values in flash memory
Various embodiments include methods, apparatus, and systems for assigning a plurality of version number values to instances of a logical entity of a memory...
US-1,016,8724 Apparatuses and methods for providing reference voltages
A reference voltage generator is disclosed that may provide a plurality of reference voltages. A reference voltage generator may include a voltage divider, a...
US-1,016,8233 Semiconductor device including sensor
Disclosed here is an apparatus that includes a sensor including a plurality of sense nodes, a plurality of first latch circuits including a plurality of first...
US-1,016,5683 Apparatus and methods for via connection with reduced via currents
Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first...
US-1,016,4817 Methods and apparatuses for signal translation in a buffered memory
According to one embodiment, A data buffer is described. The data buffer comprises a first input/output circuit configured to receive and provide a first signal...
US-1,016,4805 Characterization of decision feedback equalizer taps
Various embodiments, disclosed herein, can include apparatus and methods to characterize taps of a decision feedback equalizer of a data receiver. In...
US-1,016,4642 Circuits, apparatuses, and methods for frequency division
Circuits, apparatuses, and methods are disclosed for frequency division. In one such example circuit, a frequency divider is configured to alternate between...
US-1,016,4624 Apparatuses for reducing off state leakage currents
Apparatuses for reducing leakage currents during an off state for transistors is described herein. An example apparatus includes a switch having an input node...
US-1,016,4618 Jitter cancellation with automatic performance adjustment
Methods, systems, and devices for jitter cancellation with automatic performance adjustment are described. Within a clock distribution system in an electronic...
US-1,016,4187 Methods, apparatuses, and circuits for programming a memory device
Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.
US-1,016,4178 Methods for forming narrow vertical pillars and integrated circuit devices having the same
In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some...
US-1,016,4168 Magnetic memory cell structures, arrays, and semiconductor devices
Methods of forming memory cells, magnetic memory cell structures, and arrays of magnetic memory cell structures are disclosed. Embodiments of the methods...
US-1,016,4044 Gate stacks
Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten...
US-1,016,4009 Memory device including voids between control gates
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a channel to conduct current, the channel including...
US-1,016,4004 Semiconductor device having a second conductive layer partially embedded in a stacked insulating structure and...
Disclosed herein is a device that includes: a semiconductor substrate; a first insulating layer over a surface of the semiconductor substrate; first and second...
US-1,016,3978 Memory cell with independently-sized elements
Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in...
US-1,016,3977 Chalcogenide memory device components and composition
Systems, devices, and methods related to or that employ chalcogenide memory components and compositions are described. A memory device, such as a selector...
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