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| Patent # | Description |
|---|---|
| US-8,248,881 |
Method and apparatus for managing behavior of memory devices A method of managing power consumption by a memory in a memory device includes determining whether the device is powered by a depletable power supply, and if it... |
| US-8,248,880 |
Voltage regulators, amplifiers, memory devices and methods Circuits, devices and methods are provided, such as an amplifier (e.g., a voltage regulator) that includes a feedback circuit that supplies negative feedback... |
| US-8,248,870 |
Method and apparatus for synchronizing data from memory arrays According to one embodiment, a combination is comprised of a plurality of sense amps, each having an input for receiving a clock signal. A data bus is for... |
| US-8,248,868 |
Asynchronous/synchronous interface The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling... |
| US-8,248,851 |
System, apparatus, and reading method for NAND memories A system, apparatus, and method to read a memory cell of a memory device is described. The method includes biasing a drain select line (DSL), a source select... |
| US-8,247,907 |
Methods for forming interconnects in microelectronic workpieces and
microelectronic workpieces formed using... Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods are disclosed herein. One embodiment,... |
| US-8,247,871 |
1T/0C RAM cell with a wrapped-around gate device structure A memory device and a method of forming the memory device. The memory device comprises a storage transistor at a surface of a substrate comprising a body... |
| US-8,247,789 |
Memory cells and methods of forming memory cells Some embodiments include a memory cell that contains programmable material sandwiched between first and second electrodes. The memory cell can further include a... |
| US-8,247,302 |
Methods of fabricating substrates A method of fabricating a substrate includes forming spaced first features and spaced second features over a substrate. The first and second features alternate... |
| US-8,245,176 |
Integrated circuit apparatus, systems, and methods High density circuit modules are formed by stacking integrated circuit (IC) chips one above another. Unused input/output (I/O) locations on some of the chips... |
| US-8,245,100 |
Error recovery storage along a nand-flash string Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are... |
| US-8,245,024 |
Booting in systems having devices coupled in a chained configuration The present disclosure includes methods, devices, and systems for booting in systems having devices coupled in a chained configuration. One or more embodiments... |
| US-8,244,937 |
Solid state storage device controller with parallel operation mode Solid state storage devices and methods for operation of solid state storage devices are disclosed. In one such method, a master memory controller is comprised... |
| US-8,243,544 |
Reduction of fusible links and associated circuitry on memory dies The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among... |
| US-8,243,538 |
Small unit internal verify read in a memory device Methods for small unit internal verify read operation and a memory device are disclosed. In one such method, expected data is programmed into a grouping of... |
| US-8,243,529 |
Memory device page buffer configuration and methods Memory devices and methods are described that include communication circuitry between page buffers in a memory array. Examples include communication circuitry... |
| US-8,243,523 |
Sensing operations in a memory device Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a... |
| US-8,243,521 |
Method for kink compensation in a memory This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory... |
| US-8,243,513 |
Non-volatile multilevel memory cells with data read of reference cells Embodiments of the present disclosure provide methods, devices, modules, and systems for non-volatile multilevel memory cell data retrieval with data read of... |
| US-8,243,506 |
Phase change memory structures and methods Methods, devices, and systems associated with phase change memory structures are described herein. One method of forming a phase change memory structure... |
| US-8,243,497 |
Phase change memory device with reduced programming disturbance A Phase Change Memory device with reduced programming disturbance and its operation are described. The Phase Change Memory includes an array with word lines and... |
| US-8,243,479 |
On-die anti-resonance structure for integrated circuit A structure and method for reducing the effects of chip-package resonance in an integrated circuit assembly is described. A series RLC circuit is employed to... |
| US-8,243,164 |
Method, apparatus, and system for selecting pixels for automatic white
balance processing A method, apparatus, and system that use a white balance operation. A selecting process is applied to each pixel selected and considered for automatic white... |
| US-8,242,555 |
FIN field effect transistor Methods, devices and systems for a FinFET are provided. One method embodiment includes forming a FinFET by forming a relaxed silicon germanium... |
| US-8,242,554 |
Integrated two device non-volatile memory The non-volatile memory cell is comprised of the series integration of a fixed threshold element and a bistable element. The fixed threshold element is formed... |
| US-8,242,008 |
Methods of removing noble metal-containing nanoparticles, methods of
forming NAND string gates, and methods of... Some embodiments include methods of removing noble metal-containing particles from over a substrate. The substrate is exposed to a composition that reduces... |
| US-8,241,987 |
Methods of forming capacitors A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and... |
| US-8,241,947 |
Phase change memory elements using energy conversion layers, memory arrays
and systems including same, and... A phase change memory element and method of forming the same. The memory element includes a phase change material layer electrically coupled to first and second... |
| US-8,241,944 |
Resistive RAM devices and methods The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One... |
| US-8,241,708 |
Formation of insulator oxide films with acid or base catalyzed hydrolysis
of alkoxides in supercritical carbon... Metal and/or silicon oxides are produced by hydrolysis of alkoxide precursors in the presence of either an acid catalyst or a base catalyst in a supercritical... |
| US-8,239,725 |
Data storage with an outer block code and a stream-based inner code Apparatus and methods store stream-based error recovery data for a memory array, such as a NAND flash array. Conventionally, data is block coded per industry... |
| US-8,239,636 |
Bit inversion in memory devices Bit inversions occurring in memory systems and apparatus are provided. Data is acquired from a source destined for a target. As the data is acquired from the... |
| US-8,239,629 |
Hierarchical memory architecture to connect mass storage devices A hierarchical memory storage using a concentrator device that is located between a processor and memory storage devices to provide a succession of memory... |
| US-8,239,614 |
Memory super block allocation The present disclosure includes methods and devices for memory block selection. In one or more embodiments, a memory controller includes control circuitry... |
| US-8,239,607 |
System and method for an asynchronous data buffer having buffer write and
read pointers A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device... |
| US-8,239,432 |
Incorporating noise and/or jitter into waveform generation One or more embodiments are disclosed that involve computer implementable techniques for generating simulate-able waveforms without the need for repeatedly... |
| US-8,238,244 |
Packet deconstruction/reconstruction and link-control The present disclosure includes methods, devices, and systems for packet processing. One method embodiment for packet flow control includes deconstructing a... |
| US-8,238,176 |
I/O circuit with phase mixer for slew rate control An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state... |
| US-8,238,170 |
Non-volatile memory cell healing Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first... |
| US-8,238,167 |
Memory voltage cycle adjustment The present disclosure includes various method, device, system, and module embodiments for memory cycle voltage adjustment. One such method embodiment includes... |
| US-8,238,165 |
Word line drivers in non-volatile memory device and method having a shared
power bank and processor-based... A word line driver system that utilizes a voltage selection circuit to supply one of several voltages to an output node coupled to a plurality of word line... |
| US-8,238,155 |
Multilevel memory cell operation One or more embodiments of the present disclosure provide methods, devices, and systems for operating non-volatile multilevel memory cells. One method... |
| US-8,238,151 |
Transient heat assisted STTRAM cell for lower programming current A memory cell including magnetic materials and heating materials, and methods of programming the memory cell are provided. The memory cell includes a free... |
| US-8,237,474 |
Delay line off-state control with power reduction A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output... |
| US-8,237,290 |
Assemblies and multi-chip modules including stacked semiconductor dice
having centrally located, wire bonded... An assembly method that includes providing a first semiconductor device and positioning a second semiconductor device at least partially over the first... |
| US-8,237,254 |
Distributed semiconductor device methods, apparatus, and systems Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be... |
| US-8,237,216 |
Apparatus having a lanthanum-metal oxide semiconductor device Lanthanum-metal oxide dielectrics and methods of fabricating such dielectrics provide an insulating layer in a variety of structures for use in a wide range of... |
| US-8,237,213 |
Memory arrays having substantially vertical, adjacent semiconductor
structures and the formation thereof Memory arrays and methods of their formation are disclosed. One such memory array has memory-cell strings are formed adjacent to separated substantially... |
| US-8,236,899 |
Zwitterionic block copolymers and methods Zwitterionic block copolymers having oppositely charged or chargeable terminal groups, and methods of making and using the same, are disclosed. The zwitterionic... |
| US-8,236,691 |
Method of high aspect ratio plug fill A method of plug fill for high aspect ratio plugs wherein a nucleation layer is formed at a bottom of a via and not on the sidewalls. The plug fill is in the... |
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