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| Patent # | Description |
|---|---|
| US-8,982,631 |
Programming methods and memories Memory devices and programming methods for memories are disclosed, such as those adapted to program a memory using an increasing channel voltage for a first... |
| US-8,982,627 |
Fast programming memory device In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one... |
| US-8,982,625 |
Memory program disturb reduction Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying, during a first... |
| US-8,982,469 |
Lens master devices, lens structures, imaging devices, and methods and
apparatuses of making the same A method and apparatus providing a lens master device and use of the same to form a lens template and/or a lens structure. The method includes obtaining a... |
| US-8,981,463 |
Memory cell array with semiconductor selection device for multiple memory
cells A memory array that includes access devices that are each electrically coupled to more than one memory cell. The memory cells are coupled to the access devices... |
| US-8,981,336 |
Phase change memory cell with self-aligned vertical heater and low
resistivity interface A low resistivity interface material is provided between a self-aligned vertical heater element and a contact region of a selection device. A phase change... |
| US-8,981,334 |
Memory cells having regions containing one or both of carbon and boron Some embodiments include a memory cell having a first electrode, and an intermediate material over and directly against the first electrode. The intermediate... |
| US-8,980,756 |
Methods for device fabrication using pitch reduction Embodiments of a method for device fabrication by reverse pitch reduction flow include forming a first pattern of features above a substrate and forming a... |
| US-8,980,752 |
Method of forming a plurality of spaced features A method of forming a plurality of spaced features includes forming sacrificial hardmask material over underlying material. The sacrificial hardmask material... |
| US-8,980,699 |
Thyristor-based memory cells, devices and systems including the same and
methods for forming the same Semiconductor devices including a plurality of thyristor-based memory cells, each having a cell size of 4F.sup.2, and methods for forming the same are provided.... |
| US-8,977,929 |
Rearranging write data to avoid hard errors This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one... |
| US-8,977,822 |
Memory device and method having on-board processing logic for facilitating
interface with multiple processors,... A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating... |
| US-8,977,809 |
Sharing resources in multi-dice stacks Apparatus, systems, and methods for configuring a plurality of stacked semiconductor dice with unique identifiers and identifying a die in the stack using the... |
| US-8,977,808 |
Mapping between program states and data patterns The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes: programming a group of G... |
| US-8,976,621 |
Continuous page read for memory Subject matter disclosed herein relates to techniques to read memory in a continuous fashion. |
| US-8,976,594 |
Memory read apparatus and methods Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential,... |
| US-8,976,582 |
Analog sensing of memory cells in a solid-state memory device A memory device that includes a sample and hold circuit coupled to a bit line. The sample and hold circuit stores a target threshold voltage for a selected... |
| US-8,976,570 |
Method, system, and device for phase change memory switch wall cell with
approximately horizontal electrode contact Embodiments disclosed herein may include depositing a storage component material over and/or in a trench in a dielectric material, including depositing the... |
| US-8,976,566 |
Electronic devices, memory devices and memory arrays Some embodiments include electronic devices having two capacitors connected in series. The two capacitors share a common electrode. One of the capacitors... |
| US-8,975,908 |
Electrical test probe and probe assembly with improved probe tip An embodiment disperses a force acting on a border portion between an extending portion and a pedestal portion or a reinforcing member to prevent breakage of a... |
| US-8,975,745 |
Packaged microelectronic devices recessed in support member cavities, and
associated methods Packaged microelectronic devices recessed in support member cavities, and associated methods, are disclosed. Method in accordance with one embodiment includes... |
| US-8,975,614 |
Wavelength converters for solid state lighting devices, and associated
systems and methods Wavelength converters for solid state lighting devices, and associated systems and methods. A system in accordance with a particular embodiment includes a solid... |
| US-8,975,603 |
Systems and methods for plasma doping microfeature workpieces Systems and methods for plasma doping microfeature workpieces are disclosed herein. In one embodiment, a method of implanting boron ions into a region of a... |
| US-8,975,148 |
Memory arrays and methods of forming memory cells Some embodiments include methods of forming memory cells. A stack includes ovonic material over an electrically conductive region. The stack is patterned into... |
| US-8,974,678 |
Methods using block co-polymer self-assembly for sub-lithographic
patterning Block copolymers can be self-assembled and used in methods as described herein for sub-lithographic patterning, for example. The block copolymers can be diblock... |
| US-8,974,655 |
Methods of planarization and electro-chemical mechanical polishing
processes A method of removing a material from a surface includes providing a substrate comprising a material having a surface, contacting the surface with a polishing... |
| US-8,972,632 |
Asymmetric chip-to-chip interconnect Methods and apparatus to transfer data between a first device and a second device, is disclosed. An apparatus according to various embodiments may comprise a... |
| US-8,971,127 |
NAND flash memory programming A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a... |
| US-8,971,126 |
Charge loss compensation methods and apparatus Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss... |
| US-8,971,125 |
Erase operations with erase-verify voltages based on where in the erase
operations an erase cycle occurs Memory devices and methods of erasing the memory devices are disclosed. One such method includes performing an erase cycle of an erase operation on a plurality... |
| US-8,971,124 |
Apparatuses and methods for performing logical operations using sensing
circuitry The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an... |
| US-8,971,121 |
Method and devices for memory cell erasure with a programming monitor of
reference cells Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase... |
| US-8,971,117 |
Apparatus and methods for applying a non-zero voltage differential across
a memory cell not involved in an... Apparatus and methods for applying a non-zero voltage differential across a memory cell not involved in an access operation can facilitate improved data... |
| US-8,971,112 |
Method of programming a multi-level memory device Method of programming a multi-level memory cell may include transferring one or more values between an auxiliary latch of the multi-level memory cell and a most... |
| US-8,971,105 |
Methods and apparatuses for controlling memory write sequences Subject matter disclosed herein relates to memory operations regarding changing an order of program bits to be programmed into a memory array. |
| US-8,971,104 |
Memory programming to reduce thermal disturb A resistive memory array is programmed such that particular adjacent pairs of memory cells along a bit line having a back-to-back relationship are programmed... |
| US-8,971,086 |
Capacitorless DRAM on bulk silicon A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of... |
| US-8,970,034 |
Semiconductor assemblies and structures Semiconductor assemblies, structures, and methods of fabrication are disclosed. A coating is formed on an electrically conductive pillar. The coating, which may... |
| US-8,969,928 |
Transistors having a control gate and one or more conductive structures Transistors having a dielectric over a semiconductor, a control gate over the dielectric at a particular level, and one or more conductive structures over the... |
| US-8,969,899 |
Method for forming a light conversion material A method and system for manufacturing a light conversion structure for a light emitting diode (LED) is disclosed. The method includes forming a transparent,... |
| US-8,969,217 |
Methods of treating semiconductor substrates, methods of forming openings
during semiconductor fabrication, and... Some embodiments include methods of treating semiconductor substrates. The substrates may be exposed to one or more conditions that vary continuously. The... |
| US-8,969,214 |
Methods of forming a pattern on a substrate A method of forming a pattern on a substrate includes forming spaced first features derived from a first lithographic patterning step. Sidewall spacers are... |
| US-8,969,154 |
Methods for fabricating semiconductor device structures and arrays of
vertical transistor devices A semiconductor device structure is disclosed. The semiconductor device structure includes a mesa extending above a substrate. The mesa has a channel region... |
| US-8,966,409 |
Methods of forming a mask and methods of correcting intra-field variation
across a mask design used in... A method of forming a mask includes creating a difference map between a desired intra-field pattern that is to be formed on substrates and an intra-field... |
| US-8,966,352 |
Memory controller supporting rate-compatible punctured codes and
supporting block codes Apparatus and methods store data in a non-volatile solid state memory device according to a rate-compatible code, such as a rate-compatible convolutional code... |
| US-8,966,335 |
Method for performing error corrections of digital information codified as
a symbol sequence A method and system for making error corrections on digital information coded as symbol sequences, for example digital information stored in electronic memory... |
| US-8,966,231 |
Modifying commands The present disclosure includes methods, devices, modules, and systems for modifying commands. One device embodiment includes a memory controller including a... |
| US-8,966,165 |
Translation layer in a solid state storage device Solid state storage devices and methods for flash translation layers are disclosed. In one such translation layer, a sector indication is translated to a memory... |
| US-8,966,135 |
Methods of providing access to I/O devices A method of providing one or more computing devices with access to a plurality of resources. The plurality of resources are provided by at least one physical... |
| US-8,964,496 |
Apparatuses and methods for performing compare operations using sensing
circuitry The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can... |
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