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Patent # Description
US-8,582,356 Providing a ready-busy signal from a non-volatile memory device to a memory controller
A common standard may be used for both dynamic random access memories and non volatile memories, despite the fact that the non-volatile memory generally needs...
US-8,582,350 Capacitor-less memory cell, device, system and method of making same
A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of...
US-8,582,005 Method, apparatus and system providing adjustment of pixel defect map
A method, apparatus and system that allows for the identification of defective pixels, for example, defective pixel clusters, in an imager device. The method,...
US-8,581,651 Duty cycle based phase interpolators and methods for use
Duty cycle based phase interpolators, and methods for implementing duty cycle based phase interpolators are disclosed. One such phase interpolator includes a...
US-8,581,630 Signal driver circuit having adjustable output voltage for a high logic level output signal
A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured...
US-8,581,387 Through wire interconnect (TWI) having bonded connection and encapsulating polymer layer
A through wire interconnect for a semiconductor substrate includes a via extending through the semiconductor substrate from a first side to a second side...
US-8,581,352 Electronic devices including barium strontium titanium oxide films
Apparatus and methods of forming the apparatus include a dielectric layer containing barium strontium titanium oxide layer, an erbium-doped barium strontium...
US-8,581,224 Memory cells
Some embodiments include memory cells which contain, in order; a first electrode material, a first metal oxide material, a second metal oxide material, and a...
US-8,580,666 Methods of forming conductive contacts
Methods for forming memory devices and integrated circuitry, for example, DRAM (dynamic random access memory) circuitry, structures and devices resulting from...
US-8,580,645 Memory devices and methods of forming memory devices
Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes...
US-8,580,593 Epitaxial formation structures and associated methods of manufacturing solid state lighting devices
Epitaxial formation structures and associated methods of manufacturing solid state lighting ("SSL") devices with target thermal expansion characteristics are...
US-8,580,158 Methods of removing silicon dioxide
Some embodiments include methods of removing silicon dioxide in which the silicon dioxide is exposed to a mixture that includes activated hydrogen and at least...
US-8,578,591 Method for manufacturing a stacked device conductive path connectivity
Various embodiments include apparatus and methods having circuitry to test continuity of conductive paths coupled to dice arranged in a stack. In at least one...
US-8,578,331 Command line output redirection
In one embodiment the invention provides a method to provide command line utility output to an application without the need of temporary files. The method...
US-8,578,244 Programming error correction code into a solid state memory device with varying bits per cell
Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to...
US-8,578,208 Determining location of error detection data
Methods, devices, and systems for determining location of error detection data are described. One method for operating a memory unit having a bad group of...
US-8,578,115 Temporary mirroring, logical segregation, and redundant programming or addressing for solid state drive operation
The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes mirroring programming operations such that...
US-8,578,095 Hierarchical memory architecture using a concentrator device
A hierarchical memory storage using a concentrator device that is located between a processor and memory devices. The concentrator device includes a page...
US-8,578,070 Host controller
The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes...
US-8,576,646 Control voltage tracking circuits, methods for recording a control voltage for a clock synchronization circuit...
Memories, clock synchronization circuits, clock synchronization controller circuits, and methods for setting a voltage controlled delay of a clock...
US-8,576,632 Methods, devices, and systems for dealing with threshold voltage change in memory devices
The present disclosure includes methods, devices, and systems for dealing with threshold voltage change in memory devices. A number of embodiments include an...
US-8,576,631 Techniques for sensing a semiconductor memory device
Techniques for sensing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the technique(s) may be realized as a semiconductor...
US-8,576,627 Memory array with inverted data-lines pairs
At least one data-line pair has a first data line aligned with a first column of memory cells and a second data line aligned with a second column of memory...
US-8,575,958 Programmable on-chip logic analyzer apparatus, systems, and methods
Apparatus, systems, and methods disclosed herein may cause an event trigger state machine associated with a programmable on-chip logic analyzer (POCLA) to...
US-8,575,716 Integrated circuit devices and methods of forming memory array and peripheral circuitry isolation
A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of...
US-8,575,040 Low temperature process for polysilazane oxidation/densification
Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are...
US-8,575,032 Methods of forming a pattern on a substrate
A method of forming a pattern on a substrate includes forming a repeating pattern of four first lines elevationally over an underlying substrate. A repeating...
US-8,574,954 Phase change memory structures and methods
Methods, devices, and systems associated with phase change material memory are described herein. In one or more embodiments, a method of forming a phase change...
US-8,572,466 Apparatuses, systems, devices, and methods of replacing at least partially non-functional portions of memory
Subject matter disclosed herein relates to determining that a portion of a memory is at least partially non-functional, replacing the portion of at least...
US-8,572,361 Configuration of a multilevel flash memory device
A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the...
US-8,572,358 Meta predictor restoration upon detecting misprediction
Methods and apparatus for restoring a meta predictor system upon detecting a branch or binary misprediction, are disclosed. An example apparatus may include a...
US-8,572,333 Non-volatile memory with extended operating temperature range
A method and apparatus are described for measuring a temperature within a non-volatile memory and refreshing at least a portion of the non-volatile memory when...
US-8,572,292 Command interface systems and methods
Apparatus, systems, and methods are disclosed that operate within a memory to execute internal commands, to suspend the execution of commands during a transfer...
US-8,570,860 Redundant signal transmission
Signal transmission apparatus, systems, and methods are disclosed. In various embodiments, a signal transmission system includes a transmission network having...
US-8,570,826 Memory device having data paths facilitating array/contact consolidation and/or swapping
Apparatus and methods are disclosed, such as those involving array/port consolidation and/or swapping. One such apparatus includes a plurality of port pads...
US-8,570,807 NAND architecture memory with voltage sensing
A NAND architecture non-volatile memory voltage sensing data read/verify process and sense amplifier has been described that senses data in floating gate or...
US-8,570,798 Electronic devices formed of two or more substrates connected together, electronic systems comprising...
Electronic devices comprise a first substrate and a second substrate. The first substrate comprises circuitry including a plurality of conductive traces at...
US-8,570,613 Lithographic printing system with placement corrections
The technology disclosed relates to methods and devices that compensate for displacements in a pattern or deformations of a workpiece. In particular, this...
US-8,570,535 Pattern generators, calibration systems and methods for patterning workpieces
A pattern generator includes: a writing tool and a calibration system. The writing tool is configured to generate a pattern on a workpiece arranged on a stage....
US-8,570,084 Circuits and methods for clock signal duty-cycle correction
Duty-cycle correction circuits, clock distribution networks, and methods for correcting duty-cycle distortion are disclosed, including methods and apparatus for...
US-8,570,081 Fast measurement initialization for memory
Systems and methods for synchronization of clock signals are disclosed. In a feedback system such as a delay-lock loop circuit, delays to be applied can be...
US-8,570,063 Methods and apparatuses including an adjustable termination impedance ratio
Methods of adjusting a centerline voltage of a data signal are described, along with apparatuses to adjust the centerline voltage. In one such method, portions...
US-8,569,893 Self-aligned, integrated circuit contact
This document discusses, among other things, example systems including integrated circuit contacts configured to reduce the likelihood of shorting to unrelated...
US-8,569,891 Forming array contacts in semiconductor memories
Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks...
US-8,569,863 Voltage-controlled semiconductor inductor and method
A voltage-controlled semiconductor inductor and method is provided. According to various embodiments, the voltage-controlled inductor includes a conductor...
US-8,569,831 Integrated circuit arrays and semiconductor constructions
Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting...
US-8,569,734 Forming resistive random access memories together with fuse arrays
A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same...
US-8,569,681 Ambient infrared detection in solid state sensors
A solid state imaging device includes an array of active pixels and an infrared cut filter formed over the sensor. Optionally, a slot in the infrared cut filter...
US-8,569,167 Methods for forming a semiconductor structure
Methods of forming a Ni material on a bond pad are disclosed. The methods include forming a dielectric material over a bond pad, forming an opening within the...
US-8,569,161 Semiconductor device with copper wirebond sites and methods of making same
Semiconductor devices with external wirebond sites that include copper and methods for fabricating such semiconductor devices are disclosed. One embodiment of a...
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