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Patent # Description
US-8,289,806 Multiple device apparatus, systems, and methods
Apparatus, systems, and methods are disclosed that operate to generate a clock signal in a die in a stack and to receive the clock signal in another die in the...
US-8,289,799 Power source and power source control circuit
Power sources, backup power circuits, power source control circuits, data storage devices, and methods relating to controlling application of power to a node...
US-8,289,796 Sense amplifier having loop gain control
Memories, sense amplifiers, and methods for amplifying a current input are disclosed, including a sense amplifier including a bias circuit configured to provide...
US-8,289,790 Memory repair systems and methods for a memory having redundant memory
Memories, memory repair logic, and methods for repairing a memory having redundant memory are disclosed. One such memory includes programmable elements...
US-8,289,779 Memory cell sensing device equipped with a ramp voltage generator using a digital-to-analog converter (DAC) and...
The present disclosure includes methods, devices, and systems for sensing memory cells. One or more embodiments include providing an output of a first counter...
US-8,289,776 Expanded programming window for non-volatile multilevel memory cells
Embodiments of the present disclosure provide methods, devices, modules, and systems for utilizing an expanded programming window for non-volatile multilevel...
US-8,289,772 Memory with correlated resistance
Methods, systems, and devices include a system for sequentially writing to a data locations coupled to one another in series. The system includes a plurality of...
US-8,289,767 Providing a ready-busy signal from a non-volatile memory device to a memory controller
A common standard may be used for both dynamic random access memories and non-volatile memories, despite the fact that the non-volatile memory generally needs...
US-8,289,763 Memory arrays
Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines...
US-8,289,760 Multi-mode memory device and method having stacked memory dice, a logic die and a command processing circuit...
Memory device systems, systems and methods are disclosed, such as those involving a plurality of stacked memory device dice and a logic die connected to each...
US-8,289,428 Method, apparatus and system providing imager vertical binning and scaling using column parallel sigma-delta...
A method, apparatus and system are disclosed for digitizing a plurality of analog pixel signals of a pixel array in a manner which produces a digital signal...
US-8,289,062 Analog delay lines and adaptive biasing
Examples of analog delay lines and analog delay systems, such as DLLs incorporating analog delay lines are described, as are circuits and methods for adaptive...
US-8,289,059 Circuits and methods for clock signal duty-cycle correction
Duty-cycle correction circuits, clock distribution networks, and methods for correcting duty-cycle distortion are disclosed, including methods and apparatus for...
US-8,289,050 Switching circuits, latches and methods
Switching circuits, latches and methods are provided, such as those that may respond to an input signal that transitions from a first binary level to a second...
US-8,288,874 Stackable semiconductor assemblies and methods of manufacturing such assemblies
Stacked semiconductor devices and assemblies including attached lead frames are disclosed herein. One embodiment of a method of manufacturing a semiconductor...
US-8,288,867 Semiconductor constructions
Some embodiments include semiconductor processing methods in which a copper barrier is formed to be laterally offset from a copper component, and in which...
US-8,288,859 Semiconductor device packages including a semiconductor device and a redistribution element
A method for fabricating a chip-scale board-on-chip substrate, or redistribution element, includes forming conductive planes on opposite sides of a substrate. A...
US-8,288,832 Semiconductor devices including a layer of polycrystalline silicon having a smooth morphology
A method for controlling the morphology of deposited silicon on a layer of silicon dioxide and semiconductor devices incorporating such deposited silicon are...
US-8,288,818 Devices with nanocrystals and methods of formation
Devices can be fabricated using a method of growing nanoscale structures on a semiconductor substrate. According to various embodiments, nucleation sites are...
US-8,288,817 Semiconductor constructions for transistor gates and NAND cell units
Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at...
US-8,288,811 Fortification of charge-storing material in high-K dielectric environments and resulting apparatuses
Memories, systems, and methods for forming memory cells are disclosed. One such memory cell includes a charge storage node that includes nanodots over a tunnel...
US-8,288,809 Zirconium-doped tantalum oxide films
Dielectric layers containing a zirconium-doped tantalum oxide layer, where the zirconium-doped tantalum oxide layer is formed of one or more monolayers of...
US-8,288,795 Thyristor based memory cells, devices and systems including the same and methods for forming the same
Semiconductor devices including a plurality of thyristor-based memory cells, each having a cell size of 4F.sup.2, and methods for forming the same are provided....
US-8,288,264 Scalable multi-function and multi-level nano-crystal non-volatile memory device
A multi-functional and multi-level memory cell comprises a tunnel layer formed over a substrate. In one embodiment, the tunnel layer comprises two layers such...
US-8,288,213 Methods of forming memory arrays
Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces....
US-8,288,083 Methods of forming patterned masks
Some embodiments include methods in which spaced-apart first features are formed from a first material having a reflow temperature. Second material is formed...
US-8,286,883 System and method for updating read-only memory in smart card memory modules
A storage device contains a smart-card device and a memory device, both connected to a controller. The storage device may be used in the same manner as a...
US-8,286,066 Non-volatile memory with bi-directional error correction protection
Embodiments of the present disclosure provide methods and apparatuses related to NVM devices with bi-directional error correction protection. In some...
US-8,285,976 Method and apparatus for predicting branches using a meta predictor
A branch predicting apparatus is disclosed that reduces branch mispredictions in a processor. The branch prediction apparatus includes a base misprediction...
US-8,284,623 Electronic device comprising non volatile memory cells and corresponding programming method
A device with non volatile memory cells, with optimized programming, of the type comprising a sector of matrix memory cells organized in rows and columns, with...
US-8,284,617 Circuits, devices, systems, and methods of operation for capturing data signals
Embodiments of the invention describe driving data onto a bus. The embodiments include a data driver circuit having a data capture circuit coupled to the bus....
US-8,284,616 Trench memory structure operation
Memory cells utilizing dielectric charge carrier trapping sites formed in trenches provide for non-volatile storage of data. The memory cells of the various...
US-8,284,613 Semiconductor memory device having bit line pre-charge unit separated from data register
A semiconductor memory device is described that can, in certain embodiments, reduce a delay in access time and/or an area of a memory cell array. In one or more...
US-8,283,961 Delay line circuit
Delay circuitry is described that includes clock mixing circuitry to provide a selectable propagation time. Output signals from the mixing circuitry are...
US-8,283,950 Delay lines, amplifier systems, transconductance compensating systems and methods of compensating
Embodiments of delay lines may include a plurality of delay stages coupled to each other in series from a first stage to a last stage. Each delay stage may...
US-8,283,946 Signaling systems, preamplifiers, memory devices and methods
Signaling systems, preamplifiers, memory devices and methods are disclosed, such as a signaling system that includes a transmitter configured to receive a first...
US-8,283,785 Interconnect regions
Some embodiments include interconnect regions. The regions may contain, along a cross section, a closed-shape interior region having an electrically conductive...
US-8,283,761 Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged...
US-8,283,744 Molybdenum-doped indium oxide structures and methods
Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain indium and monolayers that contain...
US-8,283,710 Low dark current image sensors with epitaxial SiC and/or carbonated channels for array transistors
A pixel cell having a substrate with a isolation channel formed of higher carbon concentrate such as SiC or carbonated silicon. The channel comprising SiC or...
US-8,283,708 Semiconductor devices and methods of forming semiconductor devices having diffusion regions of reduced width
Semiconductor devices and methods for forming semiconductor devices are provided, including semiconductor devices that comprise one or more diffusion region in...
US-8,283,648 Resistance variable memory cell
Methods, devices, and systems associated with phase change memory structures are described herein. One or more embodiments of the present disclosure can reduce...
US-8,283,503 Methods of forming a tellurium alkoxide and methods of forming a mixed halide-alkoxide of tellurium
A method of forming a tellurium alkoxide includes providing a tellurium halide and a non-tellurium alkoxide in a liquid organic solvent. The liquid organic...
US-8,283,259 Methods of removing a metal nitride material
A method of removing a metal nitride material is disclosed. The method comprises forming a semiconductor device structure comprising an exposed metal material...
US-8,283,258 Selective wet etching of hafnium aluminum oxide films
Methods and etchant compositions for wet etching to selectively remove a hafnium aluminum oxide (HfAlO.sub.x) material relative to silicon oxide (SiO.sub.x) are...
US-8,283,257 Systems and methods for oscillating exposure of a semiconductor workpiece to multiple chemistries
Systems and methods for oscillating exposure of a semiconductor workpiece to multiple chemistries are disclosed. A method in accordance with one embodiment...
US-8,283,236 Methods of forming capacitors
Some embodiments include capacitors. The capacitors may include container-shaped storage node structures that have, along a cross-section, a pair of...
US-8,283,203 Methods utilizing microwave radiation during formation of semiconductor constructions
Some embodiments include methods in which microwave radiation is used to activate dopant and/or increase crystallinity of semiconductor material during...
US-8,283,198 Resistive memory and methods of processing resistive memory
Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include forming...
US-8,283,112 Photoresist processing methods
A photoresist processing method includes treating a substrate with a sulfur-containing substance. A positive-tone photoresist is applied on and in contact with...
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