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Patent # Description
US-8,252,697 Zinc-tin oxide thin-film transistors
Methods of forming transparent zinc-tin oxide structures are described. Devices that include transparent zinc-tin oxide structures as at least one of a channel...
US-8,252,658 Methods of etching trenches into silicon of a semiconductor substrate, methods of forming trench isolation in...
A method of etching trenches into silicon of a semiconductor substrate includes forming a mask over silicon of a semiconductor substrate, with the mask...
US-8,252,646 Peripheral gate stacks and recessed array gates
Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic...
US-8,252,622 Phase change current density control structure
A phase change memory element and method of forming the same. The memory element includes first and second electrodes. A first layer of phase change material is...
US-8,252,194 Methods of removing silicon oxide
A method of removing at least a portion of a silicon oxide material is disclosed. The silicon oxide is removed by exposing a semiconductor structure comprising...
US-8,252,119 Microelectronic substrate cleaning systems with polyelectrolyte and associated methods
Several embodiments of cleaning systems using polyelectrolyte and various associated methods for cleaning microelectronic substrates are disclosed herein. One...
US-8,250,418 Test mode for parallel load of address dependent data to enable loading of desired data backgrounds
One or more embodiments of the invention enable a memory device to load its memory array with desired background data, such as to reduce total test time and...
US-8,250,417 Method for detecting flash program failures
One or more techniques are provided for programming a flash memory device. In one embodiment, the memory device is programmed such that a data pattern written...
US-8,250,328 Apparatus and method for buffered write commands in a memory
Memories, buffered write command circuits, and methods for executing memory commands in a memory. In some embodiments, read commands that are received after...
US-8,250,314 Method and device for checking sector protection information of a non-volatile memory
A non-volatile memory device includes addressable sectors and an ancillary volatile memory array. The ancillary volatile memory array stores protection...
US-8,250,312 Configurable multi-port memory devices and methods
Embodiments of a multi-port memory device may include a plurality of ports and a plurality of memory banks some of which are native to each port and some of...
US-8,250,294 Block management for mass storage
An embodiment of the present invention includes a nonvolatile memory system comprising nonvolatile memory for storing sector information, the nonvolatile memory...
US-8,250,287 Enhanced throughput for serial flash memory, including streaming mode operations
Subject matter disclosed herein may relate to storing a streaming mode enable value in a configuration register, receiving a streaming mode entry signal at a...
US-8,250,282 PCM memories for storage bus interfaces
A memory controller for a phase change memory (PCM) that can be used on a storage bus interface is described. In one example, the memory controller includes an...
US-8,248,881 Method and apparatus for managing behavior of memory devices
A method of managing power consumption by a memory in a memory device includes determining whether the device is powered by a depletable power supply, and if it...
US-8,248,880 Voltage regulators, amplifiers, memory devices and methods
Circuits, devices and methods are provided, such as an amplifier (e.g., a voltage regulator) that includes a feedback circuit that supplies negative feedback...
US-8,248,870 Method and apparatus for synchronizing data from memory arrays
According to one embodiment, a combination is comprised of a plurality of sense amps, each having an input for receiving a clock signal. A data bus is for...
US-8,248,868 Asynchronous/synchronous interface
The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling...
US-8,248,851 System, apparatus, and reading method for NAND memories
A system, apparatus, and method to read a memory cell of a memory device is described. The method includes biasing a drain select line (DSL), a source select...
US-8,247,907 Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using...
Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods are disclosed herein. One embodiment,...
US-8,247,871 1T/0C RAM cell with a wrapped-around gate device structure
A memory device and a method of forming the memory device. The memory device comprises a storage transistor at a surface of a substrate comprising a body...
US-8,247,789 Memory cells and methods of forming memory cells
Some embodiments include a memory cell that contains programmable material sandwiched between first and second electrodes. The memory cell can further include a...
US-8,247,302 Methods of fabricating substrates
A method of fabricating a substrate includes forming spaced first features and spaced second features over a substrate. The first and second features alternate...
US-8,245,176 Integrated circuit apparatus, systems, and methods
High density circuit modules are formed by stacking integrated circuit (IC) chips one above another. Unused input/output (I/O) locations on some of the chips...
US-8,245,100 Error recovery storage along a nand-flash string
Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are...
US-8,245,024 Booting in systems having devices coupled in a chained configuration
The present disclosure includes methods, devices, and systems for booting in systems having devices coupled in a chained configuration. One or more embodiments...
US-8,244,937 Solid state storage device controller with parallel operation mode
Solid state storage devices and methods for operation of solid state storage devices are disclosed. In one such method, a master memory controller is comprised...
US-8,243,544 Reduction of fusible links and associated circuitry on memory dies
The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among...
US-8,243,538 Small unit internal verify read in a memory device
Methods for small unit internal verify read operation and a memory device are disclosed. In one such method, expected data is programmed into a grouping of...
US-8,243,529 Memory device page buffer configuration and methods
Memory devices and methods are described that include communication circuitry between page buffers in a memory array. Examples include communication circuitry...
US-8,243,523 Sensing operations in a memory device
Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a...
US-8,243,521 Method for kink compensation in a memory
This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory...
US-8,243,513 Non-volatile multilevel memory cells with data read of reference cells
Embodiments of the present disclosure provide methods, devices, modules, and systems for non-volatile multilevel memory cell data retrieval with data read of...
US-8,243,506 Phase change memory structures and methods
Methods, devices, and systems associated with phase change memory structures are described herein. One method of forming a phase change memory structure...
US-8,243,497 Phase change memory device with reduced programming disturbance
A Phase Change Memory device with reduced programming disturbance and its operation are described. The Phase Change Memory includes an array with word lines and...
US-8,243,479 On-die anti-resonance structure for integrated circuit
A structure and method for reducing the effects of chip-package resonance in an integrated circuit assembly is described. A series RLC circuit is employed to...
US-8,243,164 Method, apparatus, and system for selecting pixels for automatic white balance processing
A method, apparatus, and system that use a white balance operation. A selecting process is applied to each pixel selected and considered for automatic white...
US-8,242,555 FIN field effect transistor
Methods, devices and systems for a FinFET are provided. One method embodiment includes forming a FinFET by forming a relaxed silicon germanium...
US-8,242,554 Integrated two device non-volatile memory
The non-volatile memory cell is comprised of the series integration of a fixed threshold element and a bistable element. The fixed threshold element is formed...
US-8,242,008 Methods of removing noble metal-containing nanoparticles, methods of forming NAND string gates, and methods of...
Some embodiments include methods of removing noble metal-containing particles from over a substrate. The substrate is exposed to a composition that reduces...
US-8,241,987 Methods of forming capacitors
A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and...
US-8,241,947 Phase change memory elements using energy conversion layers, memory arrays and systems including same, and...
A phase change memory element and method of forming the same. The memory element includes a phase change material layer electrically coupled to first and second...
US-8,241,944 Resistive RAM devices and methods
The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One...
US-8,241,708 Formation of insulator oxide films with acid or base catalyzed hydrolysis of alkoxides in supercritical carbon...
Metal and/or silicon oxides are produced by hydrolysis of alkoxide precursors in the presence of either an acid catalyst or a base catalyst in a supercritical...
US-8,239,725 Data storage with an outer block code and a stream-based inner code
Apparatus and methods store stream-based error recovery data for a memory array, such as a NAND flash array. Conventionally, data is block coded per industry...
US-8,239,636 Bit inversion in memory devices
Bit inversions occurring in memory systems and apparatus are provided. Data is acquired from a source destined for a target. As the data is acquired from the...
US-8,239,629 Hierarchical memory architecture to connect mass storage devices
A hierarchical memory storage using a concentrator device that is located between a processor and memory storage devices to provide a succession of memory...
US-8,239,614 Memory super block allocation
The present disclosure includes methods and devices for memory block selection. In one or more embodiments, a memory controller includes control circuitry...
US-8,239,607 System and method for an asynchronous data buffer having buffer write and read pointers
A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device...
US-8,239,432 Incorporating noise and/or jitter into waveform generation
One or more embodiments are disclosed that involve computer implementable techniques for generating simulate-able waveforms without the need for repeatedly...
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