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Patent # Description
US-8,234,528 Systems and methods for monitoring a memory system
Systems and methods are disclosed herein, including those that operate to monitor a first set of operational parameters associated with a memory vault, to...
US-8,234,527 Method for error test, recordation and repair
In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test....
US-8,234,460 Communication between internal and external processors
Systems, methods of operating a memory device, and methods of arbitrating access to a memory array in a memory device having an internal processor are provided....
US-8,234,439 Fault-tolerant non-volatile integrated circuit memory
Apparatus and methods are disclosed, such as those that store data in a plurality of non-volatile integrated circuit memory devices, such as NAND flash, with...
US-8,233,329 Architecture and method for memory programming
Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is...
US-8,233,322 Multi-partition memory with separated read and algorithm datalines
A multiple partition memory and architecture for concurrent operations reduces circuit overhead by providing a common read sense amplifier and program path for...
US-8,233,318 Phase change memory
The present disclosure includes devices and methods for operating resistance variable memory cells. One or more embodiments include applying a programming...
US-8,233,316 Memory architecture and cell design employing two access transistors
An improved memory array architecture and cell design in which the cell employs two access transistors. In one embodiment, the two access transistors in each...
US-8,232,657 Packaged semiconductor assemblies and methods for manufacturing such assemblies
Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of...
US-8,232,585 JFET devices with PIN gate stacks
Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present...
US-8,232,206 Methods of forming electrical contacts to structures that are at different heights over a substrate relative to...
Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be...
US-8,230,305 Extended single-bit error correction and multiple-bit error detection
Some embodiments include apparatus and methods to prevent at least one of misidentifying and ignoring multiple-bit errors if the multiple-bit errors include a...
US-8,230,274 JTAG controlled self-repair after packaging
An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the...
US-8,230,196 Configurable partitions for non-volatile memory
Example embodiments for configuring a non-volatile memory device may comprise configuring M physical partitions of the non-volatile memory into two or more...
US-8,230,165 Method of storing data on a flash memory device
Methods and apparatus are disclosed, such as those involving a flash memory device. One such method includes storing data on memory cells on a memory block...
US-8,230,158 Memory devices and methods of storing data on a memory device
Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of memory...
US-8,228,743 Memory cells containing charge-trapping zones
Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material...
US-8,228,742 Memory read methods, apparatus, and systems
Some embodiments include first memory cells and a first line used to access the first memory cells, second memory cells and at least one second line used to...
US-8,228,735 Memory array having memory cells coupled between a programmable drain select gate and a non-programmable source...
Memories and their memory arrays are disclosed. One such memory array has a string of series-coupled memory cells, a non-programmable select gate coupled in...
US-8,228,730 Memory cell structures and methods
Memory cell structures and methods are described herein. One or more memory cells include a transistor having a charge storage node, a dielectric material...
US-8,228,725 Memory utilizing oxide nanolaminates
Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a...
US-8,228,717 Spin current generator for STT-MRAM or other spintronics applications
Spin current generators and systems and methods for employing spin current generators. A spin current generator may be configured to generate a spin current...
US-8,227,875 Semiconductor structures resulting from selective oxidation
Methods for selectively oxidizing a semiconductor structure include generating a gas cluster ion beam comprising an oxidizing source gas, directing the gas...
US-8,227,785 Chalcogenide containing semiconductors with chalcogenide gradient
Chalcogenide containing semiconductor devices may be formed with a gradient film between a chalcogenide film and another film. The gradient film may have its...
US-8,227,343 Die stacking with an annular via having a recessed socket
A die stack including a die having an annular via with a recessed conductive socket and methods of forming the die stack provide a structure for use in a...
US-8,227,313 One-transistor composite-gate memory
One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect...
US-8,227,309 Localized compressive strained semiconductor
One aspect of the present subject matter relates to a method for forming strained semiconductor film. According to an embodiment of the method, a crystalline...
US-8,227,305 Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines
A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally...
US-8,226,840 Methods of removing silicon dioxide
Some embodiments include methods of removing silicon dioxide in which the silicon dioxide is exposed to a mixture that includes activated hydrogen and at least...
US-8,226,772 Methods of removing particles from over semiconductor substrates
Some embodiments include methods of removing particles from over surfaces of semiconductor substrates. Liquid may be flowed across the surfaces and the...
US-8,225,745 Chemical vaporizer for material deposition systems and associated methods
System and method for operating a material deposition system are disclosed. In one embodiment, the method can include periodically injecting a precursor into a...
US-8,225,052 Methods for controlling host memory access with memory devices and systems
The present disclosure includes methods for controlling host memory access with a memory device, systems, host controllers and memory devices. One embodiment...
US-8,225,042 Method and apparatus for preventing foreground erase operations in electrically writable memory devices
Methods and systems are provided that may include a nonvolatile memory to store information, where the nonvolatile memory has a memory cache to store data...
US-8,225,033 Data storage system, electronic system, and telecommunications system
A data storage system comprising a plurality of buffers configured to store data, a read pointer to indicate a particular one of the plurality of buffers from...
US-8,225,019 SATA mass storage device emulation on a PCIe interface
A mass storage device, system, and method for operating a mass storage device are disclosed. In one such mass storage device, a host bus adaptor emulates a SATA...
US-8,223,583 Row addressing
Embodiments are provided that include a row decoder, including a row activation path, having a row address converter with an output coupled to an input of a...
US-8,223,574 Techniques for block refreshing a semiconductor memory device
Techniques for block refreshing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method...
US-8,223,561 Data line management in a memory device
Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device...
US-8,223,555 Multiple level program verify in a memory device
Methods for multiple level program verify, memory devices, and memory systems are provided. In one such method, a series of programming pulses are applied to a...
US-8,223,551 Soft landing for desired program threshold voltage
Methods of programming memory cells are disclosed. In at least one embodiment, programming is accomplished by applying a first set of programming pulses to...
US-8,223,549 NAND flash memory programming
A programming method and memory structure for preventing punch-through in a short channel source-side select gate structure includes adjusting voltages on the...
US-8,223,539 GCIB-treated resistive device
The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods...
US-8,223,537 State machine sensing of memory cells
The present disclosure includes methods, devices, modules, and systems for sensing memory cells using a state machine. One method embodiment includes generating...
US-8,222,727 Conductive structures for microfeature devices and methods for fabricating microfeature devices
Methods for fabricating conductive structures on and/or in interposing devices and microfeature devices that are formed using such methods are disclosed herein....
US-8,222,127 Methods of forming structures having nanotubes extending between opposing electrodes and structures including same
A semiconductor structure including nanotubes forming an electrical connection between electrodes is disclosed. The semiconductor structure may include an open...
US-8,222,105 Methods of fabricating a memory device
A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical...
US-8,222,102 Methods of forming field effect transistors, pluralities of field effect transistors, and DRAM circuitry...
A method of forming a field effect transistor includes forming trench isolation material within a semiconductor substrate and on opposing sides of a...
US-8,222,023 Integrated nucleic acid assays
Integrated microfluidic cartridges for nucleic acid extraction, amplification, and detection from clinical samples are disclosed. The devices are single-entry,...
US-8,221,642 Methods for removing dielectric materials
A method for removing a plurality of dielectric films from a supporting substrate by providing a substrate with a dielectric layer overlying another dielectric...
US-8,221,557 Systems and methods for exposing semiconductor workpieces to vapors for through-hole cleaning and/or other...
Systems and methods for exposing semiconductor workpieces to vapors for through-hole cleaning and/or other processes are disclosed. A representative method...
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