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Patent # Description
US-8,230,158 Memory devices and methods of storing data on a memory device
Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of memory...
US-8,228,743 Memory cells containing charge-trapping zones
Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material...
US-8,228,742 Memory read methods, apparatus, and systems
Some embodiments include first memory cells and a first line used to access the first memory cells, second memory cells and at least one second line used to...
US-8,228,735 Memory array having memory cells coupled between a programmable drain select gate and a non-programmable source...
Memories and their memory arrays are disclosed. One such memory array has a string of series-coupled memory cells, a non-programmable select gate coupled in...
US-8,228,730 Memory cell structures and methods
Memory cell structures and methods are described herein. One or more memory cells include a transistor having a charge storage node, a dielectric material...
US-8,228,725 Memory utilizing oxide nanolaminates
Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a...
US-8,228,717 Spin current generator for STT-MRAM or other spintronics applications
Spin current generators and systems and methods for employing spin current generators. A spin current generator may be configured to generate a spin current...
US-8,227,875 Semiconductor structures resulting from selective oxidation
Methods for selectively oxidizing a semiconductor structure include generating a gas cluster ion beam comprising an oxidizing source gas, directing the gas...
US-8,227,785 Chalcogenide containing semiconductors with chalcogenide gradient
Chalcogenide containing semiconductor devices may be formed with a gradient film between a chalcogenide film and another film. The gradient film may have its...
US-8,227,343 Die stacking with an annular via having a recessed socket
A die stack including a die having an annular via with a recessed conductive socket and methods of forming the die stack provide a structure for use in a...
US-8,227,313 One-transistor composite-gate memory
One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect...
US-8,227,309 Localized compressive strained semiconductor
One aspect of the present subject matter relates to a method for forming strained semiconductor film. According to an embodiment of the method, a crystalline...
US-8,227,305 Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines
A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally...
US-8,226,840 Methods of removing silicon dioxide
Some embodiments include methods of removing silicon dioxide in which the silicon dioxide is exposed to a mixture that includes activated hydrogen and at least...
US-8,226,772 Methods of removing particles from over semiconductor substrates
Some embodiments include methods of removing particles from over surfaces of semiconductor substrates. Liquid may be flowed across the surfaces and the...
US-8,225,745 Chemical vaporizer for material deposition systems and associated methods
System and method for operating a material deposition system are disclosed. In one embodiment, the method can include periodically injecting a precursor into a...
US-8,225,052 Methods for controlling host memory access with memory devices and systems
The present disclosure includes methods for controlling host memory access with a memory device, systems, host controllers and memory devices. One embodiment...
US-8,225,042 Method and apparatus for preventing foreground erase operations in electrically writable memory devices
Methods and systems are provided that may include a nonvolatile memory to store information, where the nonvolatile memory has a memory cache to store data...
US-8,225,033 Data storage system, electronic system, and telecommunications system
A data storage system comprising a plurality of buffers configured to store data, a read pointer to indicate a particular one of the plurality of buffers from...
US-8,225,019 SATA mass storage device emulation on a PCIe interface
A mass storage device, system, and method for operating a mass storage device are disclosed. In one such mass storage device, a host bus adaptor emulates a SATA...
US-8,223,583 Row addressing
Embodiments are provided that include a row decoder, including a row activation path, having a row address converter with an output coupled to an input of a...
US-8,223,574 Techniques for block refreshing a semiconductor memory device
Techniques for block refreshing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method...
US-8,223,561 Data line management in a memory device
Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device...
US-8,223,555 Multiple level program verify in a memory device
Methods for multiple level program verify, memory devices, and memory systems are provided. In one such method, a series of programming pulses are applied to a...
US-8,223,551 Soft landing for desired program threshold voltage
Methods of programming memory cells are disclosed. In at least one embodiment, programming is accomplished by applying a first set of programming pulses to...
US-8,223,549 NAND flash memory programming
A programming method and memory structure for preventing punch-through in a short channel source-side select gate structure includes adjusting voltages on the...
US-8,223,539 GCIB-treated resistive device
The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods...
US-8,223,537 State machine sensing of memory cells
The present disclosure includes methods, devices, modules, and systems for sensing memory cells using a state machine. One method embodiment includes generating...
US-8,222,727 Conductive structures for microfeature devices and methods for fabricating microfeature devices
Methods for fabricating conductive structures on and/or in interposing devices and microfeature devices that are formed using such methods are disclosed herein....
US-8,222,127 Methods of forming structures having nanotubes extending between opposing electrodes and structures including same
A semiconductor structure including nanotubes forming an electrical connection between electrodes is disclosed. The semiconductor structure may include an open...
US-8,222,105 Methods of fabricating a memory device
A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical...
US-8,222,102 Methods of forming field effect transistors, pluralities of field effect transistors, and DRAM circuitry...
A method of forming a field effect transistor includes forming trench isolation material within a semiconductor substrate and on opposing sides of a...
US-8,222,023 Integrated nucleic acid assays
Integrated microfluidic cartridges for nucleic acid extraction, amplification, and detection from clinical samples are disclosed. The devices are single-entry,...
US-8,221,642 Methods for removing dielectric materials
A method for removing a plurality of dielectric films from a supporting substrate by providing a substrate with a dielectric layer overlying another dielectric...
US-8,221,557 Systems and methods for exposing semiconductor workpieces to vapors for through-hole cleaning and/or other...
Systems and methods for exposing semiconductor workpieces to vapors for through-hole cleaning and/or other processes are disclosed. A representative method...
US-8,218,898 Method and apparatus providing noise reduction while preserving edges for imagers
A method of reducing noise in an image including steps for obtaining a first value for a target pixel, obtaining a respective second value for each neighboring...
US-8,218,385 Current mode data sensing and propagation using voltage amplifier
A method and a circuit for current mode data sensing and propagation by using voltage amplifier are provided. Example embodiments may include providing an...
US-8,218,357 Spin torque transfer cell structure utilizing field-induced antiferromagnetic or ferromagnetic coupling
A magnetic memory cell including a soft magnetic layer and a coupling layer, and methods of operating the memory cell are provided. The memory cell includes a...
US-8,218,348 Memory devices having strings of series-coupled memory cells selectively coupled to different bit lines
Memory devices where ends of series-coupled strings of memory cells are selectively coupled to different bit lines may facilitate increased memory densities,...
US-8,217,705 Voltage switching in a memory device
Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in...
US-8,217,695 Fast measurement initialization for memory
Systems and methods for synchronization of clock signals are disclosed. In a feedback system such as a delay-lock loop circuit, delays to be applied can be...
US-8,217,694 Method and apparatus for synchronizing with a clock signal
Clock synchronization and skew adjustment circuits that utilize differing unit delay elements in their delay lines in either a graduated or a stepped unit time...
US-8,217,557 Solid state lights with thermosiphon liquid cooling structures and methods
A solid state lighting (SSL) device with a solid state emitter (SSE) being partially exposed in a channel loop, and methods of making and using such SSLs. The...
US-8,217,510 Semiconductor module system having stacked components with encapsulated through wire interconnects (TWI)
A semiconductor module system includes a module substrate and first and second semiconductor components stacked on the module substrate. The stacked...
US-8,217,508 Method of packaging integrated circuit devices using preformed carrier
Disclosed is a method of packaging integrated circuit devices using a preformed carrier. In one illustrative embodiment, the method includes providing a carrier...
US-8,217,505 Packaged IC device comprising an embedded flex circuit on leadframe, and methods of making same
A device is disclosed which includes a flexible material including at least one conductive wiring trace, a first die including at least an integrated circuit,...
US-8,217,465 Semiconductor constructions
In some embodiments, an opening is formed through a first material, and sidewall topography of the opening is utilized to form a pair of separate anistropically...
US-8,217,441 Semiconductor constructions including gate arrays formed on partial SOI substrate
The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology...
US-8,217,439 DRAM unit cells, capacitors, methods of forming DRAM unit cells, and methods of forming capacitors
Some embodiments include methods of forming capacitors. A first capacitor storage node may be formed within a first opening in a first sacrificial material. A...
US-8,216,943 Epitaxial growth method
Epitaxial growth methods and devices are described that include a textured surface on a substrate. Geometry of the textured surface provides a reduced lattice...
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