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Patent # Description
US-8,221,642 Methods for removing dielectric materials
A method for removing a plurality of dielectric films from a supporting substrate by providing a substrate with a dielectric layer overlying another dielectric...
US-8,221,557 Systems and methods for exposing semiconductor workpieces to vapors for through-hole cleaning and/or other...
Systems and methods for exposing semiconductor workpieces to vapors for through-hole cleaning and/or other processes are disclosed. A representative method...
US-8,218,898 Method and apparatus providing noise reduction while preserving edges for imagers
A method of reducing noise in an image including steps for obtaining a first value for a target pixel, obtaining a respective second value for each neighboring...
US-8,218,385 Current mode data sensing and propagation using voltage amplifier
A method and a circuit for current mode data sensing and propagation by using voltage amplifier are provided. Example embodiments may include providing an...
US-8,218,357 Spin torque transfer cell structure utilizing field-induced antiferromagnetic or ferromagnetic coupling
A magnetic memory cell including a soft magnetic layer and a coupling layer, and methods of operating the memory cell are provided. The memory cell includes a...
US-8,218,348 Memory devices having strings of series-coupled memory cells selectively coupled to different bit lines
Memory devices where ends of series-coupled strings of memory cells are selectively coupled to different bit lines may facilitate increased memory densities,...
US-8,217,705 Voltage switching in a memory device
Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in...
US-8,217,695 Fast measurement initialization for memory
Systems and methods for synchronization of clock signals are disclosed. In a feedback system such as a delay-lock loop circuit, delays to be applied can be...
US-8,217,694 Method and apparatus for synchronizing with a clock signal
Clock synchronization and skew adjustment circuits that utilize differing unit delay elements in their delay lines in either a graduated or a stepped unit time...
US-8,217,557 Solid state lights with thermosiphon liquid cooling structures and methods
A solid state lighting (SSL) device with a solid state emitter (SSE) being partially exposed in a channel loop, and methods of making and using such SSLs. The...
US-8,217,510 Semiconductor module system having stacked components with encapsulated through wire interconnects (TWI)
A semiconductor module system includes a module substrate and first and second semiconductor components stacked on the module substrate. The stacked...
US-8,217,508 Method of packaging integrated circuit devices using preformed carrier
Disclosed is a method of packaging integrated circuit devices using a preformed carrier. In one illustrative embodiment, the method includes providing a carrier...
US-8,217,505 Packaged IC device comprising an embedded flex circuit on leadframe, and methods of making same
A device is disclosed which includes a flexible material including at least one conductive wiring trace, a first die including at least an integrated circuit,...
US-8,217,465 Semiconductor constructions
In some embodiments, an opening is formed through a first material, and sidewall topography of the opening is utilized to form a pair of separate anistropically...
US-8,217,441 Semiconductor constructions including gate arrays formed on partial SOI substrate
The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology...
US-8,217,439 DRAM unit cells, capacitors, methods of forming DRAM unit cells, and methods of forming capacitors
Some embodiments include methods of forming capacitors. A first capacitor storage node may be formed within a first opening in a first sacrificial material. A...
US-8,216,943 Epitaxial growth method
Epitaxial growth methods and devices are described that include a textured surface on a substrate. Geometry of the textured surface provides a reduced lattice...
US-8,216,939 Methods of forming openings
Some embodiments include methods of forming openings. For instance, a construction may have a material over a plurality of electrically conductive lines. A...
US-8,216,935 Methods of forming transistor gate constructions, methods of forming NAND transistor gate constructions, and...
A method of forming a transistor gate construction includes forming a gate stack comprising a sacrificial material received over conductive gate material. The...
US-8,216,911 Methods for etching doped oxides in the manufacture of microfeature devices
Methods for selectively etching doped oxides in the manufacture of microfeature devices are disclosed herein. An embodiment of one such method for etching...
US-8,216,832 Sanitary swab collection system, microfluidic assay device, and methods for diagnostic assays
Biohazard specimen collection containers are provided with an external disposable skin, that is stripped away and discarded after the biohazardous specimen is...
US-8,216,377 Method and system for binding halide-based contaminants
A method and apparatus are presented for reducing halide-based contamination within deposited titanium-based thin films. Halide adsorbing materials are utilized...
US-8,214,672 Method and systems for power consumption management of a pattern-recognition processor
Disclosed are methods and devices, among which is a device that includes a pattern-recognition processor. In some embodiments, the pattern-recognition processor...
US-8,213,233 Reduction of quick charge loss effect in a memory device
Methods for reducing quick charge loss effects, methods for programming, memory devices, memory devices, and memory systems are disclosed. In one such method, a...
US-8,213,226 Vertical transistor memory cell and array
A semiconductor device along with circuits including the same and methods of operating the same are described. The device includes an electrically floating body...
US-8,213,225 Methods, devices, and systems relating to memory cells having a floating body
Methods, devices, and systems are disclosed relating to a memory cell having a floating body. A memory cell includes a transistor comprising a drain and a...
US-8,212,906 Skimmed charge capture and charge packet removal for increased effective pixel photosensor full well capacity
An imaging device having pixels that store charge from a photosensor under at least one storage gate during a sampling period. A driver used to operate the at...
US-8,212,900 Method and apparatus providing color interpolation in color filter arrays using edge detection and correction terms
A method and apparatus for color plane interpolation are provided which interpolates the color values of pixels differently depending on an edge direction and...
US-8,212,642 Transponder system
The invention relates to a transponder system for the contactless inductive power transmission of a stationary part having at least one read coil (2) disposed...
US-8,212,348 Techniques for packaging multiple device components
Techniques for fabricating multiple device components. Specifically, techniques for fabricating a stacked package comprising at least one I/C module and a...
US-8,212,281 3-D and 3-D schottky diode for cross-point, variable-resistance material memories, processes of forming same,...
A variable-resistance material memory (VRMM) device includes a container conductor disposed over an epitaxial semiconductive prominence that is coupled to a...
US-8,212,200 Linear distributed pixel differential amplifier having mirrored inputs
A pixel circuit that partially incorporates an associated column amplifier into the pixel circuitry. By incorporating part of a mirrored amplifier into the...
US-8,211,803 Spacer process for on pitch contacts and related structures
Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. Also disclosed are structures associated...
US-8,211,787 Semiconductor processing methods
Some embodiments include methods of forming semiconductor constructions in which a semiconductor material sidewall is along an opening, a protective organic...
US-8,211,778 Forming isolation regions for integrated circuits
A substrate may have active areas at different levels separated by a mask. Along the mask may be a shallow trench isolation. Along the shallow trench isolation...
US-8,211,763 Methods of forming vertical field effect transistors, vertical field effect transistors, and DRAM cells
A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the...
US-8,211,762 Non-volatile memory
Briefly, embodiments of non-volatile memory and embodiments of fabrication thereof are disclosed. For example, a non-volatile memory device having a gate...
US-8,211,743 Methods of forming non-volatile memory cells having multi-resistive state material between conductive electrodes
A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. The...
US-D662,895 Electric contact
US-8,209,521 Methods of indirect register access including automatic modification of a directly accessible address register
Systems and methods are provided for managing access to registers. A system may include a set of direct registers and a set of indirect registers. The indirect...
US-8,209,477 Non-volatile memory device having assignable network identification
Memory devices and methods disclosed such as a memory device having a plurality of memory dies where each die includes a network identification that uniquely...
US-8,209,447 Device to device flow control within a chain of devices
The present disclosure includes methods, devices, and systems for device to device flow control. In one or more embodiments, a system configured for device to...
US-8,208,334 Systems, memories, and methods for refreshing memory arrays
Memories, systems, and methods for refreshing are provided, such as a memory with an array of memory cells divided into sections. Memories include replacement...
US-8,208,322 Non-volatile memory control
Methods and apparatus for use in a memory system having a non-volatile memory and a controller for limiting the number of non-volatile memory arrays from a...
US-8,208,278 Couplings within memory devices
A memory device includes a first bit line coupled to a first source/drain region of a first multiplexer gate, a second bit line coupled to a first source/drain...
US-8,208,277 Memory modules and memory devices having memory device stacks, and method of forming same
A memory module, system and method of forming the same includes a memory module including a plurality of memory devices having a first portion of memory devices...
US-8,208,241 Crystallographically orientated tantalum pentoxide and methods of making same
Methods of forming an oxide are disclosed and include contacting a ruthenium-containing material with a tantalum-containing precursor and contacting the...
US-8,207,768 Digital locked loops and methods with configurable operating parameters
A locked loop may have an adjustable hysteresis and/or a tracking speed that can be programmed by a user of an electronic device containing the locked loop or...
US-8,207,614 Methods for forming arrays of small, closely spaced features
Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can...
US-8,207,599 Method and apparatus for directing molding compound flow and resulting semiconductor device packages
Flow diverting structures for preferentially impeding, redirecting or both impeding and redirecting the flow of flowable encapsulant material, such as molding...
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