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Patent # Description
US-8,283,761 Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged...
US-8,283,744 Molybdenum-doped indium oxide structures and methods
Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain indium and monolayers that contain...
US-8,283,710 Low dark current image sensors with epitaxial SiC and/or carbonated channels for array transistors
A pixel cell having a substrate with a isolation channel formed of higher carbon concentrate such as SiC or carbonated silicon. The channel comprising SiC or...
US-8,283,708 Semiconductor devices and methods of forming semiconductor devices having diffusion regions of reduced width
Semiconductor devices and methods for forming semiconductor devices are provided, including semiconductor devices that comprise one or more diffusion region in...
US-8,283,648 Resistance variable memory cell
Methods, devices, and systems associated with phase change memory structures are described herein. One or more embodiments of the present disclosure can reduce...
US-8,283,503 Methods of forming a tellurium alkoxide and methods of forming a mixed halide-alkoxide of tellurium
A method of forming a tellurium alkoxide includes providing a tellurium halide and a non-tellurium alkoxide in a liquid organic solvent. The liquid organic...
US-8,283,259 Methods of removing a metal nitride material
A method of removing a metal nitride material is disclosed. The method comprises forming a semiconductor device structure comprising an exposed metal material...
US-8,283,258 Selective wet etching of hafnium aluminum oxide films
Methods and etchant compositions for wet etching to selectively remove a hafnium aluminum oxide (HfAlO.sub.x) material relative to silicon oxide (SiO.sub.x) are...
US-8,283,257 Systems and methods for oscillating exposure of a semiconductor workpiece to multiple chemistries
Systems and methods for oscillating exposure of a semiconductor workpiece to multiple chemistries are disclosed. A method in accordance with one embodiment...
US-8,283,236 Methods of forming capacitors
Some embodiments include capacitors. The capacitors may include container-shaped storage node structures that have, along a cross-section, a pair of...
US-8,283,203 Methods utilizing microwave radiation during formation of semiconductor constructions
Some embodiments include methods in which microwave radiation is used to activate dopant and/or increase crystallinity of semiconductor material during...
US-8,283,198 Resistive memory and methods of processing resistive memory
Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include forming...
US-8,283,112 Photoresist processing methods
A photoresist processing method includes treating a substrate with a sulfur-containing substance. A positive-tone photoresist is applied on and in contact with...
US-8,282,999 Spin-on film processing using acoustic radiation pressure
An apparatus and process operate to impose sonic pressure upon a spin-on film liquid mass that exhibits a liquid topography and in a solvent vapor overpressure...
US-8,282,988 Methods of making crystalline tantalum pentoxide
There is disclosed a method of forming crystalline tantalum pentoxide on a ruthenium-containing material having an oxygen-containing surface wherein the...
US-8,281,395 Pattern-recognition processor with matching-data reporting module
Disclosed are methods and devices, among which is a device that includes a pattern-recognition processor. The pattern-recognition processor may include a...
US-8,281,193 Method of protecting a test circuit
A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. The test vector decode circuit is driven by an...
US-8,281,074 Interface device for memory in a stack, storage devices and a processor
Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more...
US-8,281,061 Data conditioning to improve flash memory reliability
Methods and apparatus for managing data storage in memory devices utilizing memory arrays of varying density memory cells. Data can be initially stored in lower...
US-8,279,683 Digit line comparison circuits
A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during...
US-8,279,682 Determining memory page status
The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. One method embodiment includes determining a status...
US-8,279,314 Apparatus and method for eliminating artifacts in active pixel sensor (APS) imagers
An active pixel sensor (APS) that includes circuitry to eliminate artifacts in digital images. The APS includes a comparator for comparing a signal level from a...
US-8,278,993 Clock distribution network
Some embodiments include apparatus and methods having a clock path with a combination of current-mode logic (CML) based and complementary metal-oxide...
US-8,278,965 Inspection apparatus
The inspection apparatus includes a probe having a contact for contacting an electrode of an inspected object and having a built-in heater for correcting...
US-8,278,751 Methods of adhering microfeature workpieces, including a chip, to a support member
Methods and systems for adhering microfeature workpieces to support members are disclosed. A method in accordance with one embodiment of the invention includes...
US-8,278,703 Cross-hair cell based floating body device
A non-planar transistor having floating body structures and methods for fabricating the same are disclosed. In certain embodiments, the transistor includes a...
US-8,278,691 Low power memory device with JFET device structures
There is provided a low power memory device with JFET device structures. Specifically, a low power memory device is provided that includes a plurality memory...
US-8,278,653 Nanoparticle positioning technique
Embodiments of the present invention are generally directed to a method for disposing nanoparticles on a substrate. In one embodiment, a substrate having a...
US-8,278,225 Hafnium tantalum oxide dielectrics
A dielectric layer containing a hafnium tantalum oxide film and a method of fabricating such a dielectric layer produce a dielectric layer for use in a variety...
US-8,278,182 Isolation structure for a memory cell using Al.sub.1O.sub.3 dielectric
The invention provides, in one exemplary embodiment, an isolation gate formed over a substrate for biasing the substrate and providing isolation between...
US-8,278,167 Method and structure for integrating capacitor-less memory cell with logic
Methods for fabricating integrated circuits include fabricating a logic device on a substrate, forming an intermediate semiconductor substrate on a surface of...
US-8,278,131 Method and apparatus for dark current and blooming supression in 4T CMOS imager pixel
A method and apparatus for operating an imager pixel that includes the act of applying a relatively small first polarity voltage and a plurality of pulses of a...
US-8,276,185 Enhanced security memory access method and architecture
A memory device includes: at least one storage area for storing data; a protection control structure adapted to selectively allow an external device access to...
US-8,276,042 Determining sector status in a memory device
The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. A number of method embodiments include reading data...
US-8,275,926 Filtered register architecture to generate actuator signals
In various embodiments, apparatus and systems, as well as methods, may include an enhanced register to provide actuator signals to a memory array, the enhanced...
US-8,274,849 Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of...
An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each...
US-8,274,835 Mitigation of runaway programming of a memory device
Methods for mitigating runaway programming in a memory device, methods for program verifying a memory device, a memory device, and a memory system are provided....
US-8,274,833 Mitigation of data corruption from back pattern and program disturb in a non-volatile memory device
A write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program disturb in memory cells. Original data to...
US-8,274,832 Dynamic polarization for reducing stress induced leakage current
Subject matter disclosed herein relates to non-volatile flash memory, and more particularly to a method of reducing stress induced leakage current.
US-8,274,823 Methods and apparatus utilizing expected coupling effect in the programming of memory cells
Methods and memory devices configured to utilize predicted coupling effects of neighboring memory cells in the programming of target memory cells can be...
US-8,274,777 High aspect ratio openings
A capacitor forming method includes forming an electrically conductive support material over a substrate, with the support material containing at least 25 at %...
US-8,274,221 Plasma-generating structures, display devices, and methods of forming plasma-generating structures
Some embodiments include methods of forming plasma-generating microstructures. Aluminum may be anodized to form an aluminum oxide body having a plurality of...
US-8,274,163 Method and apparatus providing integrated circuit having redistribution layer with recessed connectors
A method of making a semiconductor die includes forming a trench around a conductive stud extending from the first side to a second side of a substrate to...
US-8,274,110 Vertically-oriented semiconductor selection device providing high drive current in cross-point array memory
A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first...
US-8,274,106 DRAM layout with vertical FETs and method of formation
DRAM cell arrays having a cell area of about 4F.sup.2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The...
US-8,274,081 Semiconductor constructions
Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection...
US-8,273,647 Methods of forming patterns, and methods of forming integrated circuits
Some embodiments include methods of forming patterns in substrates by utilizing block copolymer assemblies as patterning materials. A block copolymer assembly...
US-8,273,643 Diodes, and methods of forming diodes
Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is...
US-8,273,635 Semiconductor fabrication method and system
A method for manufacturing a semiconductor device is disclosed. In one embodiment, the method includes attaching a carrier to a substrate including a via to...
US-8,273,634 Methods of fabricating substrates
A method of fabricating a substrate includes forming first and second spaced features over a substrate. The first spaced features have elevationally outermost...
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