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| Patent # | Description |
|---|---|
| US-8,263,958 |
Layered resistance variable memory device and method of fabrication The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics.... |
| US-8,263,457 |
Methods of forming a plurality of capacitors A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area... |
| US-8,260,987 |
Methods and systems to accomplish variable width data input Disclosed are methods and systems for variable width data input to a pattern-recognition processor. A variable width data input method may include receiving... |
| US-8,260,973 |
Memory controllers, memory systems, solid state drives and methods for
processing a number of commands The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end... |
| US-8,260,449 |
Photolithography systems and associated methods of overlay error
correction Several embodiments of photolithography systems and associated methods of overlay error correction are disclosed herein. In one embodiment, a method for... |
| US-8,259,512 |
Low voltage sensing scheme having reduced active power down standby
current A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a Psense amplifier... |
| US-8,259,508 |
Erase operation control sequencing apparatus, systems, and methods Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a... |
| US-8,259,491 |
Coarse and fine programming in a solid state memory Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer... |
| US-8,259,488 |
Phase-change memory temperature sensitive detector A Phase-Change Memory (PCM) having a temperature detector with a dedicated PCM bit programmed to an amorphous state and a circuit to determine that the... |
| US-8,259,461 |
Apparatus for bypassing faulty connections Apparatus are disclosed, such as those involving a 3-D integrated circuit. One such apparatus includes a first die including a plurality of vertical connectors... |
| US-8,258,854 |
Devices and methods for reducing effects of device mismatch in temperature
sensor circuits A temperature sensor having one or more mirror circuits output temperature dependent output signals is disclosed in one embodiment. The temperature sensor... |
| US-8,258,836 |
Locked loops, bias generators, charge pumps and methods for generating
control voltages Locked loops, bias generators, charge pumps and methods for generating control voltages are disclosed, such as a bias generator that generates bias voltages for... |
| US-8,258,816 |
Integrated circuit comparator or amplifier An integrated circuit comparator comprises a differential amplifier, a source follower circuit coupled to a gate terminal of a first transistor in the... |
| US-8,258,518 |
Flash memory device having a graded composition, high dielectric constant
gate insulator A graded composition, high dielectric constant gate insulator is formed between a substrate and floating gate in a flash memory cell transistor. The gate... |
| US-8,258,034 |
Charge-trap based memory Methods of fabricating 3D charge-trap memory cells are described, along with apparatus and systems that include them. In a planar stack formed by alternate... |
| US-8,258,006 |
Method for fabricating stacked semiconductor components A semiconductor component includes a carrier and multiple semiconductor substrates stacked and interconnected on the carrier. The carrier includes conductive... |
| US-8,257,497 |
Insitu post atomic layer deposition destruction of active species Systems and methods for insitu post atomic layer deposition (ALD) destruction of active species are provided. ALD processes deposit multiple atomic layers on a... |
| US-8,256,695 |
Method for purification of semiconducting single wall nanotubes A process of forming a semiconductive carbon nanotube structure includes imposing energy on a mixture that contains metallic carbon nanotubes and semiconductive... |
| US-8,256,293 |
Devices comprising nanotubes for use as sensors and/or transducers, and
related methods Devices usable as sensors, as transducers, or as both sensors and transducers include one or more nanotubes or nanowires. In some embodiments, the devices may... |
| US-8,255,788 |
Method and apparatus for facilitating substitution of digital images with
line drawings One embodiment of the present invention provides a system that facilitates substitution of a full bitmap version of a graphical image with a line drawing... |
| US-8,255,771 |
Memory device repair apparatus, systems, and methods Operations within a memory device to replace one or more selected failing memory cells with one or more repair memory cells and to correct data digits read from... |
| US-8,254,199 |
Multi-channel memory and power supply-driven channel selection Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels... |
| US-8,254,191 |
Switched interface stacked-die memory architecture Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request... |
| US-8,254,182 |
Analog sensing of memory cells with a source follower driver in a
semiconductor memory device Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line.... |
| US-8,254,180 |
Methods of operating memories including characterizing memory cell signal
lines Methods of operating memories facilitate compensating for memory cell signal line propagation delays, such as to increase the overall threshold voltage range... |
| US-8,254,174 |
Memory segment accessing in a memory device Methods for programming memory devices, a memory device, and memory systems are provided. According to at least one such method, bit lines a memory segment are... |
| US-8,254,173 |
NAND memory constructions Some embodiments include NAND memory constructions. The constructions may contain semiconductor material pillars extending upwardly between dielectric regions,... |
| US-8,253,442 |
Apparatus and method for signal transmission over a channel Apparatus and methods are disclosed, such as those involving data transmission. One such apparatus includes a transmitter, a receiver, and a channel. The... |
| US-8,253,433 |
Testing apparatus for integrated circuit An apparatus for testing an integrated circuit comprises: a chip unit with a plurality of electronic parts such as chip units arranged on the upside of a chip... |
| US-8,253,396 |
Voltage regulator system The present disclosure includes circuits, systems and methods for regulating voltage. One voltage regulator system embodiment includes a voltage regulator... |
| US-8,253,230 |
Disabling electrical connections using pass-through 3D interconnects and
associated systems and methods Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are... |
| US-8,253,203 |
Electrostatic discharge (ESD) protection circuit An electrostatic discharge (ESD) protection circuit that includes a parallel connection of parasitic vertical and lateral bipolar junction transistors (BJTs)... |
| US-8,253,198 |
Devices for shielding a signal line over an active region A multi-path transistor includes an active region including a channel region and an impurity region. A gate is dielectrically separated from the channel region.... |
| US-8,253,191 |
Vertically-oriented semiconductor selection device for cross-point array
memory A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first... |
| US-8,252,697 |
Zinc-tin oxide thin-film transistors Methods of forming transparent zinc-tin oxide structures are described. Devices that include transparent zinc-tin oxide structures as at least one of a channel... |
| US-8,252,658 |
Methods of etching trenches into silicon of a semiconductor substrate,
methods of forming trench isolation in... A method of etching trenches into silicon of a semiconductor substrate includes forming a mask over silicon of a semiconductor substrate, with the mask... |
| US-8,252,646 |
Peripheral gate stacks and recessed array gates Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic... |
| US-8,252,622 |
Phase change current density control structure A phase change memory element and method of forming the same. The memory element includes first and second electrodes. A first layer of phase change material is... |
| US-8,252,194 |
Methods of removing silicon oxide A method of removing at least a portion of a silicon oxide material is disclosed. The silicon oxide is removed by exposing a semiconductor structure comprising... |
| US-8,252,119 |
Microelectronic substrate cleaning systems with polyelectrolyte and
associated methods Several embodiments of cleaning systems using polyelectrolyte and various associated methods for cleaning microelectronic substrates are disclosed herein. One... |
| US-8,250,418 |
Test mode for parallel load of address dependent data to enable loading of
desired data backgrounds One or more embodiments of the invention enable a memory device to load its memory array with desired background data, such as to reduce total test time and... |
| US-8,250,417 |
Method for detecting flash program failures One or more techniques are provided for programming a flash memory device. In one embodiment, the memory device is programmed such that a data pattern written... |
| US-8,250,328 |
Apparatus and method for buffered write commands in a memory Memories, buffered write command circuits, and methods for executing memory commands in a memory. In some embodiments, read commands that are received after... |
| US-8,250,314 |
Method and device for checking sector protection information of a
non-volatile memory A non-volatile memory device includes addressable sectors and an ancillary volatile memory array. The ancillary volatile memory array stores protection... |
| US-8,250,312 |
Configurable multi-port memory devices and methods Embodiments of a multi-port memory device may include a plurality of ports and a plurality of memory banks some of which are native to each port and some of... |
| US-8,250,294 |
Block management for mass storage An embodiment of the present invention includes a nonvolatile memory system comprising nonvolatile memory for storing sector information, the nonvolatile memory... |
| US-8,250,287 |
Enhanced throughput for serial flash memory, including streaming mode
operations Subject matter disclosed herein may relate to storing a streaming mode enable value in a configuration register, receiving a streaming mode entry signal at a... |
| US-8,250,282 |
PCM memories for storage bus interfaces A memory controller for a phase change memory (PCM) that can be used on a storage bus interface is described. In one example, the memory controller includes an... |
| US-8,248,881 |
Method and apparatus for managing behavior of memory devices A method of managing power consumption by a memory in a memory device includes determining whether the device is powered by a depletable power supply, and if it... |
| US-8,248,880 |
Voltage regulators, amplifiers, memory devices and methods Circuits, devices and methods are provided, such as an amplifier (e.g., a voltage regulator) that includes a feedback circuit that supplies negative feedback... |
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