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| Patent # | Description |
|---|---|
| US-8,211,762 |
Non-volatile memory Briefly, embodiments of non-volatile memory and embodiments of fabrication thereof are disclosed. For example, a non-volatile memory device having a gate... |
| US-8,211,743 |
Methods of forming non-volatile memory cells having multi-resistive state
material between conductive electrodes A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. The... |
| US-D662,895 |
Electric contact |
| US-8,209,521 |
Methods of indirect register access including automatic modification of a
directly accessible address register Systems and methods are provided for managing access to registers. A system may include a set of direct registers and a set of indirect registers. The indirect... |
| US-8,209,477 |
Non-volatile memory device having assignable network identification Memory devices and methods disclosed such as a memory device having a plurality of memory dies where each die includes a network identification that uniquely... |
| US-8,209,447 |
Device to device flow control within a chain of devices The present disclosure includes methods, devices, and systems for device to device flow control. In one or more embodiments, a system configured for device to... |
| US-8,208,334 |
Systems, memories, and methods for refreshing memory arrays Memories, systems, and methods for refreshing are provided, such as a memory with an array of memory cells divided into sections. Memories include replacement... |
| US-8,208,322 |
Non-volatile memory control Methods and apparatus for use in a memory system having a non-volatile memory and a controller for limiting the number of non-volatile memory arrays from a... |
| US-8,208,278 |
Couplings within memory devices A memory device includes a first bit line coupled to a first source/drain region of a first multiplexer gate, a second bit line coupled to a first source/drain... |
| US-8,208,277 |
Memory modules and memory devices having memory device stacks, and method
of forming same A memory module, system and method of forming the same includes a memory module including a plurality of memory devices having a first portion of memory devices... |
| US-8,208,241 |
Crystallographically orientated tantalum pentoxide and methods of making
same Methods of forming an oxide are disclosed and include contacting a ruthenium-containing material with a tantalum-containing precursor and contacting the... |
| US-8,207,768 |
Digital locked loops and methods with configurable operating parameters A locked loop may have an adjustable hysteresis and/or a tracking speed that can be programmed by a user of an electronic device containing the locked loop or... |
| US-8,207,614 |
Methods for forming arrays of small, closely spaced features Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can... |
| US-8,207,599 |
Method and apparatus for directing molding compound flow and resulting
semiconductor device packages Flow diverting structures for preferentially impeding, redirecting or both impeding and redirecting the flow of flowable encapsulant material, such as molding... |
| US-8,207,588 |
Method and apparatus providing analytical device and operating method
based on solid state image sensor An analytical system-on-a-chip can be used as an analytical imaging device, for example, for detecting the presence of a chemical compound. A layer of... |
| US-8,207,583 |
Memory device comprising an array portion and a logic portion In an embodiment of the present invention, a method comprises patterning a first plurality of semiconductor structures in an array portion of a semiconductor... |
| US-8,207,582 |
Semiconductor devices including dual gate structures Semiconductor devices including dual gate structures and methods of forming such semiconductor devices are disclosed. For example, semiconductor devices are... |
| US-8,207,570 |
Semiconductor constructions Some embodiments include formation of polymer spacers along sacrificial material, removal of the sacrificial material, and utilization of the polymer spacers as... |
| US-8,207,564 |
Memory cell, pair of memory cells, and memory array A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to... |
| US-8,207,557 |
Cross-point memory structures Some embodiments include cross-point memory structures. The structures may include a line of first electrode material extending along a first horizontal... |
| US-8,207,041 |
Semiconductor processing methods Some embodiments include methods in which a pair of spaced-apart adjacent features is formed over a substrate. The features have silicon dioxide surfaces.... |
| US-8,207,032 |
Methods of forming pluralities of vertical transistors, and methods of
forming memory arrays Some embodiments include methods of forming vertical transistors. A construction may have a plurality of spaced apart fins extending upwardly from a... |
| US-8,207,016 |
Methods of cooling semiconductor dies The invention includes semiconductor packages having grooves within a semiconductor die backside; and includes semiconductor packages utilizing carbon... |
| US-8,206,603 |
Methods of etching nanodots, methods of fabricating integrated circuit
devices and device structures, methods... Embodiments of the invention include methods of etching nanodots, to methods of removing nanodots from substrates, and to methods of fabricating integrated... |
| US-8,205,055 |
System and method for decoding commands based on command signals and
operating state A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based... |
| US-8,203,901 |
Configurable bandwidth memory devices and methods Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for... |
| US-8,203,900 |
Data serializers, output buffers, memory devices and methods of
serializing Data serializers, output buffers, memory devices and methods for serializing are provided, including a data serializer that may convert digits of parallel data... |
| US-8,203,886 |
Memory device reference cell programming method and apparatus Memory devices and methods are disclosed, such as those facilitating an assignment scheme of reference cells throughout an array of memory cells. For example,... |
| US-8,203,876 |
Reducing effects of erase disturb in a memory device Methods for programming and memory devices are disclosed. One such method for programming includes initially biasing a subset of a plurality of control gates of... |
| US-8,203,866 |
Capacitor-less memory cell, device, system and method of making same A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of... |
| US-8,203,695 |
Photolithography systems and associated methods of focus correction Several embodiments of photolithography systems and associated methods of focus correction are disclosed herein. In one embodiment, a method for characterizing... |
| US-8,203,213 |
Methods for packaging microelectronic devices and microelectronic devices
formed using such methods Methods for packaging microelectronic devices and microelectronic devices formed using such methods are disclosed herein. One aspect of the invention is... |
| US-8,203,202 |
Stacked package and method for forming stacked package A semiconductor chip module including a plurality of semiconductor chips, each provided on the side face thereof with a part of connection terminals coupled... |
| US-8,203,179 |
Device having complex oxide nanodots Devices are disclosed, such as those having a memory cell. The memory cell includes an active area formed of a semiconductor material; a first dielectric over... |
| US-8,203,134 |
Memory devices with enhanced isolation of memory cells, systems including
same and methods of forming same Memory cells of a memory device including a variable resistance material have a cavity between the memory cells. Electronic systems include such memory devices.... |
| US-8,202,806 |
Method to avoid threshold voltage shift in thicker dielectric films A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor... |
| US-8,202,804 |
Methods of making self-aligned nano-structures A method for creating structures in a semiconductor assembly is provided. The method includes etching apertures into a dielectric layer and applying a polymer... |
| US-8,202,754 |
Packaged microelectronic devices recessed in support member cavities, and
associated methods Packaged microelectronic devices recessed in support member cavities, and associated methods, are disclosed. Method in accordance with one embodiment includes... |
| US-8,202,684 |
Method for manufacturing probe sheet An embodiment of the invention provides a method for manufacturing a probe sheet in which a probe tip can be arranged at a predetermined accurate position... |
| US-8,200,894 |
Solid state storage device controller with expansion mode Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one... |
| US-8,200,031 |
Multisampling with reduced bit samples A relatively non-complex signal processor supporting an active pixel sensor imaging system is disclosed. The signal processor only requires the first sample... |
| US-8,199,599 |
Variable memory refresh devices and methods Memory devices and methods are described such as those that monitor and adjust characteristics for various different portions of a given memory device. Examples... |
| US-8,199,595 |
Techniques for sensing a semiconductor memory device Techniques for sensing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus... |
| US-8,199,585 |
Dynamic soft program trims Systems and methods are disclosed for modifying soft-programming trims of a non-volatile memory device, such as a flash memory device. The soft-programming... |
| US-8,199,574 |
Apparatus comparing verified data to original data in the programming of a
memory array Apparatus configured to perform a programming operation on at least one memory cell of the memory array in response to original data, and further configured to... |
| US-8,199,572 |
Non-volatile memory with both single and multiple level cells Memory arrays and methods of operating such memory arrays are described as having a memory cell operated as a single level cell interposed between and coupled... |
| US-8,199,566 |
Write performance of phase change memory using set-pulse shaping Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory. |
| US-8,199,556 |
Methods of reading and using memory cells Some embodiments include methods of reading memory cells. The memory cells have a write operation that occurs only if a voltage of sufficient absolute value is... |
| US-8,198,910 |
Transmitter apparatus, systems, and methods Apparatus, systems, and methods are disclosed that operate to drive an output with a data signal and to boost a potential of the output in response to a boost... |
| US-8,198,720 |
Microelectronic die packages with metal leads, including metal leads for
stacked die packages, and associated... Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked... |
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