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Patent # Description
US-8,164,975 Data capture system and method, and memory controllers and devices
Embodiments of a data capture system and method may be used in a variety of devices, such as in memory controllers and memory devices. The data capture system...
US-8,164,959 Method and system for programming non-volatile memory cells based on programming of proximate memory cells
A multi-level non-volatile memory device programs cells in each row in a manner that takes into account the coupling from the programming of cells that are...
US-8,164,951 Method and apparatus for providing a non-volatile memory with reduced cell capacitive coupling
A flash memory architecture that provides a mechanism for reducing floating gate to floating gate coupling. The floating gates of the memory cells are shifted,...
US-8,164,950 Reduction of punch-through disturb during programming of a memory device
A punch-through disturb effect in a memory device can be reduced by biasing a selected word line at a program voltage to program a selected memory cell, biasing...
US-8,164,948 Spintronic devices with integrated transistors
The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a...
US-8,164,368 Power savings mode for memory systems
A system and method are disclosed to accomplish power savings in an electronic device, such as a memory chip, by performing selective frequency locking and...
US-8,164,366 Locked loops, bias generators, charge pumps and methods for generating control voltages
Locked loops, bias generators, charge pumps and methods for generating control voltages are disclosed, such as a bias generator that generates bias voltages for...
US-8,164,081 Memory devices and formation methods
A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant...
US-8,163,648 Atomic layer deposition methods
An atomic layer deposition method includes providing a semiconductor substrate within a deposition chamber. A first metal halide-comprising precursor gas is...
US-8,163,613 Methods of forming a plurality of capacitors
A method of forming a plurality of capacitors includes forming a plurality of individual capacitor electrodes using two masking steps. An earlier of the two...
US-8,163,610 Fabrication of finned memory arrays
Methods and apparatus are provided. For an embodiment, a plurality fins is formed in a substrate so that the fins protrude from a substrate. After the plurality...
US-8,163,468 Method of reducing photoresist defects during fabrication of a semiconductor device
Reducing or eliminating watermark-type defects during semiconductor device fabrication are described and can comprise treating photoresist using one of several...
US-8,163,355 Formation of carbon-containing material
A method includes forming ionic clusters of carbon-containing molecules, which molecules have carbon-carbon sp.sup.2 bonds, and accelerating the clusters. A...
US-8,163,341 Methods of forming metal-containing structures, and methods of forming germanium-containing structures
Some embodiments include methods of forming metal-containing structures. A first metal-containing material may be formed over a substrate. After the first...
US-8,162,540 DRAM temperature measurement system
A converter comprising a comparator having a first input operable to receive a first signal, a second input operable to receive a second signal, and an output,...
US-8,162,227 Intelligent controller system and method for smart card memory modules
A storage device contains a smart-card device and a memory device, both of which are accessed though a controller. The storage device may be used in the same...
US-8,161,334 Externally maintained remap information
Disclosed is a system comprising a memory device, a controller to maintain remap information regarding the memory device, and a storage unit to store the...
US-8,161,229 Flash memory architecture with separate storage of overhead and user data
A memory device has a plurality of dedicated data blocks for storing only user data and a plurality of dedicated overhead blocks for storing only overhead data....
US-8,160,381 Method and apparatus for image noise reduction using noise models
A method and apparatus for processing imager pixel signals to reduce noise. The processing includes receiving a target pixel signal, receiving at least one...
US-8,160,351 Method and apparatus for mura detection and metrology
The invention addresses the lack of comprehensive and quantitative methods for measurements of unwanted visual "mura" effects in displays and image sensors....
US-8,159,899 Wordline driver for memory
Subject matter disclosed herein relates to accessing memory, and more particularly to a wordline driver of same.
US-8,159,896 Local power domains for memory sections of an array of memory
Memories, memory arrays, and methods for selectively providing electrical power to memory sections of a memory array are disclosed. A memory array can be...
US-8,159,890 Redundant memory array for replacing memory sections of main memory
Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory...
US-8,159,879 Reducing effects of program disturb in a memory device
A method for programming that biases a selected word line with a programming voltage. An unselected word line on the source side and an unselected word line on...
US-8,159,875 Methods of storing multiple data-bits in a non-volatile memory cell
Methods of storing multiple data-bits in a non-volatile memory cell are carried out by trapping carriers in a composite trapping layer formed over a tunnel...
US-8,159,874 Cell operation monitoring
Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data...
US-8,159,588 Exposure control for image sensors
An imaging system utilizes an exposure control circuit to control the length of an exposure in full frame mode. The exposure control circuit receives as an...
US-8,159,270 Circuitry and methods minimizing output switching noise through split-level signaling and bus division enabled...
Disclosed herein are circuitry and methods for transmitting data across a parallel bus using both high common mode and low common mode signaling. The...
US-8,159,050 Single crystal silicon structures
A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon...
US-8,159,014 Localized biasing for silicon on insulator structures
A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned...
US-8,158,967 Integrated memory arrays
Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces....
US-8,158,921 Dual conversion gain gate and capacitor combination
An imaging device comprising a plurality of photosensors, a shared diffusion region for receiving charge generated by the photosensors, and a dual conversion...
US-8,158,488 Method of increasing deposition rate of silicon dioxide on a catalyst
Methods for forming dielectric layers, and structures and devices resulting from such methods, and systems that incorporate the devices are provided. The...
US-8,158,476 Integrated circuit fabrication
A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a...
US-8,158,471 Capacitorless DRAM on bulk silicon
A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of...
US-8,156,950 Megasonic cleaning with controlled boundary layer thickness and associated systems and methods
Megasonic cleaning systems and methods of using megasonic pressure waves to impart cavitation energy proximate a surface of a microelectronic substrate are...
US-8,156,322 Critical security parameter generation and exchange system and method for smart-card memory modules
A storage device contains a smart-card device and a memory device, which is connected to a controller. The storage device may be used in the same manner as a...
US-8,156,291 Memory register encoding systems and methods
Apparatus, systems, and methods are disclosed that operate to encode register bits to generate encoded bits such that, for pairs of addresses, an encoded bit to...
US-8,154,931 Circuits, devices, systems, and methods of operation for capturing data signals
Embodiments of the invention are described for driving data onto a data bus. The embodiments include a data driver circuit having a data capture circuit coupled...
US-8,154,926 Memory cell programming
One or more embodiments include programming, in parallel, a first cell to one of a first number of states and a second cell to one of a second number of states....
US-8,154,906 Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and...
Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In...
US-8,154,081 Processes and apparatus having a semiconductor fin
A process may include first etching a trench isolation dielectric through a dielectric hard mask that abuts the sidewall of a fin semiconductor. The first etch...
US-8,154,066 Titanium aluminum oxide films
A dielectric layer containing an insulating metal oxide film having multiple metal components and a method of fabricating such a dielectric layer produce a...
US-8,154,064 Semiconductor constructions
The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention...
US-8,154,006 Controlling the circuitry and memory array relative height in a phase change memory feol process flow
A CMOS logic portion embedded with a PCM portion is recessed by a gate structure height as measured by a thickness of a gate oxide and a polysilicon gate to...
US-8,154,004 Hybrid MRAM array structure and operation
This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ...
US-8,153,522 Patterning mask and method of formation of mask using step double patterning
A method of forming a mask for use in fabricating an integrated circuit includes forming first non-removable portions of a photoresist material through a mask...
US-8,153,502 Methods for filling trenches in a semiconductor material
Methods of filling cavities or trenches. More specifically, methods of filling a cavity or trench in a semiconductor layer are provided. The methods include...
US-8,153,497 Lanthanide dielectric with controlled interfaces
Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer...
US-8,153,019 Methods for substantially equalizing rates at which material is removed over an area of a structure or film...
Methods for preventing isotropic removal of materials at corners formed by seams, keyholes, and other anomalies in films or other structures include use of etch...
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