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Patent # Description
US-8,181,086 Memory array error correction apparatus, systems, and methods
Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being...
US-8,180,995 Logical address offset in response to detecting a memory formatting operation
The present disclosure includes methods, devices, and systems for a logical address offset. One method embodiment includes detecting a memory unit formatting...
US-8,180,974 System, apparatus, and method for modifying the order of memory accesses
Systems and methods for controlling memory access operations are disclosed. The system may include one or more requestors performing requests to memory devices....
US-8,180,609 Jittery signal generation with discrete-time filtering
The computer-implementable method allows for the fast creation of a multi-unit interval data signal suitable for simulation. The created signal represents the...
US-8,180,150 Method and apparatus providing automatic color balancing for digital imaging systems
Pixels from an image are sampled for gray world statistics. To avoid the effect of saturated regions, the pixels are pruned. If a predetermined percentage of...
US-8,179,726 Method and apparatus for programming flash memory
A method and apparatus that provides the ability to control programming pulses having different widths and/or voltages in a flash memory device. The widths...
US-8,179,725 Programming rate identification and control in a solid state memory
Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer...
US-8,179,724 Sensing for memory read and program verify operations in a non-volatile memory device
Methods for sensing in a memory device and a memory device are disclosed. In one such sensing method, a single read operation with multiple sense amplifier...
US-8,179,706 Method for modifying data more than once in a multi-level cell memory location within a memory array
A method and apparatus for marking a block of multi-level memory cells for performance of a block management function by programming at least one bit in a lower...
US-8,179,468 Integrated CMOS imager and microcontroller
A method and apparatus providing a CMOS imager with an integrated controller on a common integrated circuit substrate. Also integrated on the common substrate...
US-8,178,984 Flip chip with interposer
A device is disclosed which includes a die comprising an integrated circuit and an interposer that is coupled to the die, the interposer having a smaller...
US-8,178,911 Semiconductor device having reduced sub-threshold leakage
A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed...
US-8,178,413 Low-temperature grown high quality ultra-thin CoTiO.sub.3 gate dielectrics
A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO.sub.2 gate oxides...
US-8,178,396 Methods for forming three-dimensional memory devices, and related structures
Methods of forming semiconductor devices that include one or more arrays of memory devices in a three-dimensional arrangement, such as those that include...
US-8,177,420 Apparatus and methods for temperature calibration and sensing
Some embodiments include apparatus and methods having a first switch, a second switch, and a circuit coupled to the first and second switches. The first switch...
US-8,176,547 System and method for controlling user access to an electronic device
A system requires a user to enter a geometric pattern on an interface device to gain access to the system. After the correct geometric pattern is entered, a...
US-8,176,371 Embedded processor
Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a...
US-8,176,232 Dedicated interface to factory program phase-change memories
A nonvolatile memory device has a dedicated serial programming port to provide a data path to memory storage. A dedicated power pin supplies power for the...
US-8,174,919 Apparatus and method for increasing data line noise tolerance
Circuits and methods for improving noise tolerance in memories are disclosed such as those that include biasing a data line above a normal threshold voltage,...
US-8,174,900 Wordline voltage transfer apparatus, systems, and methods
The apparatus and systems described herein may comprise a plurality of memory cells coupled to a local wordline, and a wordline drive circuit that includes a...
US-8,174,897 Programming in a memory device
Methods for programming a memory device and memory devices are provided. According to at least one such method, a selected memory cell is programmed by a series...
US-8,174,893 Independent well bias management in a memory device
Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device...
US-8,174,887 Adjusting for charge loss in a memory
Memory and methods of operating a memory adjusting an output voltage of an analog storage device, such as a data cache capacitor holding a voltage level...
US-8,174,881 Techniques for reducing disturbance in a semiconductor device
Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a...
US-8,174,859 Memory device interface methods, apparatus, and systems
Apparatus and systems may include a substrate and a first memory device coupled to the substrate using a through wafer interconnect (TWI). An example may...
US-8,174,297 Multi-phase clock generation
An apparatus and method for multi-phase clock generation are disclosed. One embodiment of the apparatus includes a module generating first and second...
US-8,174,105 Stacked semiconductor package having discrete components
A stacked semiconductor package includes a substrate and a plurality of semiconductor dice stacked on the substrate. Each semiconductor die includes a recess,...
US-8,174,101 Microelectronic devices and microelectronic support devices, and associated assemblies and methods
Microelectronic devices, associated assemblies, and associated methods are disclosed herein. For example, certain aspects of the invention are directed toward a...
US-8,174,081 Fully depleted silicon-on-insulator CMOS logic
A extractor implanted region is used in a silicon-on-insulator CMOS memory device. The extractor region is reversed biased to remove minority carriers from the...
US-8,174,061 Floating-gate structure with dielectric component
Floating-gate memory cells having a floating gate with a conductive portion and a dielectric portion facilitate increased levels of charge trapping sites within...
US-8,173,988 Reduced power consumption phase change memory and methods for forming the same
Memory cells for reduced power consumption and methods for forming the same are provided. A memory cell has a layer of phase change material. A first portion of...
US-8,173,550 Method for positioning spacers for pitch multiplication
Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers...
US-8,173,517 Method for forming a self-aligned isolation structure utilizing sidewall spacers as an etch mask and remaining...
The present invention relates to methods for forming microelectronic structures in a semiconductor substrate. The method includes selectively removing...
US-8,173,507 Methods of forming integrated circuitry comprising charge storage transistors
Methods include forming a charge storage transistor gate stack over semiconductive material. One such stack includes a tunnel dielectric, charge storage...
US-8,173,333 Reduced lens heating methods, apparatus, and systems
In one embodiment, a system is disclosed that includes an illuminator having a source that produces light waves having a first wavelength, and a mask. The mask...
US-8,173,034 Methods of utilizing block copolymer to form patterns
Some embodiments include methods of utilizing block copolymer to form patterns between weirs. The methods may utilize liners along surfaces of the weirs to...
US-8,171,830 Machine tool
According to one embodiment, a machine tool for machining a workpiece includes: a main spindle that holds the workpiece to rotate the workpiece around a axis; a...
US-8,171,353 System and method for initializing a memory system, and memory device and processor-based system using same
Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a...
US-8,171,203 Faster write operations to nonvolatile memory using FSInfo sector manipulation
An embodiment of the present invention includes a digital equipment system having a host for sending write commands to write files having sector information and...
US-8,171,181 Memory module with configurable input/output ports
A memory module has one or more memory devices, a controller in communication with the one or more memory devices, and a plurality of input/output ports. The...
US-8,169,841 Strobe apparatus, systems, and methods
A strobe signal is received in a device and execution of an operation in the device is delayed when the strobe signal includes a preamble. Additional apparatus,...
US-8,169,833 Partitioning process to improve memory cell retention
Subject matter disclosed herein relates to improving memory cell retention for non-volatile flash memory.
US-8,169,832 Methods of erase verification for a flash memory device
Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data...
US-8,169,830 Sensing for all bit line architecture in a memory device
Methods for sensing, memory devices, and memory systems are disclosed. One such method for sensing includes charging bit lines of an all bit line architecture...
US-8,169,808 NAND flash content addressable memory
NAND architecture non-volatile content addressable (CAM) memory devices and methods are described that allows for high density, low cost CAM devices. In...
US-8,169,759 Circuit and methods to protect input buffer
Apparatus, systems, and methods are disclosed that operate to boost an electrical potential of a control terminal of a transistor from a signal on an input...
US-8,169,032 Gate stacks and semiconductor constructions
The invention includes methods of forming PMOS transistors and NMOS transistors. The NMOS transistors can be formed to have a thin silicon-containing material...
US-8,168,502 Tantalum silicon oxynitride high-K dielectrics and metal gates
Electronic apparatus and methods of forming the electronic apparatus include a tantalum silicon oxynitride film on a substrate for use in a variety of...
US-8,168,476 Interconnects for packaged semiconductor devices and methods for manufacturing such devices
Packaged semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a...
US-8,166,488 Methods of directly accessing a mass storage data device
Methods of directly accessing a mass storage data device without communicating through an operating system layer are useful in recovering information previously...
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