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Patent # Description
US-8,153,019 Methods for substantially equalizing rates at which material is removed over an area of a structure or film...
Methods for preventing isotropic removal of materials at corners formed by seams, keyholes, and other anomalies in films or other structures include use of etch...
US-8,152,918 Methods for epitaxial silicon growth
Methods of cleaning substrates and growing epitaxial silicon thereon are provided. Wafers are exposed to a plasma for a sufficient time prior to epitaxial...
US-8,151,041 Removable storage device
Methods and removable storage devices are provided. Some such removable storage devices may include a file specifying a name of a program to be executed...
US-8,151,040 Version based non-volatile memory translation layer
A non-volatile memory and erase block/data block/sector/cluster update and address translation scheme utilizing a version number is detailed that enhances data...
US-8,149,646 Digital filters for semiconductor devices
A memory device that, in certain embodiments, includes a memory element and a digital filter. The digital filter may include a counter and a divider, where the...
US-8,149,619 Memory structure having volatile and non-volatile memory portions
A memory array is provided that includes a transistor having two active gates sharing a source, a drain, and a channel of the transistor. One of the active...
US-8,149,326 Real-time exposure control for automatic light control
An imager and a method for real-time, non-destructive monitoring of light incident on imager pixels during their exposure to light. Real-time or present pixel...
US-8,149,307 Methods of fabricating integrated imager and microcontroller
A method and apparatus providing a CMOS imager with an integrated controller on a common integrated circuit substrate. Also integrated on the common substrate...
US-8,149,045 Variable stage charge pump and method for providing boosted output voltage
An embodiment of a variable stage charge pump includes a plurality of pump stages. Each stage is configured to generate an intermediate boosted output voltage....
US-8,149,034 Delay lines, methods for delaying a signal, and delay lock loops
Locked loops, delay lines and methods for delaying signals are disclosed, such as a delay line and delay lock loop using the delay line includes a series of...
US-8,148,807 Packaged microelectronic devices and associated systems
Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged...
US-8,148,803 Molded stiffener for thin substrates
A stiffener molded to a semiconductor substrate, such as a lead frame, and methods of molding the stiffener to the substrate are provided. The stiffener is...
US-8,148,780 Devices and systems relating to a memory cell having a floating body
Methods, devices, and systems are disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the...
US-8,148,776 Transistor with a passive gate
Disclosed is a device having a transistor that includes a source, a drain, a channel region extending between the source and the drain, a gate disposed near the...
US-8,148,775 Methods of providing electrical isolation and semiconductor structures including same
Methods of isolating gates in a semiconductor structure. In one embodiment, isolation is achieved using a spacer material in combination with fins having...
US-8,148,580 Methods of forming a tellurium alkoxide and methods of forming a mixed halide-alkoxide of tellurium
A method of forming a tellurium alkoxide includes providing a tellurium halide and a non-tellurium alkoxide in a liquid organic solvent. The liquid organic...
US-8,148,263 Methods for forming conductive vias in semiconductor device components
A method for forming conductive vias in a substrate of a semiconductor device component includes forming one or more holes, or apertures or cavities, in the...
US-8,148,247 Method and algorithm for random half pitched interconnect layout with constant spacing
An embodiment of a system and method produces a random half pitched interconnect layout. A first normal-pitch mask and a second normal-pitch mask are created...
US-8,148,225 Fully-depleted (FD)(SOI) MOSFET access transistor and method of fabrication
A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity...
US-8,148,222 Cross-point diode arrays and methods of manufacturing cross-point diode arrays
Methods of forming an array of memory cells and memory cells that have pillars. Individual pillars can have a semiconductor post formed of a bulk semiconductor...
US-8,148,197 Methods of forming germanium-antimony-tellurium materials and a method of forming a semiconductor device...
A method of forming a material. The method comprises conducting an ALD layer cycle of a first metal, the ALD layer cycle comprising a reactive first metal...
US-8,145,866 Selective register reset
The present disclosure includes methods, devices, modules, and systems for storing selective register reset. One method embodiment includes receiving an...
US-8,144,534 Methods and memory devices for repairing memory cells
Methods and memory devices for repairing memory cells are discloses, such as a memory device that includes a main array having a plurality of sections of memory...
US-8,144,525 Memory cell sensing using negative voltage
Embodiments of the present disclosure provide methods, devices, modules, and systems for memory cell sensing using negative voltage. One method includes...
US-8,144,516 Dynamic pass voltage for sense operation in a memory device
Methods for sensing and memory devices are disclosed. One such method for sensing uses a dynamic pass voltage on at least one adjacent memory cell that is...
US-8,144,506 Cross-point memory devices, electronic systems including cross-point memory devices and methods of accessing a...
Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row)...
US-8,144,497 Self-identifying stacked die semiconductor components
A semiconductor die having a functional circuit (e.g., a memory array) and a decode circuit suitable for use in a stacked die semiconductor component (e.g., a...
US-8,144,307 Image forming method and apparatus
An array of phase-shifting micro-mechanical elements are used in a method and device for patterning a workpiece, for exposing a radiation sensitive layer on a...
US-8,144,269 Reflective LCOS displays utilizing novel polarizing beam splitters
Disclosed are display systems using reflective liquid-crystal microdisplays that efficiently use unpolarized light sources without needing to double the etendue...
US-8,143,966 Coupling cancellation scheme
Methods and apparatus are disclosed, such as those involving an interconnection layout for an integrated circuit (IC). One such layout includes a plurality of...
US-8,143,928 Duty cycle correction systems and methods
Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a...
US-8,143,167 Fabrication processes for forming dual depth trenches using a dry etch that deposits a polymer
Trench isolation structures and methods to form same for use in the manufacture of semiconductor devices are described. The trench isolation structures are...
US-8,142,673 Compositions for dissolution of low-k dielectric films, and methods of use
An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k...
US-8,140,780 Systems, methods, and devices for configuring a device
Disclosed are methods and devices, among which is a method for configuring an electronic device. In one embodiment, an electronic device may include one or more...
US-8,139,434 Methods and apparatus for voltage sensing and reporting
Semiconductor devices comprising at least one voltage sensor for sensing an operating voltage associated with an operational circuit of the semiconductor...
US-8,139,421 Erase degradation reduction in non-volatile memory
Methods for erasing a memory device and memory systems are provided, such as those including a non-volatile memory device is erased by using an intermediate...
US-8,139,419 Programming methods and memories
Methods of programming memory cells, and memories incorporating such methods, are disclosed. In at least one embodiment, programming is accomplished by applying...
US-8,139,418 Techniques for controlling a direct injection semiconductor memory device
Techniques for controlling a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized...
US-8,139,386 Memory, computing system and method for checkpointing
Embodiments of the present invention provide local checkpoint memories that are closely coupled to the processor of a computing system used during normal...
US-8,138,809 Periodic signal delay apparatus, systems, and methods
Apparatus, systems, and methods are disclosed that operate to delay a periodic input signal in one or more delay elements of a group of delay elements to...
US-8,138,794 Output slew rate control
This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver...
US-8,138,613 Microelectronic devices
Microelectronic devices and methods for manufacturing microelectronic devices are described herein. An embodiment of one such method includes attaching a...
US-8,138,541 Memory cells
Some embodiments include memory cells that contain floating bodies and diodes. The diodes may be gated diodes having sections doped to a same conductivity type...
US-8,138,526 Semiconductor structures including dual fins
Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel...
US-8,138,039 Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array
A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by...
US-8,138,021 Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing...
Packaged semiconductor components, apparatus for packaging semiconductor devices, methods of packaging semiconductor devices, and methods of manufacturing...
US-8,137,875 Method and apparatus for overlay compensation between subsequently patterned layers on workpiece
Methods and apparatuses for patterning workpieces are provided. The methods and apparatuses described herein improve overlay between subsequently patterned...
US-8,136,000 Test mode for multi-chip integrated circuit packages
When a test mode of a controller of a multi-chip integrated circuit package is activated, external signal lines coupled to the controller are re-mapped to...
US-8,135,940 Method of rotating data in a plurality of processing elements
A method of rotating data in a plurality of processing elements comprises a plurality of shifting operations and a plurality of storing operations, with the...
US-8,135,939 Robust index storage for non-volatile memory
A non-volatile memory data address translation scheme is described that utilizes a hierarchal address translation system that is stored in the non-volatile...
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