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Patent # Description
US-8,187,901 Epitaxial formation support structures and associated methods
Epitaxial formation support structures and associated methods of manufacturing epitaxial formation support structures and solid state lighting devices are...
US-8,187,487 Material removal methods employing solutions with reversible ETCH selectivities
A method for removing (e.g., etching) different dielectric materials from a semiconductor substrate includes exposing the semiconductor substrate to a solution...
US-8,184,492 Tri-state driver circuits having automatic high-impedance enabling
Memories, driver circuits, and methods for generating an output signal in response to an input signal. One such driver circuit includes an input stage and an...
US-8,184,489 Level shifting circuit
A level shifting circuit having an input and an output where the level shifting circuit is configured to receive a logical high level having a first voltage...
US-8,184,487 Modified read operation for non-volatile memory
A method may comprise executing a read operation to access a memory array by performing a preactive command to include a row-address-write operation and a...
US-8,184,481 Memory devices and methods of their operation including selective compaction verify operations
Memory devices and methods of their operation, where following an erasure of a string of memory cells, a selective compaction verify operation is performed on...
US-8,184,469 Stored multi-bit data characterized by multiple-dimensional memory states
A method for enhancing data storage may comprise storing two or more bits in a memory cell, wherein the stored bits may be characterized by two or more...
US-8,184,264 Calibration methods and devices useful in semiconductor photolithography
Several embodiments of photolithography devices and associated methods of focal calibration are disclosed herein. In one embodiment, a method for determining a...
US-8,184,188 Methods and apparatus for high dynamic operation of a pixel cell
A pixel circuit providing high dynamic operation, and methods of operating the pixel circuit providing for high dynamic operation. Methods include a lateral...
US-8,183,901 Delay locked loop circuit and method
Delay locked loop circuits and methods are disclosed. In the embodiments, a delay locked loop may include a phase detector to detect a phase difference between...
US-8,183,880 Devices and methods for driving a signal off an integrated circuit
Embodiments of the present invention provide electronic devices, memory devices and methods of driving an on-chip signal off a chip. In one such embodiment, an...
US-8,183,625 NROM flash memory devices on ultrathin silicon
An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is...
US-8,183,615 Memory cell with a vertically oriented transistor coupled to a digit line and method of forming the same
A memory cell, array and device include an active area formed in a substrate with a vertical transistor including a first end disposed over a first portion of...
US-8,183,515 Pumps for CMOS imagers
A pixel for an imaging device is described. The pixel includes a photosensitive device provided within a substrate for providing photo-generated charges, a...
US-8,183,157 Method of forming capacitors, and methods of utilizing silicon dioxide-containing masking structures
Some embodiments include methods of forming capacitors. Storage nodes are formed within a material. The storage nodes have sidewalls along the material. Some of...
US-8,183,154 Selective metal deposition over dielectric layers
Selective deposition of metal over dielectric layers in a manner that minimizes or eliminates keyhole formation is provided. According to one embodiment, a...
US-8,183,151 Methods of forming conductive vias through substrates, and structures and assemblies resulting therefrom
Methods of forming conductive elements on and in a substrate include forming a layer of conductive material over a surface of a substrate prior to forming a...
US-8,183,138 Methods for forming nanodots and/or a patterned material during the formation of a semiconductor device
Methods for forming nanodots and/or a patterned material are provided. One such method involves forming a first patterning material over a base. Blades of a...
US-8,183,110 Memory cells, methods of forming dielectric materials, and methods of forming memory cells
Some embodiments include memory cells. The memory cells may include a tunnel dielectric material, a charge-retaining region over the tunnel dielectric material,...
US-8,183,085 High rate selective polymer growth on a substrate
Method and systems provide growth of polymer structures at a high rate in a selective manner. In various embodiments, the method or system can expose the growth...
US-D660,349 Printer
US-8,181,086 Memory array error correction apparatus, systems, and methods
Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being...
US-8,180,995 Logical address offset in response to detecting a memory formatting operation
The present disclosure includes methods, devices, and systems for a logical address offset. One method embodiment includes detecting a memory unit formatting...
US-8,180,974 System, apparatus, and method for modifying the order of memory accesses
Systems and methods for controlling memory access operations are disclosed. The system may include one or more requestors performing requests to memory devices....
US-8,180,609 Jittery signal generation with discrete-time filtering
The computer-implementable method allows for the fast creation of a multi-unit interval data signal suitable for simulation. The created signal represents the...
US-8,180,150 Method and apparatus providing automatic color balancing for digital imaging systems
Pixels from an image are sampled for gray world statistics. To avoid the effect of saturated regions, the pixels are pruned. If a predetermined percentage of...
US-8,179,726 Method and apparatus for programming flash memory
A method and apparatus that provides the ability to control programming pulses having different widths and/or voltages in a flash memory device. The widths...
US-8,179,725 Programming rate identification and control in a solid state memory
Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer...
US-8,179,724 Sensing for memory read and program verify operations in a non-volatile memory device
Methods for sensing in a memory device and a memory device are disclosed. In one such sensing method, a single read operation with multiple sense amplifier...
US-8,179,706 Method for modifying data more than once in a multi-level cell memory location within a memory array
A method and apparatus for marking a block of multi-level memory cells for performance of a block management function by programming at least one bit in a lower...
US-8,179,468 Integrated CMOS imager and microcontroller
A method and apparatus providing a CMOS imager with an integrated controller on a common integrated circuit substrate. Also integrated on the common substrate...
US-8,178,984 Flip chip with interposer
A device is disclosed which includes a die comprising an integrated circuit and an interposer that is coupled to the die, the interposer having a smaller...
US-8,178,911 Semiconductor device having reduced sub-threshold leakage
A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed...
US-8,178,413 Low-temperature grown high quality ultra-thin CoTiO.sub.3 gate dielectrics
A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO.sub.2 gate oxides...
US-8,178,396 Methods for forming three-dimensional memory devices, and related structures
Methods of forming semiconductor devices that include one or more arrays of memory devices in a three-dimensional arrangement, such as those that include...
US-8,177,420 Apparatus and methods for temperature calibration and sensing
Some embodiments include apparatus and methods having a first switch, a second switch, and a circuit coupled to the first and second switches. The first switch...
US-8,176,547 System and method for controlling user access to an electronic device
A system requires a user to enter a geometric pattern on an interface device to gain access to the system. After the correct geometric pattern is entered, a...
US-8,176,371 Embedded processor
Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a...
US-8,176,232 Dedicated interface to factory program phase-change memories
A nonvolatile memory device has a dedicated serial programming port to provide a data path to memory storage. A dedicated power pin supplies power for the...
US-8,174,919 Apparatus and method for increasing data line noise tolerance
Circuits and methods for improving noise tolerance in memories are disclosed such as those that include biasing a data line above a normal threshold voltage,...
US-8,174,900 Wordline voltage transfer apparatus, systems, and methods
The apparatus and systems described herein may comprise a plurality of memory cells coupled to a local wordline, and a wordline drive circuit that includes a...
US-8,174,897 Programming in a memory device
Methods for programming a memory device and memory devices are provided. According to at least one such method, a selected memory cell is programmed by a series...
US-8,174,893 Independent well bias management in a memory device
Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device...
US-8,174,887 Adjusting for charge loss in a memory
Memory and methods of operating a memory adjusting an output voltage of an analog storage device, such as a data cache capacitor holding a voltage level...
US-8,174,881 Techniques for reducing disturbance in a semiconductor device
Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a...
US-8,174,859 Memory device interface methods, apparatus, and systems
Apparatus and systems may include a substrate and a first memory device coupled to the substrate using a through wafer interconnect (TWI). An example may...
US-8,174,297 Multi-phase clock generation
An apparatus and method for multi-phase clock generation are disclosed. One embodiment of the apparatus includes a module generating first and second...
US-8,174,105 Stacked semiconductor package having discrete components
A stacked semiconductor package includes a substrate and a plurality of semiconductor dice stacked on the substrate. Each semiconductor die includes a recess,...
US-8,174,101 Microelectronic devices and microelectronic support devices, and associated assemblies and methods
Microelectronic devices, associated assemblies, and associated methods are disclosed herein. For example, certain aspects of the invention are directed toward a...
US-8,174,081 Fully depleted silicon-on-insulator CMOS logic
A extractor implanted region is used in a silicon-on-insulator CMOS memory device. The extractor region is reversed biased to remove minority carriers from the...
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