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Patent # Description
US-8,125,252 Multi-phase signal generator and method
Multi-phase signal generators and methods for generating multi-phase signals are described. In one embodiment, the clock generator generates quadrature clock...
US-8,125,092 Semiconductor device packages and assemblies
A semiconductor device package includes a carrier, one or more semiconductor devices on the carrier, and a redistribution element above the uppermost of the one...
US-8,125,067 Method for forming terminal of stacked package element and method for forming stacked package
A semiconductor chip module having high degree of freedom in assignment of a circuit to each semiconductor chip and in position of a connection terminal of each...
US-8,125,065 Elimination of RDL using tape base flip chip on flex for die stacking
A flexible film interposer for stacking a flip chip semiconductor die onto a second (bottom) semiconductor die, semiconductor devices and stacked die assemblies...
US-8,125,038 Nanolaminates of hafnium oxide and zirconium oxide
A dielectric film containing a HfO.sub.2/ZrO.sub.2 nanolaminate and a method of fabricating such a dielectric film produce a reliable dielectric layer having an...
US-8,125,003 High-performance one-transistor memory cell
One aspect of this disclosure relates to a memory cell. In various embodiments, the memory cell includes an access transistor having a floating node, and a...
US-8,124,977 Localized compressive strained semiconductor
One aspect of the present subject matter relates to a method for forming strained semiconductor film. According to an embodiment of the method, a crystalline...
US-8,124,956 Phase change memory devices
A phase change material including a high adhesion phase change material formed on a dielectric material and a low adhesion phase change material formed on the...
US-8,124,955 Memory devices and methods of forming the same
Memory devices having a plurality of memory cells, with each memory cell including a phase change material having a laterally constricted portion thereof. The...
US-8,124,545 Methods of etching oxide, reducing roughness, and forming capacitor constructions
The invention includes methods in which one or more components of a carboxylic acid having an aqueous acidic dissociation constant of at least 1.times.10.sup.-6...
US-8,124,541 Etchant gas and a method for removing material from a late transition metal structure
An etchant gas and a method for removing at least a portion of a late transition metal structure. The etchant gas includes PF.sub.3 and at least one oxidizing...
US-8,124,528 Method for forming a ruthenium film
Methods for forming ruthenium films and semiconductor devices such as capacitors that include the films are provided.
US-8,124,491 Container capacitor structure and method of formation thereof
Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of...
US-8,124,456 Methods for securing semiconductor devices using elongated fasteners
Semiconductor device assemblies include elements such as electronic components and substrates secured together by a fastener that includes an elongated portion...
US-8,124,445 Confined resistance variable memory cell structures and methods
Confined resistance variable memory cell structures and methods are described herein. One or more methods of forming a confined resistance variable memory cell...
US-8,124,326 Methods of patterning positive photoresist
A method of patterning positive photoresist includes providing positive photoresist over a substrate. An area of the positive photoresist is exposed to a...
US-8,124,320 Method and apparatus for surface tension control in advanced photolithography
A method and apparatus are used for cleaning and drying a semiconductor wafer. Within a sealable chamber, a wafer having photoresist features thereon is spun...
US-8,123,962 Alternating self-assembling morphologies of diblock copolymers controlled by variations in surfaces
Methods for fabricating sublithographic, nanoscale microstructures arrays including openings and linear microchannels utilizing self-assembling block...
US-8,123,961 Extensions of self-assembled structures to increased dimensions via a "bootstrap" self-templating method
Methods for fabricating sublithographic, nanoscale arrays of openings and linear microchannels utilizing self-assembling block copolymers, and films and devices...
US-8,123,960 Sub-10 nm line features via rapid graphoepitaxial self-assembly of amphiphilic monolayers
Methods for fabricating sublithographic, nanoscale microchannels utilizing an aqueous emulsion of an amphiphilic agent and a water-soluble, hydrogel-forming...
US-8,122,846 Platforms, apparatuses, systems and methods for processing and analyzing substrates
Devices and methods for manufacturing displays, solar panels and other devices using larger size workpieces are provided. The workpiece is rolled into a...
US-8,122,321 Methods of data handling
Methods of data handling include receiving data having a previously-generated error correction code and generating one or more error correction codes for the...
US-8,122,304 JTAG controlled self-repair after packaging
An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the...
US-8,120,954 Method, apparatus, and system for erasing memory
Methods, apparatus, and systems may operate to perform a pre-programming operation on a plurality of multiple level memory cells of a memory device. An example...
US-8,120,952 Memory device with a decreasing dynamic pass voltage for reducing read-disturb effect
The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying sensing voltages to...
US-8,120,951 Memory devices, memory device constructions, constructions, memory device forming methods, current conducting...
Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive...
US-8,120,696 Methods, apparatuses and systems using windowing to accelerate automatic camera functions
Methods, apparatuses and systems are disclosed for accelerating the operation of the automatic functions of an imager, e.g. a camera system. The automatic...
US-8,120,184 Semiconductor constructions and methods of forming layers
The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating...
US-8,120,167 System with semiconductor components having encapsulated through wire interconnects (TWI)
A method for fabricating a semiconductor component with an encapsulated through wire interconnect includes the steps of providing a substrate having a first...
US-8,120,137 Isolation trench structure
Among structures, methods, devices, and systems for isolation trenches, a semiconductor device is provided that includes a substrate and an isolation trench...
US-8,120,134 High-performance diode device structure and materials used for the same
A diode and memory device including the diode, where the diode includes a conductive portion and another portion formed of a first material that has...
US-8,120,124 Ultra thin TCS (SiCl.sub.4) cell nitride for DRAM capacitor with DCS (SiH.sub.2Cl.sub.2) interface seeding layer
A method for forming silicon nitride films on semiconductor devices is provided. In one embodiment of the method, a silicon-comprising substrate is first...
US-8,120,109 Low dose super deep source/drain implant
A semiconductor device for reducing junction capacitance by an additional low dose super deep source/drain implant and a method for its fabrication are...
US-8,120,101 Semiconductor constructions and transistors, and methods of forming semiconductor constructions and transistors
The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the...
US-8,120,083 Polymer-based ferroelectric memory
Apparatus and systems may comprise electrode structures that include two or more dissimilar and abutting metal layers on a surface, some of the electrode...
US-8,120,072 JFET devices with increased barrier height and methods of making same
Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present...
US-8,119,543 Methods of reducing defect formation on silicon dioxide formed by atomic layer deposition (ALD) processes
Methods for reducing and inhibiting defect formation on silicon dioxide formed by atomic layer deposition (ALD) are disclosed. Defect reduction is accomplished...
US-8,119,537 Selective etching of oxides to metal nitrides and metal oxides
A method is provided for selectively etching native oxides or other contaminants to metal nitrides and metal oxides during manufacture of a semiconductor...
US-8,119,514 Cobalt-doped indium-tin oxide films and methods
Methods of forming cobalt-doped indium-tin oxide structures are shown. Properties of structures include transparency, conductivity, and ferromagnetism....
US-8,119,484 DRAM with nanofin transistors
One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second...
US-8,119,483 Methods of forming memory cells
Some embodiments include methods of utilizing polysilazane in forming non-volatile memory cells. The memory cells may be multi-level cells (MLCs). The...
US-8,119,459 Recessed channel negative differential resistance-based memory cell
Disclosed herein is an improved recessed thyristor-based memory cell. The disclosed cell comprises in one embodiment a conductive plug recessed into the bulk of...
US-8,119,440 Method and apparatus providing refractive index structure for a device capturing or displaying images
A transient index stack having an intermediate transient index layer, for use in an imaging device or a display device, that reduces reflection between layers...
US-8,117,520 Error detection for multi-bit memory
Systems, methods, and devices are disclosed, including a device that includes a plurality of data locations, a quantizing circuit coupled to the plurality of...
US-8,117,519 Memory apparatus and method using erasure error correction to reduce power consumption
An error correction circuit coupled to a plurality of memory cells in a memory device includes an error correcting code ("ECC") generator and an ECC controller....
US-8,117,375 Memory device program window adjustment
In one or more embodiments, a memory device is disclosed as having an adjustable programming window having a plurality of programmable levels. The programming...
US-8,117,351 Serial parallel interface for data word architecture
Subject matter disclosed herein relates to techniques involving transitioning serial data into a serial parallel interface.
US-8,116,143 Method of erasing memory cell
An embodiment of a method of erasing a target memory cell includes grounding a selected word line commonly coupled to portions of a row of memory cells...
US-8,116,138 Memory device distributed controller system
A memory device distributed controller circuit distributes memory control functions amongst a plurality of memory controllers. A master controller receives an...
US-8,116,137 Memory cell operation
Embodiments of the present disclosure provide methods, devices, modules, and systems for programming memory cells. One method includes determining a quantity of...
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