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Patent # Description
US-9,489,302 Control arrangements and methods for accessing block oriented nonvolatile memory
A memory system digitally communicates with a host device to provide data storage capacity for the host device. The memory system includes at least one module...
US-9,489,301 Memory systems
Memory systems having a volatile memory, a non-volatile memory arranged in blocks, and a controller coupled to the volatile memory and to the non-volatile...
US-D770,986 Plunger housing body
US-D770,985 Electric contact
US-9,484,536 Memory cells, memory arrays, and methods of forming memory cells and arrays
Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed...
US-9,484,534 Via formation for cross-point memory
Embodiments disclosed herein may relate to electrically conductive vias in cross-point memory array devices. In an embodiment, the vias may be formed using a...
US-9,484,378 Semiconductor devices including back-side integrated circuitry
Semiconductor devices may include a semiconductor substrate comprising at least one of transistors and capacitors may be located at an active surface of the...
US-9,484,326 Apparatuses having stacked devices and methods of connecting dice stacks
Various embodiments include apparatuses having stacked devices and methods of forming dice stacks on an interface die. In one such apparatus, a dice stack...
US-9,484,225 Method for packaging circuits
A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base...
US-9,484,196 Semiconductor structures including liners comprising alucone and related methods
A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and...
US-9,484,101 Methods of programming memories
Methods of programming memories include applying a first plurality of programming pulses to the group of memory cells to program first data to the group of...
US-9,484,100 Memory devices having source lines directly coupled to body regions and methods
Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body...
US-9,484,088 Permutational memory cells
Various embodiments include at least one resistance change memory (RCM) cell, In one embodiment, three or more pairs of electrical contacts are coupled to the...
US-9,484,074 Current mode sense amplifier with load circuit for performance stability
Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled...
US-9,484,070 Apparatuses supporting multiple interface types and methods of operating the same
Apparatuses supporting multiple interface types and methods operating the same are described. One such method can include providing, to a memory device, a first...
US-9,483,632 Intelligent controller system and method for smart card memory modules
A storage device contains a smart-card device and a memory device, both of which are accessed though a controller. The storage device may be used in the same...
US-9,483,399 Sub-OS virtual memory management layer
A binary memory image in system is modified. The system may or may not already have virtual memory management enabled. Virtual memory management is enabled...
US-9,483,370 Error detection/correction based memory management
The present disclosure includes methods, devices, and systems for error detection/correction based memory management. One embodiment includes performing a read...
US-9,483,203 Temporary mirroring, logical segregation, and redundant programming or addressing for solid state drive operation
The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes mirroring programming operations such that...
US-9,479,361 Method and apparatus for selecting an operating mode based on a determination of the availability of internal...
A system and method to operate an electronic device, such as a memory chip, with an output driver circuit that is configured to include an ODT (On-Die...
US-9,479,167 Apparatuses and methods for line charge sharing
Apparatuses and methods for charge sharing, between signal lines are disclosed. An example apparatus may include first and second lines and a charge sharing...
US-9,479,151 Apparatuses and methods for controlling delay circuits during an idle state to reduce degradation of an...
Delay circuits may be controlled by apparatuses and methods during an idle state to reduce degradation of an electrical characteristic. An example apparatus...
US-9,478,740 Switching device structures and methods
Switching device structures and methods are described herein. A switching device can include a vertical stack comprising a material formed between a first and a...
US-9,478,735 Magnetic tunnel junctions
Some embodiments include a magnetic tunnel junction which has a conductive first magnetic electrode containing magnetic recording material, a conductive second...
US-9,478,550 Arrays of vertically-oriented transistors, and memory arrays including vertically-oriented transistors
An array includes vertically-oriented transistors. The array includes rows of access lines and columns of data/sense lines. Individual of the rows include an...
US-9,478,502 Device identification assignment and total device number detection
Various embodiments comprise apparatuses to assign a respective one of a sequence of unique device identification (ID) values to each die in a stacked device....
US-9,478,497 Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n.gtoreq.2, tiers of stacked mandrels are...
US-9,478,282 State determination in resistance variable memory
An evaluation signal is applied to a memory cell in an array of resistance variable memory cells. The evaluation signal is configured to cause the memory cell...
US-9,478,270 Data paths using a first signal to capture data and a second signal to output data and methods for providing data
Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register....
US-9,478,262 Semiconductor device including input/output circuit
Disclosed here is an apparatus that comprises a data terminal, a data output circuit including a plurality of output buffers coupled in common to the data...
US-9,477,863 Systems and methods to determine motion parameters using RFID tags
Systems and methods to determine motion parameters of physical objects using radio frequency identification (RFID) tags attached to the objects. In one...
US-9,477,636 Memory having internal processors and data communication methods in memory
Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may...
US-9,477,616 Devices, systems, and methods of reducing chip select
Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a...
US-9,477,587 Method and apparatus for a volume management system in a non-volatile memory device
Embodiments for partitioning a non-volatile memory device is described. In one embodiment a memory system includes a first addressable range of memory blocks...
US-9,476,934 Inspection apparatus and inspection method for inspecting a wiring board
An inspection apparatus for inspecting a wiring board having an opposing electrode facing an upper face of the wiring board, a capacitance meter electrically...
US-9,473,146 Apparatuses and methods for low power counting circuits
Apparatuses and methods for low power counting circuits are described herein. An example apparatus may include a frequency divider configured to receive an...
US-9,472,663 N-type field effect transistors, arrays comprising N-type vertically-oriented transistors, methods of forming...
An n-type field effect transistor includes silicon-comprising semiconductor material comprising a pair of source/drain regions having a channel region...
US-9,472,560 Memory cell and an array of memory cells
A memory cell includes a first electrode and a second electrode. A select device and a programmable device are in series with each other between the first and...
US-9,472,542 DRAM arrays, semiconductor constructions and DRAM array layouts
Some embodiments include a DRAM array layout. Wordlines extend along a first direction, and bitlines extend along a second direction that crosses the first...
US-9,472,518 Semiconductor structures including carrier wafers and methods of using such semiconductor structures
A semiconductor structure comprising a carrier wafer and a device wafer. The carrier wafer comprises trenches sized and configured to receive conductive pillars...
US-9,472,461 Double gated 4F2 dram CHC cell and methods of fabricating the same
A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein...
US-9,472,287 Local self-boost using a plurality of cut-off cells on a single side of a string of memory cells
Methods for local self-boost of a selected memory cell channel, memory devices, and systems are disclosed. One such method generates a cut-off channel under...
US-9,472,265 Apparatuses and methods for performing logical operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an...
US-9,472,264 Semiconductor memory device having sense amplifier
An apparatus includes a memory cell, a bit line coupled to the memory cell, and a sense amplifier configured to amplify a data signal on the bit line read out...
US-9,472,253 Semiconductor device including spiral data path
A semiconductor device disclosed in this disclosure includes a first terminal formed above a first surface of a semiconductor substrate, a second terminal...
US-9,472,252 Apparatuses and methods for improving retention performance of hierarchical digit lines
Apparatuses and methods for improving retention performance of hierarchical digit lines are disclosed herein. An example apparatus may include a first digit...
US-9,472,244 Apparatus power control
The present disclosure includes apparatuses and methods for apparatus power control. A number of embodiments include determining a power profile for each of a...
US-9,471,425 Data conditioning to improve flash memory reliability
Methods for managing data stored in a memory device facilitate managing utilization of memory of different densities. The methods include reading first data...
US-9,471,290 Utilizing special purpose elements to implement a FSM
Apparatus, systems, and methods for a compiler are described. One such compiler generates machine code corresponding to a set of elements including a general...
US-9,471,087 Apparatuses and methods for providing clock signals
Apparatuses and methods for providing clock signals are described herein. An example apparatus may include a clock generator circuit. The clock generator...
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