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Patent # Description
US-1,016,3928 Memory having memory cell string and coupling components
Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the...
US-1,016,3917 Cell disturb prevention using a leaker device to reduce excess charge from an electronic device
Various embodiments comprise apparatuses and methods of forming the apparatuses. In one embodiment, an exemplary apparatus includes a plurality of memory cells....
US-1,016,3909 Methods for fabricating a semiconductor memory device
A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas...
US-1,016,3908 Array of conductive lines individually extending transversally across and elevationally over a mid-portion of...
An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material...
US-1,016,3906 Circuit and layout for single gate type precharge circuit for data lines in memory device
Some embodiments include apparatus and methods using a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion...
US-1,016,3893 Apparatus containing circuit-protection devices
Apparatus including an array of memory cells may include circuit-protection devices that may include first and second circuit-protection units, a first gate...
US-1,016,3840 Methods of fluxless micro-piercing of solder balls, and resulting devices
A method of establishing conductive connections is disclosed. The method includes providing an integrated circuit die having a plurality of solder balls each of...
US-1,016,3830 Bonding pads with thermal pathways
Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal...
US-1,016,3826 Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a system comprises a...
US-1,016,3755 Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths
Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a...
US-1,016,3693 Methods for processing semiconductor dice and fabricating assemblies incorporating same
A method for processing semiconductor dice comprises removing material from a surface of a semiconductor wafer to create a pocket surrounded by a sidewall at a...
US-1,016,3685 Methods of forming one or more covered voids in a semiconductor substrate
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
US-1,016,3655 Through substrate via liner densification
Apparatuses and methods are disclosed herein for densification of through substrate insulating liners. An example method may include forming a through substrate...
US-1,016,3514 Methods of operating a memory during a programming operation
Methods of operating a memory include increasing a voltage applied to a first access line from a first voltage to a second voltage higher than the first voltage...
US-1,016,3507 Apparatuses and methods including memory access in cross point memory
Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch...
US-1,016,3506 Apparatuses including memory cells and methods of operation of same
Disclosed herein is a memory cell including a memory element and a selector device. The memory cell may be programmed with a programming pulse having a first...
US-1,016,3501 Apparatuses, memories, and methods for address decoding and selecting an access line
Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address...
US-1,016,3498 Reflow protection
Devices and techniques to reduce corruption of preloaded data during assembly are disclosed herein. A memory device can perform operations to store received...
US-1,016,3486 Command signal clock gating
A semiconductor device includes a clock gating tree comprising a first clock gating stage and a second clock gating stage. The first clock gating stage is...
US-1,016,3483 Dynamic reference voltage determination
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first value may be written to a first memory cell and a second...
US-1,016,3482 Ground reference scheme for a memory cell
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be employed in a digit line...
US-1,016,3481 Offset cancellation for latching in a memory device
Methods, systems, and devices for offset cancellation for latching in memory devices are described. A memory device may include a sense component comprising a...
US-1,016,3480 Periphery fill and localized capacitance
Methods, systems, and devices for periphery fill and localized capacitance are described. A memory array may be fabricated with certain containers connected to...
US-1,016,3472 Apparatuses and methods for memory operations having variable latencies
Apparatuses and methods for performing memory operations are described. In an example apparatus, a memory is configured to receive a memory instruction and...
US-1,016,3469 System and method for write data bus control in a stacked memory device
Apparatuses and methods for transmitting data between a plurality of chips are described. An example apparatus includes: a first chip, wherein the first chip...
US-1,016,3467 Multiple endianness compatibility
Examples of the present disclosure provide apparatuses and methods for multiple endianness compatibility. An example method comprises receiving a plurality of...
US-1,016,2992 Systems and methods to determine kinematical parameters using RFID tags
Systems and methods to determine kinematical parameters of physical objects using radio frequency identification (RFID) tags attached to the objects. In one...
US-1,016,2862 Devices, systems, and methods to synchronize simultaneous DMA parallel processing of a single data stream by...
Disclosed are methods and devices, among which is a system that includes a device that includes one or more pattern-recognition processors in a ...
US-1,016,2781 Logic component switch
The present disclosure relates generally to semiconductor memory and methods, and more particularly, to apparatuses, and methods for controlling logic die...
US-1,016,2569 Non-volatile memory module architecture to support memory error correction
Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first...
US-1,016,2557 Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers
Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers are described. In one such method, where memory...
US-1,016,2556 Multi-partitioning of memories
Various embodiments comprise devices and methods to manage multiple memory types and reconfigure partitions in a memory device as directed by a host. In one...
US-1,016,2526 Logical address history management in memory device
Some embodiments include apparatuses and methods including memory cells and a control unit to store information in a portion of the memory cells and to generate...
US-1,016,2406 Systems and methods for frequency mode detection and implementation
The systems and methods provided herein identify a command acquisition mode from a plurality of command acquisition modes of a command interface of a memory...
US-1,016,2377 Apparatuses and methods for providing reference voltages
A reference voltage generator is disclosed that may provide a plurality of reference voltages. A reference voltage generator may include a voltage divider, a...
US-1,016,2005 Scan chain operations
A number of embodiments include an apparatus comprising a memory array including a first memory bank and a second memory bank and a serializer/de-serializer...
US-1,015,8071 Semiconductor devices, memory devices, and related methods
Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the...
US-1,015,7965 Cross-point memory and methods for fabrication of same
The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same....
US-1,015,7933 Integrated structures including material containing silicon, nitrogen, and at least one of carbon, oxygen,...
Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive...
US-1,015,7926 Memory cells and memory arrays
Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors....
US-1,015,7913 Methods of forming an array comprising pairs of vertically opposed capacitors and arrays comprising pairs of...
A method of forming an array comprising pairs of vertically opposed capacitors comprises forming an upwardly-open conductive lining in individual capacitor...
US-1,015,7841 Construction of integrated circuitry and a method of forming an elevationally-extending conductor laterally...
A method includes forming insulative material along the opposing sides of a conductive via and a conductive line in a vertical cross-section comprising forming...
US-1,015,7830 3D interconnect multi-die inductors with through-substrate via cores
A semiconductor device having a first die and a second die is provided. The first die of the device includes a first surface and a through-substrate via (TSV)...
US-1,015,7788 Self-aligned interconnection for integrated circuits
Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one...
US-1,015,7769 Semiconductor devices including a diode structure over a conductive strap and methods of forming such...
Semiconductor devices including at least one diode over a conductive strap. The semiconductor device may include at least one conductive strap over an insulator...
US-1,015,7743 Methods of patterning a target layer
A method of forming patterns includes the steps of providing a substrate on which a target layer and a hard mask layer are formed; forming a plurality of first...
US-1,015,7673 Resistive random access memory having multi-cell memory bits
Some embodiments include methods of storing and retrieving data for an RRAM array. The array is subdivided into a plurality of memory bits, with each memory bit...
US-1,015,7670 Apparatuses including memory cells and methods of operation of same
Disclosed herein is a memory cell including a memory element and a selector device. The memory cell may be programmed with a programming pulse having a first...
US-1,015,7669 Method of storing and retrieving information for a resistive random access memory (RRAM) with multi-memory...
Some embodiments include methods of storing and retrieving data for an RRAM array. The array is subdivided into a plurality of memory bits, with each memory bit...
US-1,015,7667 Mixed cross point memory
Methods, systems, and devices for multi-deck memory arrays are described. A multi-deck memory device may include a memory array with a cell having a...
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