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Patent # Description
US-1,006,2745 Methods of forming an array of capacitors, methods of forming an array of memory cells individually comprising...
A method of forming an array of capacitors comprises forming elevationally-extending and longitudinally-elongated capacitor electrode lines over a substrate....
US-1,006,2708 Memory blocks and related devices and methods
Vertical memory blocks for semiconductor devices include a memory cell region including an array of memory cell pillars and at least one via region including a...
US-1,006,2703 Methods of forming a ferroelectric memory cell
A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation....
US-1,006,2679 Apparatuses and methods for forming die stacks
Apparatuses and methods for forming die stacks are disclosed herein. An example method includes dispensing a temporary adhesive onto a substrate, placing a base...
US-1,006,2678 Proximity coupling of interconnect packaging systems and methods
Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed...
US-1,006,2677 Back-to-back solid state lighting devices and associated methods
Solid state lights (SSLs) including a back-to-back solid state emitters (SSEs) and associated methods are disclosed herein. In various embodiments, an SSL can...
US-1,006,2667 Stacked microfeature devices and associated methods
Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second...
US-1,006,2634 Semiconductor die assembly having heat spreader that extends through underlying interposer and related technology
A semiconductor die assembly in accordance with an embodiment of the present technology includes a first semiconductor die, a package substrate underlying the...
US-1,006,2608 Semiconductor devices comprising nickel- and copper-containing interconnects
A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate...
US-1,006,2595 Systems and methods for wafer alignment
Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations....
US-1,006,2441 Determining data states of memory cells
Methods of operating a memory include determining a respective raw data value for each memory cell of a plurality of memory cells; determining the numbers of...
US-1,006,2433 Apparatuses and methods of reading memory cells
A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (.sub.VTH) region between a first state...
US-1,006,2432 Resistive memory sensing
The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a...
US-1,006,2426 Field effect transistor constructions with gate insulator having local regions radially there-through that have...
A field effect transistor construction includes a semiconductive channel core. A source/drain region is at opposite ends of the channel core. A gate is...
US-1,006,2420 Memory devices having special mode access using a serial message
A memory device includes a serial interface controller that receives and operates using a serial message having a format that includes a command field of the...
US-1,006,1709 Systems and methods for accessing memory
Methods of mapping memory cells to applications, methods of accessing memory cells, systems, and memory controllers are described. In some embodiments, a memory...
US-1,006,1699 Multiple data channel memory module architecture
According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a...
US-1,006,1643 Estimating an error rate associated with memory
The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored...
US-1,006,1590 Generating and executing a control flow
The present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device...
US-1,006,1541 Systems and methods for refreshing a memory bank while accessing another memory bank using a shared address path
A system includes multiple memory banks that store data. The system also includes an address path coupled to the memory banks that provides a row address to the...
US-1,005,8705 Antenna assembly
An antenna assembly includes a metal layer configured to emit linearly polarized electromagnetic energy to a receiving antenna implanted underneath a subject's...
US-1,005,7845 Control system for information processing apparatus using portable terminal, portable terminal, and control...
The present invention enables a processing to be executed by the closest information processing apparatuses selected by a portable terminal without exclusive...
US-1,005,6688 Patch antenna assembly
A patch antenna assembly that includes a signal metal layer configured to emit linearly polarized electromagnetic energy to a receiving antenna implanted up to...
US-1,005,6386 Memory cells and memory arrays
Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first...
US-1,005,6359 Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated...
Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked...
US-1,005,6338 Methods of forming semiconductor packages including molding semiconductor chips of the semiconductor packages
Some embodiments of the present disclosure disclose a method for forming semiconductor packages. The method includes disposing a plurality of semiconductor...
US-1,005,6157 Memory apparatus with post package repair
Apparatuses for memory repair for a memory device are described. An example apparatus includes: a non-volatile storage element that stores information; a...
US-1,005,6154 Apparatuses and methods for flexible fuse transmission
Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each...
US-1,005,6149 Semiconductor memory column decoder device and method
Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in...
US-1,005,6137 Apparatuses and methods for accessing memory cells
Apparatuses and methods for accessing a memory cell are described. An example apparatus includes a first voltage circuit coupled to a node and is configured to...
US-1,005,6129 Cell bottom node reset in a memory array
Methods, systems, and devices for cell bottom node reset in a memory array are described. The memory array may include a plurality of ferroelectric memory cells...
US-1,005,6122 Apparatuses and methods for performing compare operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can...
US-1,005,6120 Interconnection for memory electrodes
Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central...
US-1,005,5293 High performance memory controller
A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an...
US-1,005,5285 Physical page, logical page, and codeword correspondence
The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a...
US-1,005,5196 Division operations for memory
Examples of the present disclosure provide apparatuses and methods for performing division operations in a memory. An example apparatus comprises a first...
US-1,005,5180 Printer setting state updating system
The invention facilitates a setting state updating operation of the printer. An updating system of a setting state of a printer comprises an application...
US-1,005,0084 Replacement materials processes for forming cross point memory
Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line...
US-1,005,0049 Apparatuses including memory arrays with source contacts adjacent edges of sources
Various apparatuses, including three-dimensional (3D) memory devices and systems including the same, are described herein. In one embodiment, a 3D memory device...
US-1,005,0023 Solid state lighting device with different illumination parameters at different regions of an emitter array
Solid state lighting (SSL) devices and methods of manufacturing such devices. One embodiment of an SSL device comprises a support and an emitter array having a...
US-1,004,9874 Self-assembled nanostructures including metal oxides and semiconductor structures comprised thereof
A self-assembled nanostructure comprises first domains and second domains. The first domains comprise a first block of a block copolymer material and an...
US-1,004,9756 Memory devices that apply a programming potential to a memory cell in a string coupled to a source and data...
A first string of memory cells, including a selected memory cell, and a second string of memory cells are coupled to a common data line and a common source. The...
US-1,004,9750 Methods including establishing a negative body potential in a memory cell
Apparatus and methods of operating such apparatus include establishing a negative potential in a body of a memory cell prior to initiating a sensing operation...
US-1,004,9737 Memory cell architecture for multilevel cell programming
Methods, systems, and devices for operating and forming a multilevel memory cell and array are described. A multilevel memory cell includes two or more binary...
US-1,004,9722 Apparatuses and methods for a memory device with dual common data I/O lines
Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O...
US-1,004,9721 Apparatuses and methods for in-memory operations
The present disclosure includes apparatuses and methods for in-memory operations. An example apparatus includes a memory device including a plurality of...
US-1,004,9713 Full bias sensing in a memory array
Methods, systems, and apparatuses for full bias sensing in a memory array are described. Various embodiments of an access operation of a cell in a array may be...
US-1,004,9707 Shifting data
The present disclosure includes apparatuses and methods related to shifting data. A number of embodiments of the present disclosure include an apparatus...
US-1,004,9705 Memories having select devices between access lines and in memory cells formed of a same type of circuit element
Memories may include a first select device connected between a first access line and a second access line, and a plurality of memory cells. Each memory cell of...
US-1,004,9207 Methods of operating storage systems including encrypting a key salt
A method of operating a storage system includes using the device driver to combine a password, the key salt, and the number of iterations to generate a primary...
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