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Patent # Description
US-9,515,261 Memory cells and methods of making memory cells
Some embodiments include a memory cell having a data storage region between a pair of conductive structures. The data storage region is configured to support a...
US-9,515,151 Gettering agents in memory charge storage structures
Methods of forming memory cells including a charge storage structure having a gettering agent therein can be useful for non-volatile memory devices. Providing...
US-9,515,046 Stacked microfeature devices and associated methods
Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second...
US-9,515,002 Bonding pads with thermal pathways
Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal...
US-9,514,976 Trench isolation implantation
Embodiments of the disclosure include a shallow trench isolation structure having a dielectric material with energetic species implanted to a predetermined...
US-9,514,975 Semiconductor with through-substrate interconnect
Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor...
US-9,514,905 Fuses, and methods of forming and using fuses
Some embodiments include a fuse having a tungsten-containing structure directly contacting an electrically conductive structure. The electrically conductive...
US-9,514,838 Apparatus including memory system controllers and related methods for memory management using block tables
Memory controllers can include a switch and non-volatile memory control circuitry including channel control circuits coupled to the switch. The channel control...
US-9,514,829 Access line management in a memory device
Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device...
US-9,514,809 Memory array plane select
Memory arrays and methods of forming the same are provided. An example memory array can include at least one plane having a plurality of memory cells arranged...
US-9,514,063 Secure compact flash
Methods and apparatus are provided, such as a memory card with a processor and nonvolatile memory coupled thereto. The nonvolatile memory has a secure area...
US-9,513,992 Method and apparatus to perform concurrent read and write memory operations
Subject matter disclosed herein relates to read and write processes of a memory device. During a write process to a particular partition in a memory array, a...
US-9,513,912 Memory controllers
Methods and controllers for executing an instruction set are provided. In one such method, executing an instruction set includes executing an instruction of one...
US-9,509,535 Multi-level signaling
Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits....
US-9,509,312 Boolean logic in a state machine lattice
Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic...
US-9,508,931 Memory cells and methods of forming memory cells
Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the...
US-9,508,735 Methods and apparatuses having strings of memory cells and select gates with double gates
An apparatus, a method, and a system are disclosed. The apparatus includes a string of memory cells coupled to a select gate drain transistor that has a front...
US-9,508,686 Semiconductor device assembly with package interconnect extending into overlying spacer material, and...
Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material...
US-9,508,628 Semiconductor substrates with unitary vias and via terminals, and associated systems and methods
Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a...
US-9,508,591 Stair step formation using at least two masks
Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a...
US-9,508,440 Program and read trim setting
A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device...
US-9,508,427 Apparatuses and methods including supply current in memory
Some embodiments include apparatuses and methods having first conductive lines, second conductive lines, a memory array including memory cells, each of the...
US-9,508,426 Program-disturb management for phase change memory
Methods, systems, and devices related to memory, including read or write performance of a phase change memory, are described. A plurality of memory cells of a...
US-9,508,417 Methods and apparatuses for controlling timing paths and latency based on a loop delay
Apparatuses and methods for controlling timing circuit locking and/or latency during a change in clock frequency (e.g. gear down mode) are described herein. An...
US-9,508,409 Apparatuses and methods for implementing masked write commands
Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and...
US-9,508,407 Wiring configuration of a bus system and power wires in a memory chip
Devices and circuits for wiring configurations of a bus system and power supply wires in a memory chip with improved power efficiencies. The effective...
US-9,507,104 Apparatus providing simplified alignment of optical fiber in photonic integrated circuits
A structure for optically aligning an optical fiber to a photonic device and method of fabrication of same. The structure optically aligns an optical fiber to...
US-9,503,066 Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals
Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes...
US-9,503,019 Apparatuses and methods for providing oscillation signals
Apparatuses and methods are disclosed for oscillators that are substantially insensitive to supply voltage variations. In one such example apparatus, a...
US-9,502,650 Memory including a selector switch on a variable resistance memory cell
Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a...
US-9,502,642 Magnetic tunnel junctions, methods used while forming magnetic tunnel junctions, and methods of forming...
A method used while forming a magnetic tunnel junction comprises forming non-magnetic tunnel insulator material over magnetic electrode material. The tunnel...
US-9,502,516 Recessed access devices and gate electrodes
Recessed access transistor devices used with semiconductor devices may include gate electrodes having materials with multiple work functions, materials that are...
US-9,502,369 Semiconductor devices and packages
Semiconductor device packages include first and second semiconductor dice in a facing relationship. At least one group of solder bumps is substantially along a...
US-9,502,314 Method for manufacturing tested apparatus and method for manufacturing system including tested apparatus
Disclosed herein is a method for manufacturing a tested apparatus that includes forming a stacked structure that includes a plurality of first semiconductor...
US-9,502,256 ZrAION films
Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium aluminum oxynitride (ZrAlON) for use in a variety of electronic devices....
US-9,502,125 Concurrently reading first and second pages of memory cells having different page addresses
In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The...
US-9,502,101 Two-part programming methods
A first memory cell is programmed to a first level using a first set of program pulses within a first programming voltage range. A second memory cell to be...
US-9,502,083 Output buffer circuit with low sub-threshold leakage current
A device includes a cutting circuit that is coupled between power supply lines in series with first and second output circuits which drive an output terminal in...
US-9,501,705 Methods and apparatuses for reducing power consumption in a pattern recognition processor
Apparatuses and methods are provided for reducing power consumption in a pattern-recognition processor. A power control circuit may be coupled to a block of...
US-9,501,222 Protection zones in virtualized physical addresses for reconfigurable memory systems using a memory abstraction
Systems and methods define a memory system using an abstracted memory protocol that enables virtual to physical mapping of memory address requests at an...
US-9,501,131 Methods and systems for power management in a pattern recognition processing system
A device includes a state machine. The state machine includes a plurality of blocks, where each of the blocks includes a plurality of rows. Each of these rows...
US-9,499,907 Methods of forming material over a substrate and methods of forming capacitors
A method of forming a material over a substrate includes performing at least one iteration of the following temporally separated ALD-type sequence. First, an...
US-9,496,495 Memory cells and methods of forming memory cells
Some embodiments include a memory cell having a first electrode, and an intermediate material over and directly against the first electrode. The intermediate...
US-9,496,491 Methods of forming a metal chalcogenide material and related methods of forming a memory cell
A method of forming a metal chalcogenide material. The method comprises introducing a metal precursor and a chalcogenide precursor into a chamber, and reacting...
US-9,496,454 Solid state optoelectronic device with plated support substrate
A vertical solid state lighting (SSL) device is disclosed. In one embodiment, the SSL device includes a light emitting structure formed on a growth substrate....
US-9,496,355 Conductive nanoparticles
Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge storage units in...
US-9,496,050 Methods and apparatuses for stacked device testing
Various embodiments include apparatus, systems, and methods having multiple dies arranged in a stack in which the dies or a logic chip in communication with the...
US-9,496,023 Comparison operations on logical representations of values in memory
One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first...
US-9,490,631 Over-limit electrical condition protection circuits and methods
Apparatuses and methods for protecting a circuit from an over-limit electrical condition are disclosed. One example apparatus includes a protection circuit...
US-9,490,425 Semiconductor constructions and memory arrays
Some embodiments include semiconductor constructions having an electrically conductive interconnect with an upper surface, and having an electrically conductive...
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