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Patent # Description
US-8,120,696 Methods, apparatuses and systems using windowing to accelerate automatic camera functions
Methods, apparatuses and systems are disclosed for accelerating the operation of the automatic functions of an imager, e.g. a camera system. The automatic...
US-8,120,184 Semiconductor constructions and methods of forming layers
The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating...
US-8,120,167 System with semiconductor components having encapsulated through wire interconnects (TWI)
A method for fabricating a semiconductor component with an encapsulated through wire interconnect includes the steps of providing a substrate having a first...
US-8,120,137 Isolation trench structure
Among structures, methods, devices, and systems for isolation trenches, a semiconductor device is provided that includes a substrate and an isolation trench...
US-8,120,134 High-performance diode device structure and materials used for the same
A diode and memory device including the diode, where the diode includes a conductive portion and another portion formed of a first material that has...
US-8,120,124 Ultra thin TCS (SiCl.sub.4) cell nitride for DRAM capacitor with DCS (SiH.sub.2Cl.sub.2) interface seeding layer
A method for forming silicon nitride films on semiconductor devices is provided. In one embodiment of the method, a silicon-comprising substrate is first...
US-8,120,109 Low dose super deep source/drain implant
A semiconductor device for reducing junction capacitance by an additional low dose super deep source/drain implant and a method for its fabrication are...
US-8,120,101 Semiconductor constructions and transistors, and methods of forming semiconductor constructions and transistors
The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the...
US-8,120,083 Polymer-based ferroelectric memory
Apparatus and systems may comprise electrode structures that include two or more dissimilar and abutting metal layers on a surface, some of the electrode...
US-8,120,072 JFET devices with increased barrier height and methods of making same
Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present...
US-8,119,543 Methods of reducing defect formation on silicon dioxide formed by atomic layer deposition (ALD) processes
Methods for reducing and inhibiting defect formation on silicon dioxide formed by atomic layer deposition (ALD) are disclosed. Defect reduction is accomplished...
US-8,119,537 Selective etching of oxides to metal nitrides and metal oxides
A method is provided for selectively etching native oxides or other contaminants to metal nitrides and metal oxides during manufacture of a semiconductor...
US-8,119,514 Cobalt-doped indium-tin oxide films and methods
Methods of forming cobalt-doped indium-tin oxide structures are shown. Properties of structures include transparency, conductivity, and ferromagnetism....
US-8,119,484 DRAM with nanofin transistors
One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second...
US-8,119,483 Methods of forming memory cells
Some embodiments include methods of utilizing polysilazane in forming non-volatile memory cells. The memory cells may be multi-level cells (MLCs). The...
US-8,119,459 Recessed channel negative differential resistance-based memory cell
Disclosed herein is an improved recessed thyristor-based memory cell. The disclosed cell comprises in one embodiment a conductive plug recessed into the bulk of...
US-8,119,440 Method and apparatus providing refractive index structure for a device capturing or displaying images
A transient index stack having an intermediate transient index layer, for use in an imaging device or a display device, that reduces reflection between layers...
US-8,117,520 Error detection for multi-bit memory
Systems, methods, and devices are disclosed, including a device that includes a plurality of data locations, a quantizing circuit coupled to the plurality of...
US-8,117,519 Memory apparatus and method using erasure error correction to reduce power consumption
An error correction circuit coupled to a plurality of memory cells in a memory device includes an error correcting code ("ECC") generator and an ECC controller....
US-8,117,375 Memory device program window adjustment
In one or more embodiments, a memory device is disclosed as having an adjustable programming window having a plurality of programmable levels. The programming...
US-8,117,351 Serial parallel interface for data word architecture
Subject matter disclosed herein relates to techniques involving transitioning serial data into a serial parallel interface.
US-8,116,143 Method of erasing memory cell
An embodiment of a method of erasing a target memory cell includes grounding a selected word line commonly coupled to portions of a row of memory cells...
US-8,116,138 Memory device distributed controller system
A memory device distributed controller circuit distributes memory control functions amongst a plurality of memory controllers. A master controller receives an...
US-8,116,137 Memory cell operation
Embodiments of the present disclosure provide methods, devices, modules, and systems for programming memory cells. One method includes determining a quantity of...
US-8,116,135 Non-volatile memory cell read failure reduction
The present disclosure includes various method, device, and system embodiments for reducing non-volatile memory cell read failures. One such method embodiment...
US-8,116,115 Multilevel phase change memory operation
Methods, devices, and systems associated with multilevel phase change memory cells are described herein. One or more embodiments of the present disclosure...
US-8,115,854 Imager method and apparatus employing photonic crystals
An image sensor and a method of forming an image sensor. The image sensor includes an array of pixel cells at a surface of a substrate. Each pixel cell has a...
US-8,115,841 Method, apparatus and system providing an image sensor having pixels with multiple exposures, diodes and gain...
A method, apparatus and system are described providing a high dynamic range pixel. Operating conditions, including integration time and sensitivity of different...
US-8,115,637 Systems and methods to selectively connect antennas to receive and backscatter radio frequency signals
Systems and methods to selectively attach and control antennas via diodes and current sources. In one embodiment, a system includes: an RFID reader having a...
US-8,115,528 Method and apparatus for output data synchronization with system clock
A circuit, delay-locked loop, memory device, system and method of synchronizing a clock are described. A circuit generally includes a delay line configured to...
US-8,115,296 Electronic device package
Various embodiments for molding tools for moisture-resistant image sensor packaging structures and methods of assembly are disclosed. Image sensor packages of...
US-8,115,243 Surround gate access transistors with grown ultra-thin bodies
A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid...
US-8,115,112 Interposer substrates and semiconductor device assemblies and electronic systems including such interposer...
Chip-scale packages and assemblies thereof are disclosed. The chip-scale package includes a core member of a metal or alloy having a recess for at least...
US-8,114,763 Tantalum aluminum oxynitride high-K dielectric
Electronic apparatus and methods of forming the electronic apparatus may include a tantalum aluminum oxynitride film for use in a variety of electronic systems...
US-8,114,753 Buried decoupling capacitors, devices and systems including same, and methods of fabrication
A buried decoupling capacitor apparatus and method are provided. According to various embodiments, a buried decoupling capacitor apparatus includes a...
US-8,114,737 Methods of forming memory cells on pillars and memories with memory cells on pillars
Methods of fabricating memory are disclosed. For example, a method includes fabricating rows of memory cells on pillars separated by isolation regions...
US-8,114,718 Antiblooming imaging apparatus, systems, and methods
Apparatus, systems, and methods are described to assist in reducing dark current in an active pixel sensor. In various embodiments, a potential barrier...
US-8,114,573 Topography based patterning
A mask having features formed by self-organizing material, such as diblock copolymers, is formed on a partially fabricated integrated circuit. Initially, a...
US-8,114,301 Graphoepitaxial self-assembly of arrays of downward facing half-cylinders
Methods for fabricating sublithographic, nanoscale microstructures in line arrays utilizing self-assembling block copolymers, and films and devices formed from...
US-8,114,300 Multi-layer method for formation of registered arrays of cylindrical pores in polymer films
Methods for fabricating sublithographic, nanoscale polymeric microstructures utilizing self-assembling block copolymers, and films and devices formed from these...
US-8,114,219 Systems and methods for forming metal oxide layers
A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or...
US-8,113,066 Chuck-integrated force-measuring system
A chuck-integrated force-measuring system for determining cutting forces at the cutting tool tip of a rotating tool, for example a drill or milling cutter...
US-8,112,578 Low power, hash-content addressable memory architecture
A comparand word is input to a plurality of hash circuits, with each hash circuit responding to a different portion of the comparand word. The hash circuits...
US-8,112,573 Non-volatile memory with erase block state indication in a subset of sectors of erase block
An improved Flash memory device with a distributed erase block management (EBM) scheme is detailed that enhances operation and helps minimize write fatigue of...
US-8,111,965 Waveguide for thermo optic device
A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the...
US-8,111,580 Multi-phase duty-cycle corrected clock signal generator and memory having same
Memories, multi-phase clock signal generators, and methods for generating multi-phase duty cycle corrected clock signals are disclosed. For example, one such...
US-8,111,578 Memory devices having redundant arrays for repair
Apparatus and methods are disclosed, such as those involving a memory device. One such memory device includes a memory array including a sub-array that includes...
US-8,111,570 Devices and methods for a threshold voltage difference compensated sense amplifier
Embodiments are described for a voltage compensated sense amplifier. One such sense amplifier includes a pair of digit line nodes respectively coupled to a pair...
US-8,111,555 NAND step voltage switching method
Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a...
US-8,111,534 Rank select using a global select pin
Methods, memory devices, and systems are disclosed, such as those for accessing a memory circuit through the use of reduced external pins. With one such system,...
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