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Patent # Description
US-8,089,142 Methods and apparatus for a stacked-die interposer
An improved stacked-die package includes an interposer which improves the manufacturability of the package. A semiconductor package includes a package substrate...
US-8,089,128 Transistor gate forming methods and integrated circuits
A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal...
US-8,089,123 Semiconductor device comprising transistor structures and methods for forming same
A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some...
US-8,088,691 Selective etch chemistries for forming high aspect ratio features and associated structures
An interlevel dielectric layer, such as a silicon oxide layer, is selectively etched using a plasma etch chemistry including a silicon species and a halide...
US-8,088,659 Method of forming capacitors
High dielectric films of mixed transition metal oxides of titanium and tungsten, or titanium and tantalum, are formed by sequential chemical vapor deposition...
US-8,088,643 Resistance variable memory device with nanoparticle electrode and method of fabrication
A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a...
US-8,088,551 Methods of utilizing block copolymer to form patterns
Some embodiments include methods of forming patterns in which a block copolymer-containing composition is formed over a substrate, and is then patterned to form...
US-8,088,293 Methods of forming reticles configured for imprint lithography
The invention includes methods of forming reticles configured for imprint lithography, methods of forming capacitor container openings, and methods in which...
US-8,086,920 Method of controlling a test mode of a circuit
A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. The test vector decode circuit is driven by an...
US-8,086,916 System and method for running test and redundancy analysis in parallel
A memory redundancy analyzing apparatus having a tester, a queue, and a redundancy analyzer is provided. The tester includes testing portions for different...
US-8,086,913 Methods, apparatus, and systems to repair memory
Methods, apparatus and systems pertain to performing READ, WRITE functions in a memory which is coupled to a repair controller. One such repair controller could...
US-8,086,790 Non-volatile memory device having assignable network identification
Memory devices and methods disclosed such as a memory device having a plurality of memory dies where each die includes a network identification that uniquely...
US-8,085,612 Method and apparatus for managing behavior of memory devices
A method of managing power consumption by a memory in a memory device includes determining whether the device is powered by a depletable power supply, and if it...
US-8,085,606 Input-output line sense amplifier having adjustable output drive capability
An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line...
US-8,085,596 Reducing noise in semiconductor devices
The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a...
US-8,085,594 Reading technique for memory cell with electrically floating body transistor
A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting...
US-8,085,591 Charge loss compensation during programming of a memory device
In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is...
US-8,085,584 Memory to store user-configurable data polarity
Subject matter disclosed herein relates to user configuration of polarity of data storage in memory devices.
US-8,084,866 Microelectronic devices and methods for filling vias in microelectronic devices
Microelectronic devices and methods for filling vias and forming conductive interconnects in microfeature workpieces and dies are disclosed herein. In one...
US-8,084,854 Pass-through 3D interconnect for microelectronic dies and associated systems and methods
Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a...
US-8,084,846 Balanced semiconductor device packages including lead frame with floating leads and associated methods
A semiconductor device assembly or package includes at least one semiconductor device that is positioned adjacent to floating leads. Such an assembly or package...
US-8,084,845 Subresolution silicon features and methods for forming the same
Novel etch techniques are provided for shaping silicon features below the photolithographic resolution limits. FinFET devices are defined by recessing oxide and...
US-8,084,843 N well implants to separate blocks in a flash memory device
A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is...
US-8,084,808 Zirconium silicon oxide films
Electronic apparatus and systems include structures having a dielectric layer containing a zirconium silicon oxide film. A zirconium silicon oxide film may be...
US-8,084,806 Isolation structure for a memory cell using A1.sub.2O.sub.3 dielectric
The invention provides, in one exemplary embodiment, an isolation gate formed over a substrate for biasing the substrate and providing isolation between...
US-8,084,370 Hafnium tantalum oxynitride dielectric
Electronic apparatus and methods may include a hafnium tantalum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium tantalum...
US-8,084,355 Methods of forming copper-comprising conductive lines in the fabrication of integrated circuitry
A method of forming copper-comprising conductive lines in the fabrication of integrated circuitry includes depositing damascene material over a substrate. Line...
US-8,084,345 Methods of forming dispersions of nanoparticles, and methods of forming flash memory cells
Some embodiments include methods of forming dispersions of nanoparticles. The nanoparticles are incorporated into first coordination complexes in which the...
US-8,084,322 Method of manufacturing devices having vertical junction edge
Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled...
US-8,084,296 Methods for reducing stress in microelectronic devices and microelectronic devices formed using such methods
Methods for reducing stress in microelectronic devices and microelectronic devices formed using such methods are disclosed herein. One such device can include a...
US-8,084,142 Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects
The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local...
US-8,083,953 Registered structure formation via the application of directed thermal energy to diblock copolymer films
Methods for fabricating sublithographic, nanoscale linear microchannel arrays over surfaces without defined features utilizing self-assembling block copolymers,...
US-8,082,456 Data controlled power supply apparatus
A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a...
US-8,082,435 Memory device initiate and terminate boot commands
Memory devices and methods facilitate initiation and termination of boot data output from a memory device through the use of received commands. For example,...
US-8,082,413 Detection circuit for mixed asynchronous and synchronous memory operation
A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device. The memory access mode detection circuit...
US-8,082,404 Memory arbitration system and method having an arbitration packet protocol
A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub....
US-8,082,387 Methods, systems, and devices for management of a memory system
Methods, devices, and systems for a memory management system within an electronic device are disclosed, such as those wherein the memory management system is...
US-8,082,382 Memory device with user configurable density/performance
The memory device is comprised of a memory array having a plurality of memory cells that are organized into memory blocks. Each memory cell is capable of...
US-8,081,511 Flash memory device with redundant columns
Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns....
US-8,081,249 Image sensor with a gated storage node linked to transfer gate
A CMOS imaging system with increased charge storage of pixels yet decreased physical size, kTC noise and active area. A storage node is connected to the...
US-8,081,020 Delay-lock loop and method adapting itself to operate over a wide frequency range
A delay-lock loop receives an input clock signal from the output of a programmable divider that receives a reference clock signal. The delay-lock loop includes...
US-8,080,837 Memory devices, transistors, and memory cells
A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain...
US-8,080,817 Memory cells
In some embodiments, a memory cell includes a transistor gate spaced from a channel region by gate dielectric; a source region on one side of the channel...
US-8,080,816 Silver-selenide/chalcogenide glass stack for resistance variable memory
The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics....
US-8,080,615 Crosslinkable graft polymer non-preferentially wetted by polystyrene and polyethylene oxide
Methods for fabricating a random graft PS-r-PEO copolymer and its use as a neutral wetting layer in the fabrication of sublithographic, nanoscale arrays of...
US-8,080,460 Methods of forming diodes
Some embodiments include methods of forming diodes. A stack may be formed over a first conductive material. The stack may include, in ascending order, a...
US-8,078,848 Memory controller having front end and back end channels for modifying commands
The present disclosure includes methods, devices, modules, and systems for modifying commands. One device embodiment includes a memory controller including a...
US-8,078,797 Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash...
A memory storage system of an embodiment includes a nonvolatile memory unit and memory control circuitry coupled to the memory unit. Storage locations of the...
US-8,078,796 Method for writing to and erasing a non-volatile memory
A method for writing to and erasing a non-volatile memory is described. The method includes determining the size of a command window for use in n write...
US-8,078,018 Communication methods, methods of forming an interconnect, signal interconnects, integrated circuit structures,...
Some embodiments include communication methods, methods of forming an interconnect, signal interconnects, integrated circuit structures, circuits, and data...
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