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Patent # Description
US-8,098,180 Devices including analog-to-digital converters for internal data storage locations
A device that includes an internal data storage location coupled to an electrical conductor and an analog-to-digital converter coupled to the internal data...
US-8,097,947 Conductive systems and devices including wires coupled to anisotropic conductive film, and methods of forming...
Methods and apparatus for eliminating wire sweep and shorting while avoiding the use of under-bump metallization and high cost attendant to the use of...
US-8,097,910 Vertical transistors
The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain...
US-8,097,908 Antiblooming imaging apparatus, systems, and methods
Apparatus, systems, and methods are described to assist in reducing dark current in an active pixel sensor. In various embodiments, a potential barrier...
US-8,097,537 Phase change memory cell structures and methods
Phase change memory cell structures and methods are described herein. A number of methods of forming a phase change memory cell structure include forming a...
US-8,097,506 Shallow trench isolation for a memory
In some embodiments, a gate structure with a spacer on its side may be used as a mask to form self-aligned trenches in a microelectronic memory, such as a flash...
US-8,097,175 Method for selectively permeating a self-assembled block copolymer, method for forming metal oxide structures,...
Methods of forming metal oxide structures and methods of forming metal oxide patterns on a substrate using a block copolymer system formulated for...
US-8,095,835 Error scanning in flash memory
Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is...
US-8,095,834 Macro and command execution from memory array
Methods and apparatus for executing internal operations of memory devices utilizing instructions stored in the memory array of the memory device are disclosed....
US-8,095,765 Memory block management
Various embodiments include one or more memory devices having at least two planes of physical blocks organized into super blocks, with each super block...
US-8,095,748 Method and apparatus for sending data from multiple sources over a communications bus
In a memory system, multiple memory modules communicate over a bus. Each memory module may include a hub and at least one memory storage unit. The hub receives...
US-8,094,984 Semiconductor constructions, methods of forming semiconductor constructions, light-conducting conduits, and...
The invention includes optical signal conduits having rare earth elements incorporated therein. The optical signal conduits can, for example, contain rare earth...
US-8,094,508 Memory block testing
A memory block of a memory device is tested by programming a plurality of pages of the memory block, passing the memory block if a number of pages, each...
US-8,094,507 Command latency systems and methods
Examples of command latency systems and methods are described. In some examples, phase information associated with a received command signal is stored, a...
US-8,094,047 Data serializer apparatus and methods
Some embodiments include apparatus and methods having an output line, clock nodes to receive clock signals, the clock signals being out of phase with each...
US-8,094,045 Data bus inversion apparatus, systems, and methods
Apparatus, systems, and methods are disclosed such as those that operate to encode data bits transmitted on a plurality of channels according to at least one of...
US-8,093,937 Seamless coarse and fine delay structure for high performance DLL
A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at a boundary of coarse and...
US-8,093,730 Underfilled semiconductor die assemblies and methods of forming the same
An apparatus and method may be used for packaging a semiconductor die and a carrier substrate to substantially prevent trapped moisture therebetween and provide...
US-8,093,725 High aspect ratio contacts
A contact formed in accordance with a process for etching a insulating layer to produce an opening having an aspect ratio of at least 15:1 by first exposing the...
US-8,093,702 Stacked microelectronic devices and methods for manufacturing stacked microelectronic devices
Stacked microelectronic devices and methods of manufacturing stacked microelectronic devices are disclosed herein. In one embodiment, a method of manufacturing...
US-8,093,666 Lanthanide yttrium aluminum oxide dielectric films
Electronic apparatus and methods of forming the electronic apparatus include a lanthanide yttrium aluminum oxide dielectric film on a substrate for use in a...
US-8,093,658 Electronic device with asymmetric gate strain
The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced...
US-8,093,643 Multi-resistive integrated circuit memory
A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a...
US-8,093,638 Systems with a gate dielectric having multiple lanthanide oxide layers
Electronic systems and methods of forming the electronic systems include a gate dielectric having multiple lanthanide oxide layers. Such electronic systems may...
US-8,093,576 Chemical-mechanical polish termination layer to build electrical device isolation
A method of forming a semiconductor device may comprise forming a memory portion, forming a carbon film, depositing insulation to at least partially cover the...
US-8,093,155 Method of controlling striations and CD loss in contact oxide etch
A method for controlling striations and CD loss in a plasma etching method is disclosed. During the etching process, the substrate of semiconductor material to...
US-8,093,129 Methods of forming memory cells
Some embodiments include methods of forming memory cells. A semiconductor construction may be provided, with such construction including tunnel dielectric...
US-8,093,090 Integrated circuit edge and method to fabricate the same
In the fabrication of an integrated circuit, a trench with a sidewall is formed along the periphery of the integrated circuit and the substrate is back-lapped...
US-8,090,999 Memory media characterization for development of signal processors
Methods and apparatus utilizing media characterization of memory devices facilitate the development of signal processors for analyzing memory device outputs....
US-8,090,955 Boot block features in synchronous serial interface NAND
Embodiments are provided for protecting boot block space in a NAND memory device connected to a host device via an SPI interface. One such method includes...
US-8,090,886 Direct secondary device interface by a host
A device has a controller and a function module configured to be in communication with the controller as a result of the controller receiving a pass-through...
US-8,089,816 Memory erase methods and devices
Memory devices and erase methods for memories are disclosed, such as those adapted to discharge an erase voltage from a memory block while protecting low...
US-8,089,805 Two-part programming methods and memories
Programming a memory in two parts to reduce cell disturb includes, in at least one embodiment, programming data in two or more sequences of programming pulses...
US-8,089,800 Memory cell
Methods, and circuits, are disclosed for operating a programmable memory device. One method embodiment includes storing a value as a state in a first memory...
US-8,089,542 CMOS imager with integrated circuitry
A CMOS imager is integrated on a single substrate along with logic and support circuitry for decoding and processing optical information received by the CMOS...
US-8,089,387 Quantizing circuits with variable parameters
Systems, methods, and devices for obtaining data from a data location. The method may include generating a first value by sensing a data location under a first...
US-8,089,142 Methods and apparatus for a stacked-die interposer
An improved stacked-die package includes an interposer which improves the manufacturability of the package. A semiconductor package includes a package substrate...
US-8,089,128 Transistor gate forming methods and integrated circuits
A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal...
US-8,089,123 Semiconductor device comprising transistor structures and methods for forming same
A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some...
US-8,088,691 Selective etch chemistries for forming high aspect ratio features and associated structures
An interlevel dielectric layer, such as a silicon oxide layer, is selectively etched using a plasma etch chemistry including a silicon species and a halide...
US-8,088,659 Method of forming capacitors
High dielectric films of mixed transition metal oxides of titanium and tungsten, or titanium and tantalum, are formed by sequential chemical vapor deposition...
US-8,088,643 Resistance variable memory device with nanoparticle electrode and method of fabrication
A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a...
US-8,088,551 Methods of utilizing block copolymer to form patterns
Some embodiments include methods of forming patterns in which a block copolymer-containing composition is formed over a substrate, and is then patterned to form...
US-8,088,293 Methods of forming reticles configured for imprint lithography
The invention includes methods of forming reticles configured for imprint lithography, methods of forming capacitor container openings, and methods in which...
US-8,086,920 Method of controlling a test mode of a circuit
A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. The test vector decode circuit is driven by an...
US-8,086,916 System and method for running test and redundancy analysis in parallel
A memory redundancy analyzing apparatus having a tester, a queue, and a redundancy analyzer is provided. The tester includes testing portions for different...
US-8,086,913 Methods, apparatus, and systems to repair memory
Methods, apparatus and systems pertain to performing READ, WRITE functions in a memory which is coupled to a repair controller. One such repair controller could...
US-8,086,790 Non-volatile memory device having assignable network identification
Memory devices and methods disclosed such as a memory device having a plurality of memory dies where each die includes a network identification that uniquely...
US-8,085,612 Method and apparatus for managing behavior of memory devices
A method of managing power consumption by a memory in a memory device includes determining whether the device is powered by a depletable power supply, and if it...
US-8,085,606 Input-output line sense amplifier having adjustable output drive capability
An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line...
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