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Patent # Description
US-8,148,263 Methods for forming conductive vias in semiconductor device components
A method for forming conductive vias in a substrate of a semiconductor device component includes forming one or more holes, or apertures or cavities, in the...
US-8,148,247 Method and algorithm for random half pitched interconnect layout with constant spacing
An embodiment of a system and method produces a random half pitched interconnect layout. A first normal-pitch mask and a second normal-pitch mask are created...
US-8,148,225 Fully-depleted (FD)(SOI) MOSFET access transistor and method of fabrication
A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity...
US-8,148,222 Cross-point diode arrays and methods of manufacturing cross-point diode arrays
Methods of forming an array of memory cells and memory cells that have pillars. Individual pillars can have a semiconductor post formed of a bulk semiconductor...
US-8,148,197 Methods of forming germanium-antimony-tellurium materials and a method of forming a semiconductor device...
A method of forming a material. The method comprises conducting an ALD layer cycle of a first metal, the ALD layer cycle comprising a reactive first metal...
US-8,145,866 Selective register reset
The present disclosure includes methods, devices, modules, and systems for storing selective register reset. One method embodiment includes receiving an...
US-8,144,534 Methods and memory devices for repairing memory cells
Methods and memory devices for repairing memory cells are discloses, such as a memory device that includes a main array having a plurality of sections of memory...
US-8,144,525 Memory cell sensing using negative voltage
Embodiments of the present disclosure provide methods, devices, modules, and systems for memory cell sensing using negative voltage. One method includes...
US-8,144,516 Dynamic pass voltage for sense operation in a memory device
Methods for sensing and memory devices are disclosed. One such method for sensing uses a dynamic pass voltage on at least one adjacent memory cell that is...
US-8,144,506 Cross-point memory devices, electronic systems including cross-point memory devices and methods of accessing a...
Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row)...
US-8,144,497 Self-identifying stacked die semiconductor components
A semiconductor die having a functional circuit (e.g., a memory array) and a decode circuit suitable for use in a stacked die semiconductor component (e.g., a...
US-8,144,307 Image forming method and apparatus
An array of phase-shifting micro-mechanical elements are used in a method and device for patterning a workpiece, for exposing a radiation sensitive layer on a...
US-8,144,269 Reflective LCOS displays utilizing novel polarizing beam splitters
Disclosed are display systems using reflective liquid-crystal microdisplays that efficiently use unpolarized light sources without needing to double the etendue...
US-8,143,966 Coupling cancellation scheme
Methods and apparatus are disclosed, such as those involving an interconnection layout for an integrated circuit (IC). One such layout includes a plurality of...
US-8,143,928 Duty cycle correction systems and methods
Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a...
US-8,143,167 Fabrication processes for forming dual depth trenches using a dry etch that deposits a polymer
Trench isolation structures and methods to form same for use in the manufacture of semiconductor devices are described. The trench isolation structures are...
US-8,142,673 Compositions for dissolution of low-k dielectric films, and methods of use
An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k...
US-8,140,780 Systems, methods, and devices for configuring a device
Disclosed are methods and devices, among which is a method for configuring an electronic device. In one embodiment, an electronic device may include one or more...
US-8,139,434 Methods and apparatus for voltage sensing and reporting
Semiconductor devices comprising at least one voltage sensor for sensing an operating voltage associated with an operational circuit of the semiconductor...
US-8,139,421 Erase degradation reduction in non-volatile memory
Methods for erasing a memory device and memory systems are provided, such as those including a non-volatile memory device is erased by using an intermediate...
US-8,139,419 Programming methods and memories
Methods of programming memory cells, and memories incorporating such methods, are disclosed. In at least one embodiment, programming is accomplished by applying...
US-8,139,418 Techniques for controlling a direct injection semiconductor memory device
Techniques for controlling a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized...
US-8,139,386 Memory, computing system and method for checkpointing
Embodiments of the present invention provide local checkpoint memories that are closely coupled to the processor of a computing system used during normal...
US-8,138,809 Periodic signal delay apparatus, systems, and methods
Apparatus, systems, and methods are disclosed that operate to delay a periodic input signal in one or more delay elements of a group of delay elements to...
US-8,138,794 Output slew rate control
This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver...
US-8,138,613 Microelectronic devices
Microelectronic devices and methods for manufacturing microelectronic devices are described herein. An embodiment of one such method includes attaching a...
US-8,138,541 Memory cells
Some embodiments include memory cells that contain floating bodies and diodes. The diodes may be gated diodes having sections doped to a same conductivity type...
US-8,138,526 Semiconductor structures including dual fins
Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel...
US-8,138,039 Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array
A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by...
US-8,138,021 Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing...
Packaged semiconductor components, apparatus for packaging semiconductor devices, methods of packaging semiconductor devices, and methods of manufacturing...
US-8,137,875 Method and apparatus for overlay compensation between subsequently patterned layers on workpiece
Methods and apparatuses for patterning workpieces are provided. The methods and apparatuses described herein improve overlay between subsequently patterned...
US-8,136,000 Test mode for multi-chip integrated circuit packages
When a test mode of a controller of a multi-chip integrated circuit package is activated, external signal lines coupled to the controller are re-mapped to...
US-8,135,940 Method of rotating data in a plurality of processing elements
A method of rotating data in a plurality of processing elements comprises a plurality of shifting operations and a plurality of storing operations, with the...
US-8,135,939 Robust index storage for non-volatile memory
A non-volatile memory data address translation scheme is described that utilizes a hierarchal address translation system that is stored in the non-volatile...
US-8,135,925 Methods of operating a memory system
Methods of operating a memory system are useful in facilitating access to data. Where repetitive data patterns are detected among portions of received data, and...
US-8,134,886 Method and apparatus for reducing oscillation in synchronous circuits
Control signal oscillation filtering circuits, delay locked loops, clock synchronization methods and devices and systems incorporating the control signal...
US-8,134,872 Apparatus and methods for programming multilevel-cell NAND memory devices
Methods and apparatus are provided. A first data value is read from a first memory cell and is stored. An attempt is made to add a second data value to the...
US-8,134,868 Memory device biasing method and apparatus
Memory devices and methods are disclosed, such as those facilitating data line shielding by way of capacitive coupling with data lines coupled to a memory...
US-8,134,867 Memory array having a programmable word length, and method of operating same
A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or...
US-8,134,771 Spatial light modulators with changeable phase masks for use in holographic data storage
A holographic data storage system that includes a write head that includes a pixellated spatial light modulator and a separate or integral phase mask that...
US-8,134,548 DC-DC converter switching transistor current measurement technique
A method is described comprising conducting a first current through a switching transistor. The method also comprises conducting a second current through a pair...
US-8,134,391 Semiconductor devices with signal synchronization circuits
Semiconductor devices are disclosed providing synchronization circuits for synchronized signal distribution for a plurality of devices in a semiconductor...
US-8,134,378 Reconfigurable connections for stacked semiconductor devices
Some embodiments include apparatus, systems, and methods comprising semiconductor dice arranged in a stack, a number of connections configured to provide...
US-8,134,197 Nanowire transistor with surrounding gate
One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous...
US-8,134,194 Memory cells, memory cell constructions, and memory cell programming methods
Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material...
US-8,134,137 Memory device constructions, memory cell forming methods, and semiconductor construction forming methods
Memory device constructions include a first column line extending parallel to a second column line, the first column line being above the second column line; a...
US-8,133,664 Methods of forming patterns
Some embodiments include methods of forming patterns of openings. The methods may include forming spaced features over a substrate. The features may have tops...
US-8,133,554 Methods for depositing material onto microfeature workpieces in reaction chambers and systems for depositing...
Methods for depositing material onto microfeature workpieces in reaction chambers and systems for depositing materials onto microfeature workpieces are...
US-8,130,585 System and method for hidden-refresh rate modification
A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a...
US-8,130,550 Memory with sub-blocks
A non-volatile memory comprising a NOR block with a first sub-block independently addressable from a second sub-block, the two sub-blocks sharing a physical...
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