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Encapsulated phase change cell structures and methods
Methods and devices associated with phase change cell structures are described herein. In one or more embodiments, a method of forming a phase change cell...
Method of compensation for bleaching of resist during three-dimensional
exposure of resist
The field of this disclosure is making three-dimensional topographic structures by means of graduated exposure in a photosensitive material, such as a...
Nanotube separation methods
A nanotube separation method includes depositing a tag on a nanotube in a nanotube mixture. The nanotube has a defect and the tag deposits at the defect where a...
Memory device and method having on-board processing logic for facilitating
interface with multiple processors,...
A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating...
Memory controllers, memory systems, solid state drives and methods for
processing a number of commands
The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end...
Semiconductor component having through wire interconnect with compressed
A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back...
Semiconductor devices including damascene trenches with conductive
A method and apparatus for providing a conductive structure adjacent to a damascene conductive structure in a semiconductor device structure. The semiconductor...
Apparatus and methods for selective removal of material from wafer
A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an...
Methods and systems for imaging and cutting semiconductor wafers and other
Methods and systems for imaging and cutting semiconductor wafers and other microelectronic device substrates are disclosed herein. In one embodiment, a system...
Method for purification of semiconducting single wall nanotubes
A process of forming a semiconductive carbon nanotube structure includes imposing energy on a mixture that contains metallic carbon nanotubes and semiconductive...
Error recovery storage along a nand-flash string
Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are...
Word line activation in memory devices
Memory devices and methods facilitate flexibility in applying differing biasing schemes to word lines. For example, one such memory device can include an...
Programming method to reduce gate coupling interference for non-volatile
A non-volatile memory device and programming process is described that compensates for coupling effects on threshold gate voltages of adjacent floating gate or...
Memory page boosting method, device and system
A memory page boosting method, device and system for boosting unselected memory cells in a multi-level cell memory cell is described. The memory device includes...
Method, apparatus and system using hierarchical histogram for automatic
exposure adjustment of an image
An automatic exposure control circuit and a method for generating a hierarchical histogram for exposure control. The control circuit and the method result in...
Integrated circuit inspection system
Methods and systems that include a nanotube used as an emitter in the testing and fabrication of integrated circuits. The nanotube emits a signal to a...
Structure and method for forming a capacitively coupled chip-to-chip
A system and method for providing capacitively-coupled signaling in a system-in-package (SiP) device is disclosed. In one embodiment, the system includes a...
Isolation trenches for memory devices
A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric...
Disposable pillars for contact formation
Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various...
Bottom electrode for memory device and method of forming the same
Contacts having use in an integrated circuit and exemplary methods of forming the contacts are disclosed. The methods involve forming a conductive cap over a...
Method for removing metal layers formed outside an aperture of a BPSG
layer utilizing multiple etching...
A microelectronic substrate and method for removing adjacent conductive and nonconductive materials from a microelectronic substrate. In one embodiment, the...
Resistive memory and methods of processing resistive memory
Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include...
Method and apparatus providing an imager module with a permanent carrier
Method and apparatus providing a wafer level fabrication of imager modules in which a permanent carrier protects imager devices on an imager wafer and is used...
Defective memory block identification in a memory device
During manufacture and testing of a memory device, a memory test is performed to determine which, if any, memory blocks are defective. A memory map of the...
Failure recovery memory devices and methods
Memory devices and methods are described that include serially chained memory devices. In one or more of the configurations shown, a serial chain of memory...
Fault-tolerant non-volatile integrated circuit memory
Apparatus and methods are disclosed, such as those that store data in a plurality of non-volatile integrated circuit memory devices, such as NAND flash, with...
Method and memory device providing reduced quantity of interconnections
Methods, devices and systems for reducing the quantity of external interconnections of a memory device are disclosed. Implementation of one such method, device...
Circuits, systems and methods for driving high and low voltages on bit
lines in non-volatile memory
An integrated circuit bit line driver system includes a plurality of bit line drivers coupled to respective bit lines of an array of non-volatile memory cells....
Methods and apparatus for programming a memory cell using one or more
blocking memory cells
Methods and apparatus for programming a memory cell using one or more blocking memory cells facilitate mitigation of capacitive voltage coupling. The methods...
Memory modules having daisy chain wiring configurations and filters
Examples described include memory units coupled to a controller using a daisy chain wiring configuration. A filter located between a first memory unit and the...
Correction of non-uniform sensitivity in an image array
An improved non-uniform sensitivity correction algorithm for use in an imager device (e.g., a CMOS APS). The algorithm provides zones having flexible boundaries...
Transistors, semiconductor devices, assemblies and constructions
Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another...
Silicon dioxide deposition methods using at least ozone and TEOS as
Embodiments disclosed herein pertain to silicon dioxide deposition methods using at least ozone and tetraethylorthosilicate (TEOS) as deposition precursors. In...
Method for providing electrical connections to spaced conductive lines
An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an...
Method of forming a bond pad
A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an...
Process for enhancing solubility and reaction rates in supercritical
Processes for enhancing solubility and the reaction rates in supercritical fluids are provided. In preferred embodiments, such processes provide for the uniform...
Pitch multiplied mask patterns for isolated features
Crisscrossing spacers formed by pitch multiplication are used as a mask to form isolated features, such as contacts vias. A first plurality of mandrels are...
Methods of forming semiconductor constructions
The invention includes methods of forming semiconductor constructions in which a single etch is utilized to penetrate through a titanium-containing layer and...
Method, system, and apparatus for distributed decoding during prolonged
Methods, apparatuses and systems are disclosed for preserving, verifying, and correcting data in DRAM device during a power-saving mode. In the power-saving...
Systems and devices including memory with built-in self test and methods
of making and using the same
Disclosed are methods, systems and devices, such as a device including a data location, a quantizing circuit coupled to the data location, and a test module...
System and method for capturing data signals using a data strobe signal
A signal capture system and method is used to capture a data signal using a data strobe signal having a preamble of strobe signal transitions. The system...
NAND memory device column charging
Embodiments of NAND Flash memory devices and methods recognize that effective column coupling capacitance can be reduced by maintaining a sourced voltage on...
High gain, low noise photodiode for image sensors and method of formation
Embodiments of the present invention provide a pixel cell for an image sensor that includes a photodiode, which provides high gain, low noise, and low dark...
Deuterated structures for image sensors and methods for forming the same
A pixel cell with a photo-conversion device and at least one structure includes a deuterated material adjacent the photo-conversion device.
Methods of forming patterns utilizing lithography and spacers
Some embodiments include methods of forming patterns. A first set of features is photolithographically formed over a substrate, and then a second set of...
Some embodiments include methods of forming capacitors. A first section of a capacitor may be formed to include a first storage node, a first dielectric...
Integrated circuitry and methods of forming a semiconductor-on-insulator
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
Vertical gated access transistor
According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches and a plurality of shallow...
Methods of forming an array of memory cells, methods of forming a
plurality of field effect transistors,...
A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall...
Transistor forming methods
A transistor forming method includes forming a dielectric spacer in a trench surrounding an active area island, forming line openings through the spacer, and...