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Patent # Description
US-8,138,794 Output slew rate control
This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver...
US-8,138,613 Microelectronic devices
Microelectronic devices and methods for manufacturing microelectronic devices are described herein. An embodiment of one such method includes attaching a...
US-8,138,541 Memory cells
Some embodiments include memory cells that contain floating bodies and diodes. The diodes may be gated diodes having sections doped to a same conductivity type...
US-8,138,526 Semiconductor structures including dual fins
Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel...
US-8,138,039 Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array
A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by...
US-8,138,021 Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing...
Packaged semiconductor components, apparatus for packaging semiconductor devices, methods of packaging semiconductor devices, and methods of manufacturing...
US-8,137,875 Method and apparatus for overlay compensation between subsequently patterned layers on workpiece
Methods and apparatuses for patterning workpieces are provided. The methods and apparatuses described herein improve overlay between subsequently patterned...
US-8,136,000 Test mode for multi-chip integrated circuit packages
When a test mode of a controller of a multi-chip integrated circuit package is activated, external signal lines coupled to the controller are re-mapped to...
US-8,135,940 Method of rotating data in a plurality of processing elements
A method of rotating data in a plurality of processing elements comprises a plurality of shifting operations and a plurality of storing operations, with the...
US-8,135,939 Robust index storage for non-volatile memory
A non-volatile memory data address translation scheme is described that utilizes a hierarchal address translation system that is stored in the non-volatile...
US-8,135,925 Methods of operating a memory system
Methods of operating a memory system are useful in facilitating access to data. Where repetitive data patterns are detected among portions of received data, and...
US-8,134,886 Method and apparatus for reducing oscillation in synchronous circuits
Control signal oscillation filtering circuits, delay locked loops, clock synchronization methods and devices and systems incorporating the control signal...
US-8,134,872 Apparatus and methods for programming multilevel-cell NAND memory devices
Methods and apparatus are provided. A first data value is read from a first memory cell and is stored. An attempt is made to add a second data value to the...
US-8,134,868 Memory device biasing method and apparatus
Memory devices and methods are disclosed, such as those facilitating data line shielding by way of capacitive coupling with data lines coupled to a memory...
US-8,134,867 Memory array having a programmable word length, and method of operating same
A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or...
US-8,134,771 Spatial light modulators with changeable phase masks for use in holographic data storage
A holographic data storage system that includes a write head that includes a pixellated spatial light modulator and a separate or integral phase mask that...
US-8,134,548 DC-DC converter switching transistor current measurement technique
A method is described comprising conducting a first current through a switching transistor. The method also comprises conducting a second current through a pair...
US-8,134,391 Semiconductor devices with signal synchronization circuits
Semiconductor devices are disclosed providing synchronization circuits for synchronized signal distribution for a plurality of devices in a semiconductor...
US-8,134,378 Reconfigurable connections for stacked semiconductor devices
Some embodiments include apparatus, systems, and methods comprising semiconductor dice arranged in a stack, a number of connections configured to provide...
US-8,134,197 Nanowire transistor with surrounding gate
One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous...
US-8,134,194 Memory cells, memory cell constructions, and memory cell programming methods
Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material...
US-8,134,137 Memory device constructions, memory cell forming methods, and semiconductor construction forming methods
Memory device constructions include a first column line extending parallel to a second column line, the first column line being above the second column line; a...
US-8,133,664 Methods of forming patterns
Some embodiments include methods of forming patterns of openings. The methods may include forming spaced features over a substrate. The features may have tops...
US-8,133,554 Methods for depositing material onto microfeature workpieces in reaction chambers and systems for depositing...
Methods for depositing material onto microfeature workpieces in reaction chambers and systems for depositing materials onto microfeature workpieces are...
US-8,130,585 System and method for hidden-refresh rate modification
A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a...
US-8,130,550 Memory with sub-blocks
A non-volatile memory comprising a NOR block with a first sub-block independently addressable from a second sub-block, the two sub-blocks sharing a physical...
US-8,130,542 Reading non-volatile multilevel memory cells
Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile multilevel memory cells. One method includes...
US-8,130,536 Read window in chalcogenide semiconductor memories
Using a shorter read pulse width may increase read window in some embodiments. This may allow the use of higher voltages with less likelihood of a read disturb...
US-8,130,527 Stacked device identification assignment
Some embodiments include apparatus and methods having dice arranged in a stack. The dice include at least a first die and a second die, and a connection coupled...
US-8,130,439 Optics arrangements including light source arrangements for an active matrix liquid crystal generator
A system for producing modulated lights disclosed. The system comprises a spatial light modulator including a light modulating medium switchable between...
US-8,130,185 Active matrix liquid crystal image generator
A system for producing spatially modulated monochrome or color light having gray scale includes an active matrix liquid crystal spatial light modulator having...
US-8,130,024 Temperature compensation via power supply modification to produce a temperature-independent delay in an...
A method and circuitry for adjusting the delay of a variable delay line (VDL) in a delay locked loop (DLL) or other delay element or subcircuit on an integrated...
US-8,129,839 Electronic device package structures
A sealing layer is provided on a surface of a substrate, such as a semiconductor wafer. The sealing layer includes apertures which expose external contact...
US-8,129,781 Method of forming memory devices by performing halogen ion implantation and diffusion processes
Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes...
US-8,129,289 Method to deposit conformal low temperature SiO2
Methods of controlling critical dimensions of reduced-sized features during semiconductor fabrication through pitch multiplication are disclosed. Pitch...
US-8,129,243 Methods of forming non-volatile memory having tunnel insulator of increasing conduction band offset
Methods of forming non-volatile memory cell structures are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers...
US-8,129,240 Methods of forming a plurality of capacitors
A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area...
US-8,129,218 Self-aligned, planar phase change memory elements and devices, systems employing the same and method of forming...
Phase change memory elements, devices and systems using the same and methods of forming the same are disclosed. A memory element includes first and second...
US-8,129,205 Solid state lighting devices and associated methods of manufacturing
Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state light device includes a light...
US-8,129,093 Prevention of photoresist scumming
A photo acid generator (PAG) or an acid is used to reduce resist scumming and footing. Diffusion of acid from photoresist into neighbors causes a decreased acid...
US-8,127,204 Memory system and method using a memory device die stacked with a logic die using data encoding, and system...
A memory system and method using at least one memory device die stacked with and coupled to a logic die by interconnects, such as through silicon vias. One such...
US-8,127,185 Memory devices and methods for managing error regions
Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for...
US-8,127,091 Programming memory cells with additional data for increased threshold voltage resolution
Methods for data transfer and/or programming a memory device, memory devices and memory systems are provided. According to at least one such method, additional...
US-8,125,836 Verifying an erase threshold in a memory device
In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory...
US-8,125,831 Sensing against a reference cell
Memory devices, bulk storage devices, and methods of operating memory are disclosed, such as those adapted to process and generate analog data signals...
US-8,125,829 Biasing system and method
Embodiments are provided that include a memory system that includes a memory system, having an access device coupled between a global line and a local line and...
US-8,125,826 Fractional bits in memory cells
Methods, devices, modules, and systems for programming memory cells can include storing charges corresponding to a data state that represents an integer number...
US-8,125,268 High performance input receiver circuit for reduced-swing inputs
An input buffer receiver circuit for electronic devices (e.g., memory chips) to receive and process reduced-swing and high bandwidth inputs to obtain "buffered"...
US-8,125,260 Phase mixer with adjustable load-to-drive ratio
Phase mixers, clock signal generators, memories and methods for providing an output signal having a phase relative to the phase difference of input clock...
US-8,125,252 Multi-phase signal generator and method
Multi-phase signal generators and methods for generating multi-phase signals are described. In one embodiment, the clock generator generates quadrature clock...
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