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Patent # Description
US-8,082,435 Memory device initiate and terminate boot commands
Memory devices and methods facilitate initiation and termination of boot data output from a memory device through the use of received commands. For example,...
US-8,082,413 Detection circuit for mixed asynchronous and synchronous memory operation
A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device. The memory access mode detection circuit...
US-8,082,404 Memory arbitration system and method having an arbitration packet protocol
A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub....
US-8,082,387 Methods, systems, and devices for management of a memory system
Methods, devices, and systems for a memory management system within an electronic device are disclosed, such as those wherein the memory management system is...
US-8,082,382 Memory device with user configurable density/performance
The memory device is comprised of a memory array having a plurality of memory cells that are organized into memory blocks. Each memory cell is capable of...
US-8,081,511 Flash memory device with redundant columns
Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns....
US-8,081,249 Image sensor with a gated storage node linked to transfer gate
A CMOS imaging system with increased charge storage of pixels yet decreased physical size, kTC noise and active area. A storage node is connected to the...
US-8,081,020 Delay-lock loop and method adapting itself to operate over a wide frequency range
A delay-lock loop receives an input clock signal from the output of a programmable divider that receives a reference clock signal. The delay-lock loop includes...
US-8,080,837 Memory devices, transistors, and memory cells
A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain...
US-8,080,817 Memory cells
In some embodiments, a memory cell includes a transistor gate spaced from a channel region by gate dielectric; a source region on one side of the channel...
US-8,080,816 Silver-selenide/chalcogenide glass stack for resistance variable memory
The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics....
US-8,080,615 Crosslinkable graft polymer non-preferentially wetted by polystyrene and polyethylene oxide
Methods for fabricating a random graft PS-r-PEO copolymer and its use as a neutral wetting layer in the fabrication of sublithographic, nanoscale arrays of...
US-8,080,460 Methods of forming diodes
Some embodiments include methods of forming diodes. A stack may be formed over a first conductive material. The stack may include, in ascending order, a...
US-8,078,848 Memory controller having front end and back end channels for modifying commands
The present disclosure includes methods, devices, modules, and systems for modifying commands. One device embodiment includes a memory controller including a...
US-8,078,797 Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash...
A memory storage system of an embodiment includes a nonvolatile memory unit and memory control circuitry coupled to the memory unit. Storage locations of the...
US-8,078,796 Method for writing to and erasing a non-volatile memory
A method for writing to and erasing a non-volatile memory is described. The method includes determining the size of a command window for use in n write...
US-8,078,018 Communication methods, methods of forming an interconnect, signal interconnects, integrated circuit structures,...
Some embodiments include communication methods, methods of forming an interconnect, signal interconnects, integrated circuit structures, circuits, and data...
US-8,078,001 Methods, apparatuses and systems for piecewise generation of pixel correction values for image processing
Methods, apparatuses and systems providing pixel correction values for a captured image, where the correction values are determined based on a ...
US-8,077,538 Address decoder and/or access line driver and method for memory devices
Address decoders and access line drivers are provided. One such row decoder and access line driver receives power supply voltages in a manner that prevents CHC...
US-8,077,532 Small unit internal verify read in a memory device
Methods for small unit internal verify read operation and a memory device are disclosed. In one such method, expected data is programmed into a grouping of...
US-8,077,519 Programming a memory device to increase data reliability
Methods for programming a memory array, memory devices, and memory systems are disclosed. In one such method, the target reliability of the data to be...
US-8,077,515 Methods, devices, and systems for dealing with threshold voltage change in memory devices
The present disclosure includes methods, devices, and systems for dealing with threshold voltage change in memory devices. A number of embodiments include an...
US-8,077,377 Spatial light modulator with structured mirror surfaces
The invention relates to methods to improve SLMs, in particular to reflecting micromechanical SLMs, for applications with simple system architecture, high...
US-8,076,760 Semiconductor fuse arrangements
The invention includes semiconductor fuse arrangements containing an electrically conductive plate over and in electrical contact with a plurality of...
US-8,076,727 Magnesium-doped zinc oxide structures and methods
Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain zinc and monolayers that contain...
US-8,076,721 Fin structures and methods of fabricating fin structures
There is provided fin structures and methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may...
US-8,076,717 Vertically-oriented semiconductor selection device for cross-point array memory
A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first...
US-8,076,714 Memory device with high dielectric constant gate dielectrics and metal floating gates
A memory cell transistor includes a high dielectric constant tunnel insulator, a metal floating gate, and a high dielectric constant inter-gate insulator...
US-8,076,673 Recessed gate dielectric antifuse
A recessed dielectric antifuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A recess is formed between the...
US-8,076,663 Phase change memory structures
Methods, devices, and systems associated with phase change memory structures are described herein. One or more embodiments of the present disclosure can reduce...
US-8,076,249 Structures containing titanium silicon oxide
A dielectric containing a titanium silicon oxide film disposed in an integrated circuit and a method of fabricating such a dielectric provide a dielectric for...
US-8,076,248 Methods for forming semiconductor constructions, and methods for selectively etching silicon nitride relative...
The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for...
US-8,076,244 Methods for causing fluid to flow through or into via holes, vents and other openings or recesses that...
A method for removing material from surfaces of at least a portion of at least one recess or at least one aperture extending into a surface of a substrate...
US-8,076,229 Methods of forming data cells and connections to data cells
Disclosed are methods and devices, among which is a method that includes forming a lower conductive material on a substrate, forming a stop material on the...
US-8,076,211 Fabricating bipolar junction select transistors for semiconductor memories
A bipolar junction transistor may act as a select device for a semiconductor memory. The bipolar junction transistor may be formed of a stack of base and...
US-8,076,208 Method for forming transistor with high breakdown voltage using pitch multiplication technique
Transistors are formed using pitch multiplication. Each transistor includes a source region and a drain region connected by strips of active area material...
US-8,076,200 Charge trapping dielectric structures with variable band-gaps
A nonvolatile read-only memory having a thin nitrided tunnel insulator surface with a charge blocking insulator over the nitrided surface is presented. The...
US-8,076,195 Resistive memory architectures with multiple memory cells per access device
A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is...
US-8,074,353 Methods of providing semiconductor components within sockets
The invention includes methods of utilizing removable mechanical precising mechanisms and/or optical-based precising mechanisms to align chips within sockets....
US-8,074,159 Method and apparatus for detecting communication errors on a bus
A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on...
US-8,074,122 Program failure recovery
A program failure is detected during programming of a memory device. When the program failure is detected, a transfer of the contents of a register of the...
US-8,073,986 Memory devices configured to identify an operating mode
Memory devices having a memory module, an interface, identification circuitry and a controller coupled to the memory module and the identification circuitry....
US-8,073,890 Continuous high-frequency event filter
A circuit and method for generating an active output signal in response to detecting N events, which are represented by an event signal. A counter circuit is...
US-8,072,838 Control voltage tracking circuits, methods for recording a control voltage for a clock synchronization circuit...
Memories, clock synchronization circuits, clock synchronization controller circuits, and methods for setting a voltage controlled delay of a clock...
US-8,072,836 Systems, methods and devices for arbitrating die stack position in a multi-die stack device
Embodiments are described for arbitrating stacked dies in multi-die semiconductor packages. In one embodiment, die identification data for at least two stacked...
US-8,072,820 System and method for reducing pin-count of memory devices, and memory device testers for same
Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output...
US-8,072,816 Memory block reallocation in a flash memory device
A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability....
US-8,072,814 NAND with back biased operation
Methods of programming, reading and erasing memory cells are disclosed. In at least one embodiment, program, sense, and erase operations in a memory are...
US-8,072,812 Sensing of memory cells in NAND flash
An analog voltage NAND architecture non-volatile memory data read/verify process and circuits is described that senses analog voltages in non-volatile cells...
US-8,072,523 Redundancy in column parallel or row architectures
A column circuitry architecture for an imager includes redundant column or row circuits. The column or row circuitry includes a number of redundant column or...
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