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Patent # Description
US-8,065,551 Adjustable byte lane offset for memory module to reduce skew
Disclosed herein are solutions for addressing the problem of skew of data within a byte lane by factors caused external to the integrated circuit or module...
US-8,065,461 Capturing read data
Various techniques are disclosed for providing data retrieved from a memory device and furnished to a memory bus in response to a read operation to a local bus...
US-8,064,562 Digital frequency locked delay line
A device includes a signal generator having a delay locked circuit for providing a number of output signals based on an input signal. The output signals have a...
US-8,064,274 Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or...
A method of generating a voltage as well as an integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i)...
US-8,064,269 Apparatus and methods having majority bit detection
Electronic apparatus and fabrication of the electronic apparatus that includes detection of the majority of values in a plurality of data bits may be used in a...
US-8,064,267 Erase voltage reduction in a non-volatile memory device
In erasing a memory block of memory cells, a semiconductor tub that contains a memory block to be erased can be biased with a high, positive voltage. The...
US-8,064,266 Memory devices and methods of writing data to memory devices utilizing analog voltage levels
Memory devices, and methods of writing data to memory devices, utilizing analog voltage levels indicative of threshold voltages and desired threshold voltages...
US-8,064,258 Method apparatus, and system providing adjustable memory page configuration
A method, apparatus and system providing a memory device having an array of cells which may be selectively designated for either error correction code use or...
US-8,064,252 Multi-pass programming in a memory device
A method for programming a memory device, a memory device, and a memory system are provided. According to at least one such method, a first programming pass...
US-8,064,251 Memory device and method having charge level assignments selected to minimize signal coupling
A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the...
US-8,064,250 Providing a ready-busy signal from a non-volatile memory device to a memory controller
A common standard may be used for both dynamic random access memories and non-volatile memories, despite the fact that the non-volatile memory generally needs...
US-8,064,218 Multilayer wiring board and electrical connecting apparatus using the same
The present invention makes repair easy and reduces effects on the electrical connection conditions of an electronic component to an internal wiring after...
US-8,063,965 Apparatus and method for eliminating artifacts in active pixel sensor (APS) imagers
An active pixel sensor (APS) that includes circuitry to eliminate artifacts in digital images. The APS includes a comparator for comparing a signal level from a...
US-8,063,676 Band-gap reference voltage detection circuit
Methods, devices, modules, and systems for a band-gap reference voltage detection circuit are provided. One embodiment for a band-gap reference voltage...
US-8,063,651 Contact for electrical test of electronic devices, probe assembly and method for manufacturing the same
A contact for an electrical test comprises a first area to be bonded to a board, a second area extending in the right-left direction from the lower end portion...
US-8,063,646 Apparatus and methods for testing microelectronic devices
Microelectronic devices, methods for testing microelectronic devices, and detachable electrical components. One embodiment of an apparatus for testing...
US-8,063,493 Semiconductor device assemblies and packages
A sacrificial substrate for fabricating semiconductor device assemblies and packages with edge contacts includes conductive elements on a surface thereof, which...
US-8,063,491 Stacked device conductive path connectivity
Various embodiments include apparatus and methods having circuitry to test continuity of conductive paths coupled to dice arranged in a stack.
US-8,063,454 Semiconductor structures including a movable switching element and systems including same
Semiconductor structures including a movable switching element having a base disposed on a conductive pad, a body extending from the base, and an end laterally...
US-8,063,436 Memory cells configured to allow for erasure by enhanced F-N tunneling of holes from a control gate to a charge...
Memory cells including a control gate, a charge trapping material, and a charge blocking material between the control gate and the charge trapping material. The...
US-8,062,969 Methods of selectively growing nickel-containing materials
The invention includes methods of electroless plating of nickel selectively on exposed conductive surfaces relative to exposed insulative surfaces. The...
US-8,062,958 Microelectronic device wafers and methods of manufacturing
Methods of forming microelectronic device wafers include fabricating a plurality of semiconductor dies at an active side of a semiconductor wafer, depositing a...
US-8,062,949 Nanowire transistor with surrounding gate
One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous...
US-8,062,945 Methods of forming non-volatile memory structure with crested barrier tunnel layer
Embodiments of methods of forming non-volatile memory structures are provided. In one such embodiment, first and second source/drain regions are formed on a...
US-8,062,814 Optical compensation devices, systems, and methods
Photolithographic apparatus, systems, and methods that make use of optical compensation devices are disclosed. In various embodiments, an imaging mask includes...
US-8,060,798 Refresh of non-volatile memory cells based on fatigue conditions
In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment,...
US-8,060,719 Hybrid memory management
Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi level memory cells. Logical addresses can be...
US-8,059,474 Reducing read failure in a memory device
Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is...
US-8,059,142 Digital display
A display system that achieves a gamma characteristic different than 1, such as a gamma characteristic of 2 for example. The gamma characteristic may be...
US-8,058,729 Titanium nitride films
The use of atomic layer deposition (ALD) to form a conductive titanium nitride layer produces a reliable structure for use in a variety of electronic devices....
US-8,058,716 Integrated circuit devices with stacked package interposers
An IC device includes a die and a first package interposer stacked over a second package interposer. The IC device includes a first conductive connection from a...
US-8,058,140 Thickened sidewall dielectric for memory cell
Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a...
US-8,058,138 Gap processing
Among various methods, devices, and apparatuses, a number of methods are provided for forming a gap between circuitry. One such method includes depositing a...
US-8,058,130 Method of forming a nitrogen-enriched region within silicon-oxide-containing masses
The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a...
US-8,058,126 Semiconductor devices and structures including at least partially formed container capacitors and methods of...
Methods of forming semiconductor devices that include one or more container capacitors include anchoring an end of a conductive member to a surrounding lattice...
US-8,058,118 Methods of forming and operating back-side trap non-volatile memory cells
Methods of forming and operating a back-side trap non-volatile memory cell. Method of forming a back-side trap non-volatile memory cell include forming a...
US-8,058,095 Encapsulated phase change cell structures and methods
Methods and devices associated with phase change cell structures are described herein. In one or more embodiments, a method of forming a phase change cell...
US-8,057,971 Method of compensation for bleaching of resist during three-dimensional exposure of resist
The field of this disclosure is making three-dimensional topographic structures by means of graduated exposure in a photosensitive material, such as a...
US-8,057,686 Nanotube separation methods
A nanotube separation method includes depositing a tag on a nanotube in a nanotube mixture. The nanotube has a defect and the tag deposits at the defect where a...
US-8,055,852 Memory device and method having on-board processing logic for facilitating interface with multiple processors,...
A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating...
US-8,055,816 Memory controllers, memory systems, solid state drives and methods for processing a number of commands
The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end...
US-8,053,909 Semiconductor component having through wire interconnect with compressed bump
A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back...
US-8,053,899 Semiconductor devices including damascene trenches with conductive structures
A method and apparatus for providing a conductive structure adjacent to a damascene conductive structure in a semiconductor device structure. The semiconductor...
US-8,053,371 Apparatus and methods for selective removal of material from wafer alignment marks
A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an...
US-8,053,279 Methods and systems for imaging and cutting semiconductor wafers and other semiconductor workpieces
Methods and systems for imaging and cutting semiconductor wafers and other microelectronic device substrates are disclosed herein. In one embodiment, a system...
US-8,052,075 Method for purification of semiconducting single wall nanotubes
A process of forming a semiconductive carbon nanotube structure includes imposing energy on a mixture that contains metallic carbon nanotubes and semiconductive...
US-8,051,358 Error recovery storage along a nand-flash string
Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are...
US-8,050,102 Word line activation in memory devices
Memory devices and methods facilitate flexibility in applying differing biasing schemes to word lines. For example, one such memory device can include an...
US-8,050,096 Programming method to reduce gate coupling interference for non-volatile memory
A non-volatile memory device and programming process is described that compensates for coupling effects on threshold gate voltages of adjacent floating gate or...
US-8,050,090 Memory page boosting method, device and system
A memory page boosting method, device and system for boosting unselected memory cells in a multi-level cell memory cell is described. The memory device includes...
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