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Patent # Description
US-8,094,047 Data serializer apparatus and methods
Some embodiments include apparatus and methods having an output line, clock nodes to receive clock signals, the clock signals being out of phase with each...
US-8,094,045 Data bus inversion apparatus, systems, and methods
Apparatus, systems, and methods are disclosed such as those that operate to encode data bits transmitted on a plurality of channels according to at least one of...
US-8,093,937 Seamless coarse and fine delay structure for high performance DLL
A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at a boundary of coarse and...
US-8,093,730 Underfilled semiconductor die assemblies and methods of forming the same
An apparatus and method may be used for packaging a semiconductor die and a carrier substrate to substantially prevent trapped moisture therebetween and provide...
US-8,093,725 High aspect ratio contacts
A contact formed in accordance with a process for etching a insulating layer to produce an opening having an aspect ratio of at least 15:1 by first exposing the...
US-8,093,702 Stacked microelectronic devices and methods for manufacturing stacked microelectronic devices
Stacked microelectronic devices and methods of manufacturing stacked microelectronic devices are disclosed herein. In one embodiment, a method of manufacturing...
US-8,093,666 Lanthanide yttrium aluminum oxide dielectric films
Electronic apparatus and methods of forming the electronic apparatus include a lanthanide yttrium aluminum oxide dielectric film on a substrate for use in a...
US-8,093,658 Electronic device with asymmetric gate strain
The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced...
US-8,093,643 Multi-resistive integrated circuit memory
A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a...
US-8,093,638 Systems with a gate dielectric having multiple lanthanide oxide layers
Electronic systems and methods of forming the electronic systems include a gate dielectric having multiple lanthanide oxide layers. Such electronic systems may...
US-8,093,576 Chemical-mechanical polish termination layer to build electrical device isolation
A method of forming a semiconductor device may comprise forming a memory portion, forming a carbon film, depositing insulation to at least partially cover the...
US-8,093,155 Method of controlling striations and CD loss in contact oxide etch
A method for controlling striations and CD loss in a plasma etching method is disclosed. During the etching process, the substrate of semiconductor material to...
US-8,093,129 Methods of forming memory cells
Some embodiments include methods of forming memory cells. A semiconductor construction may be provided, with such construction including tunnel dielectric...
US-8,093,090 Integrated circuit edge and method to fabricate the same
In the fabrication of an integrated circuit, a trench with a sidewall is formed along the periphery of the integrated circuit and the substrate is back-lapped...
US-8,090,999 Memory media characterization for development of signal processors
Methods and apparatus utilizing media characterization of memory devices facilitate the development of signal processors for analyzing memory device outputs....
US-8,090,955 Boot block features in synchronous serial interface NAND
Embodiments are provided for protecting boot block space in a NAND memory device connected to a host device via an SPI interface. One such method includes...
US-8,090,886 Direct secondary device interface by a host
A device has a controller and a function module configured to be in communication with the controller as a result of the controller receiving a pass-through...
US-8,089,816 Memory erase methods and devices
Memory devices and erase methods for memories are disclosed, such as those adapted to discharge an erase voltage from a memory block while protecting low...
US-8,089,805 Two-part programming methods and memories
Programming a memory in two parts to reduce cell disturb includes, in at least one embodiment, programming data in two or more sequences of programming pulses...
US-8,089,800 Memory cell
Methods, and circuits, are disclosed for operating a programmable memory device. One method embodiment includes storing a value as a state in a first memory...
US-8,089,542 CMOS imager with integrated circuitry
A CMOS imager is integrated on a single substrate along with logic and support circuitry for decoding and processing optical information received by the CMOS...
US-8,089,387 Quantizing circuits with variable parameters
Systems, methods, and devices for obtaining data from a data location. The method may include generating a first value by sensing a data location under a first...
US-8,089,142 Methods and apparatus for a stacked-die interposer
An improved stacked-die package includes an interposer which improves the manufacturability of the package. A semiconductor package includes a package substrate...
US-8,089,128 Transistor gate forming methods and integrated circuits
A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal...
US-8,089,123 Semiconductor device comprising transistor structures and methods for forming same
A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some...
US-8,088,691 Selective etch chemistries for forming high aspect ratio features and associated structures
An interlevel dielectric layer, such as a silicon oxide layer, is selectively etched using a plasma etch chemistry including a silicon species and a halide...
US-8,088,659 Method of forming capacitors
High dielectric films of mixed transition metal oxides of titanium and tungsten, or titanium and tantalum, are formed by sequential chemical vapor deposition...
US-8,088,643 Resistance variable memory device with nanoparticle electrode and method of fabrication
A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a...
US-8,088,551 Methods of utilizing block copolymer to form patterns
Some embodiments include methods of forming patterns in which a block copolymer-containing composition is formed over a substrate, and is then patterned to form...
US-8,088,293 Methods of forming reticles configured for imprint lithography
The invention includes methods of forming reticles configured for imprint lithography, methods of forming capacitor container openings, and methods in which...
US-8,086,920 Method of controlling a test mode of a circuit
A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. The test vector decode circuit is driven by an...
US-8,086,916 System and method for running test and redundancy analysis in parallel
A memory redundancy analyzing apparatus having a tester, a queue, and a redundancy analyzer is provided. The tester includes testing portions for different...
US-8,086,913 Methods, apparatus, and systems to repair memory
Methods, apparatus and systems pertain to performing READ, WRITE functions in a memory which is coupled to a repair controller. One such repair controller could...
US-8,086,790 Non-volatile memory device having assignable network identification
Memory devices and methods disclosed such as a memory device having a plurality of memory dies where each die includes a network identification that uniquely...
US-8,085,612 Method and apparatus for managing behavior of memory devices
A method of managing power consumption by a memory in a memory device includes determining whether the device is powered by a depletable power supply, and if it...
US-8,085,606 Input-output line sense amplifier having adjustable output drive capability
An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line...
US-8,085,596 Reducing noise in semiconductor devices
The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a...
US-8,085,594 Reading technique for memory cell with electrically floating body transistor
A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting...
US-8,085,591 Charge loss compensation during programming of a memory device
In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is...
US-8,085,584 Memory to store user-configurable data polarity
Subject matter disclosed herein relates to user configuration of polarity of data storage in memory devices.
US-8,084,866 Microelectronic devices and methods for filling vias in microelectronic devices
Microelectronic devices and methods for filling vias and forming conductive interconnects in microfeature workpieces and dies are disclosed herein. In one...
US-8,084,854 Pass-through 3D interconnect for microelectronic dies and associated systems and methods
Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a...
US-8,084,846 Balanced semiconductor device packages including lead frame with floating leads and associated methods
A semiconductor device assembly or package includes at least one semiconductor device that is positioned adjacent to floating leads. Such an assembly or package...
US-8,084,845 Subresolution silicon features and methods for forming the same
Novel etch techniques are provided for shaping silicon features below the photolithographic resolution limits. FinFET devices are defined by recessing oxide and...
US-8,084,843 N well implants to separate blocks in a flash memory device
A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is...
US-8,084,808 Zirconium silicon oxide films
Electronic apparatus and systems include structures having a dielectric layer containing a zirconium silicon oxide film. A zirconium silicon oxide film may be...
US-8,084,806 Isolation structure for a memory cell using A1.sub.2O.sub.3 dielectric
The invention provides, in one exemplary embodiment, an isolation gate formed over a substrate for biasing the substrate and providing isolation between...
US-8,084,370 Hafnium tantalum oxynitride dielectric
Electronic apparatus and methods may include a hafnium tantalum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium tantalum...
US-8,084,355 Methods of forming copper-comprising conductive lines in the fabrication of integrated circuitry
A method of forming copper-comprising conductive lines in the fabrication of integrated circuitry includes depositing damascene material over a substrate. Line...
US-8,084,345 Methods of forming dispersions of nanoparticles, and methods of forming flash memory cells
Some embodiments include methods of forming dispersions of nanoparticles. The nanoparticles are incorporated into first coordination complexes in which the...
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