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Patent # Description
US-8,039,327 Transistor forming methods
A transistor forming method includes forming a dielectric spacer in a trench surrounding an active area island, forming line openings through the spacer, and...
US-8,039,300 Reproducible resistance variable insulating memory devices and methods for forming same
The present invention relates to the use of a shaped bottom electrode in a resistance variable memory device. The shaped bottom electrode ensures that the...
US-8,039,287 Method of forming high gain, low noise, photodiode sensor for image sensors
Embodiments of the present invention provide a pixel cell for an image sensor that includes a photodiode, which provides high gain, low noise, and low dark...
US-8,037,446 Methods for defining evaluation points for optical proximity correction and optical proximity correction...
Methods are disclosed for defining evaluation points for use in optical proximity correction of a rectangular target geometry. A method for defining evaluation...
US-8,037,381 Error detection, documentation, and correction in a flash memory device
A memory device has an error documentation memory array that is separate from the primary memory array. The error documentation memory array stores data...
US-8,037,378 Automatic test entry termination in a memory device
A memory device has a control register comprising a test mode disable bit. The test mode is initially enabled. If the device does not receive an appropriate key...
US-8,036,334 Delay lock loop phase glitch error filter
A method and apparatus is provided for providing a phase glitch error filter for a delay lock loop. The device comprises a delay lock loop to provide an output...
US-8,036,058 Symmetrically operating single-ended input buffer devices and methods
Embodiments are described including those pertaining to an input buffer having first and second complementary input terminals. One such input buffer has a...
US-8,036,035 Erase cycle counter usage in a memory device
Memory devices and methods are disclosed to facilitate adjustment of program voltages applied during a program operation based upon erase operation cycle...
US-8,036,019 Resistive memory
The present disclosure includes resistive memory devices and systems having resistive memory cells, as well as methods for operating the resistive memory cells....
US-8,036,016 Maintenance process to enhance memory endurance
Subject matter disclosed herein relates to enhancing an operational lifespan of non-volatile memory.
US-8,035,433 Process insensitive delay line
A delay line including a phase detector having two inputs and one output. The first input of the phase detector is connected to an input of the delay line. The...
US-8,035,189 Semiconductor constructions
The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can...
US-8,035,179 Packaged microelectronic imagers and methods of packaging microelectronic imagers
Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in...
US-8,035,160 Recessed access device for a memory
Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming...
US-8,035,142 Deuterated structures for image sensors and methods for forming the same
A pixel cell with a photo-conversion device and at least one structure includes a deuterated material adjacent the photo-conversion device.
US-8,035,129 Integrated circuitry
This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer...
US-8,034,728 Systems and methods for forming metal oxides using metal diketonates and/or ketoimines
A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a...
US-8,034,716 Semiconductor structures including vertical diode structures and methods for making the same
Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode...
US-8,034,706 Contact formation
The present disclosure includes various method of contact embodiments. One such method embodiment includes creating a trench in an insulator stack material of a...
US-8,034,702 Methods of forming through substrate interconnects
A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the...
US-8,034,687 Methods of forming a plurality of transistor gates, and methods of forming a plurality of transistor gates...
A method of forming a plurality of transistor gates having at least two different work functions includes forming first and second transistor gates over a...
US-8,034,655 Non-volatile resistive oxide memory cells, non-volatile resistive oxide memory arrays, and methods of forming...
A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate....
US-8,034,516 Photomasks, methods of forming photomasks, and methods of photolithographically-patterning substrates
Some embodiments include methods of forming photomasks. A stack of at least three different materials is formed over a base. Regions of the stack are removed to...
US-8,034,315 Methods of forming devices comprising carbon nanotubes
Some embodiments include devices that contain bundles of CNTs. An undulating topography extends over the CNTs and within spaces between the CNTs. A global...
US-8,033,884 Methods of forming plasma-generating structures; methods of plasma-assisted etching, and methods of...
Some embodiments include methods of forming plasma-generating microstructures. Aluminum may be anodized to form an aluminum oxide body having a plurality of...
US-8,032,804 Systems and methods for monitoring a memory system
Systems and methods are disclosed herein, including those that operate to monitor a first set of operational parameters associated with a memory vault, to...
US-8,032,778 Clock distribution apparatus, systems, and methods
Apparatus, systems, and methods are disclosed that operate to adjust power received by a clock distribution network at least partially based on operating...
US-8,032,694 Direct logical block addressing flash memory mass storage architecture
A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle...
US-8,032,350 Techniques for generating and simulating a simulatable vector having amplitude noise and/or timing jitter added...
Methods for generating realistic waveform vectors with controllable amplitude noise and timing jitter, simulatable in a computer-based simulation environment...
US-8,031,529 Memory cell threshold voltage drift estimation methods and apparatus
Methods of operating memory devices include determining a threshold voltage drift of two or more reference memory cells of the memory device programmed to only...
US-8,031,518 Methods, structures, and devices for reducing operational energy in phase change memory
Methods of forming and operating phase change memory devices include adjusting an activation energy barrier between a metastable phase and a stable phase of a...
US-8,031,249 Missing pixel architecture
An active pixel sensor (APS) comprises a regular repeating pattern of geometrically similar pixel regions, active pixels of which have photodiodes formed...
US-8,030,952 Power sink for IC temperature control
The use of a power sink function in IC testing results in a simple and rapid method for testing ICs, and assembled modules, at elevated temperature profiles...
US-8,030,780 Semiconductor substrates with unitary vias and via terminals, and associated systems and methods
Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a...
US-8,030,751 Board-on-chip type substrates with conductive traces in multiple planes and semiconductor device packages...
A method for fabricating a chip-scale board-on-chip substrate, or redistribution element, includes forming conductive planes on opposite sides of a substrate. A...
US-8,030,748 Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing...
A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second ...
US-8,030,636 Enhanced memory density resistance variable memory cells, arrays, devices and systems including the same, and...
A resistance variable memory cell and method of forming the same. The memory cell includes a first electrode and at least one layer of resistance variable...
US-8,030,218 Method for selectively modifying spacing between pitch multiplied structures
Methods for circuit material processing are provided. In at least one such method, a substrate is provided with a plurality of overlying spacers. The spacers...
US-8,030,217 Simplified pitch doubling process flow
A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further...
US-8,030,211 Methods for forming bit line contacts and bit lines during the formation of a semiconductor device
A method for forming a semiconductor device comprises forming first and second bit lines at different levels. Forming the bit lines at different levels...
US-8,030,170 Methods of forming isolation structures, and methods of forming nonvolatile memory
Some embodiments include methods of forming isolation structures. A trench may be formed to extend into a semiconductor material. Polysilazane may be formed...
US-8,030,168 Methods of forming DRAM memory cells
The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an...
US-8,030,156 Methods of forming DRAM arrays
Methods of etching into silicon oxide-containing material with an etching ambient having at least 75 volume percent helium. The etching ambient may also include...
US-8,029,947 Systems and methods for implementing and manufacturing reticles for use in photolithography tools
Methods, systems, and tool sets involving reticles and photolithography processing. Several embodiments of the invention are directed toward obtaining...
US-8,029,858 Methods of forming material on a substrate, and a method of forming a field effect transistor gate oxide on a...
The invention includes methods of forming material on a substrate and methods of forming a field effect transistor gate oxide. In one implementation, a first...
US-8,028,198 Devices, methods, and apparatuses for detection, sensing, and reporting functionality for semiconductor memory
Methods, apparatuses and systems are disclosed for a memory device. In one embodiment, a memory device is disclosed that may include a command error module...
US-8,027,200 Reduction of quick charge loss effect in a memory device
Methods for reducing quick charge loss effects, methods for programming, memory devices, memory devices, and memory systems are disclosed. In one such method, a...
US-8,027,187 Memory sensing devices, methods, and systems
The present disclosure includes devices, methods, and systems for sensing memory, such as resistance variable memory, among other types of memory. One or more...
US-8,026,967 Rolling shutter for prevention of blooming
A rolling shutter technique for a pixel array is described in which multiple rows of the array are hard reset as the shutter moves down the array. As the...
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