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Erase verification for flash memory
Example embodiments for verifying an erase operation for a flash memory device may comprise, for one or more embodiments, utilizing program operation...
Single transistor memory cell
A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one...
Anti-eclipsing circuit for image sensors
An anti-eclipse circuit of an image pixel includes a clamping circuit for pulling up a voltage of a reset signal output by the pixel and an eclipse detection...
Embodiments are provided that include a memory die, memory devices, and methods, such as those comprising a voltage generator, including an output voltage and...
Method and structure to reduce optical crosstalk in a solid state imager
Methods and structures to reduce optical crosstalk in solid state imager arrays. Sections of pixel material layers that previously would have been etched away...
Memory arrays, semiconductor constructions and electronic systems with
transistor gates extending partially...
Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within...
Ultra thin TCS (SiCl.sub.4) cell nitride for DRAM capacitor with DCS
(SiH.sub.2Cl.sub.2) interface seeding layer
A method for forming silicon nitride films on semiconductor devices is provided. In one embodiment of the method, a silicon-comprising substrate is first...
Methods of forming trench isolation in the fabrication of integrated
circuitry and methods of fabricating...
First and second isolation trenches are formed into semiconductive material of a semiconductor substrate. The first isolation trench has a narrowest outermost...
Methods of manufacturing imaging device packages
Methods of manufacturing an imaging device package are provided. In accordance with an embodiment a sensor die may be coupled to bond pads on a transparent...
Efficient pitch multiplication process
Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated...
Methods of making crystalline tantalum pentoxide
There is disclosed a method of forming crystalline tantalum pentoxide on a ruthenium-containing material having an oxygen-containing surface wherein the...
Semiconductor workpiece carriers and methods for processing semiconductor
Semiconductor workpiece carriers and methods for processing semiconductor workpieces are disclosed herein. In one embodiment, a semiconductor workpiece carrier...
Supercritical fluid-assisted direct write for printing integrated circuits
High resolution patterns provided on a surface of a semiconductor substrate and methods of direct printing of such high resolution patterns are disclosed. The...
Methods of providing semiconductor components within sockets
The invention includes methods of utilizing removable mechanical precising mechanisms and/or optical-based precising mechanisms to align chips within sockets....
Method for forming and planarizing adjacent regions of an integrated
Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction...
Memory system and method using stacked memory device dice, and system
using the memory system
A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that...
System and method for mitigating reverse bias leakage
The present disclosure includes devices, methods, and systems for programming memory, such as resistance variable memory. One embodiment can include an array of...
Non-volatile memory apparatus and methods
Some embodiments include apparatus and methods having memory cells coupled in series and a module to cause an application of voltages with at least three...
Device and method for using dynamic cell plate sensing in a DRAM memory
A memory cell, device, system and method for operating a memory cell utilize an isolated dynamic cell plate. The memory cell includes a first and second pass...
Open pattern inductor
Various embodiments includes a stacked open pattern inductor fabricated above a semiconductor substrate. The stacked open pattern inductor includes a plurality...
Multi-phase signal generator and method
Multi-phase signal generators and methods for generating multi-phase signals are described. In one embodiment, the clock generator generates quadrature clock...
Balanced phase detector
Methods and apparatus are disclosed, such as those involving a digital phase detector that includes a phase detection circuit configured to detect which one of...
Method to create a metal pattern using a damascene-like process
A method of forming a metal pattern on a dielectric layer that comprises forming at least one trench in a dielectric layer formed from a photosensitive,...
Conductive interconnect structures and formation methods using
Conductive interconnect structures and formation methods using supercritical fluids are disclosed. A method in accordance with one embodiment of the invention...
Select devices including an open volume, memory devices and systems
including same, and methods for forming same
Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a...
Dual work function recessed access device and methods of forming
A recessed access device having a gate electrode formed of two or more gate materials having different work functions may reduce the gate-induced drain leakage...
Castellation wafer level packaging of integrated circuit chips
Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled...
Methods and apparatuses for heating semiconductor wafers
Methods and apparatuses for heat treatment of semiconductor wafers are disclosed herein. A method of heating a semiconductor wafer in accordance with one...
Programming error correction code into a solid state memory device with
varying bits per cell
Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to...
Reducing data hazards in pipelined processors to provide high processor
A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of...
Flexible results pipeline for processing element
A flexible results pipeline for a processing element of a parallel processor is described. A plurality of result registers are selectively connected to each...
Command interface systems and methods
Apparatus, systems, and methods are disclosed that operate within a memory to execute internal commands, to suspend the execution of commands during a transfer...
Power saving memory apparatus, systems, and methods
Some embodiments include a voltage generator to generate a voltage to apply to a line used to access a memory cell of a memory device in which the voltage is...
Data bus power-reduced semiconductor storage apparatus
In one or more of the disclosed embodiments, the number of times toggle operations of a data bus are performed at the time of a data transmission in a...
Single latch data circuit in a multiple level cell non-volatile memory
A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a...
Configurable digital and analog input/output interface in a memory device
Methods and memory devices are disclosed, for example a memory device that has both an analog path and a digital path that both share the same input/output pad....
Spintronic devices with integrated transistors
The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a...
Methods, devices, and systems for a high voltage tolerant buffer
Methods, devices, and systems are disclosed, including those for a buffer having pre-driver circuitry configured to provide voltages to thin-gate dielectric...
The present disclosure includes various method, device, and system embodiments for isolation circuits. One such isolation circuit embodiment includes: a first...
Electromagnetic radiation conduits
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
Memory device transistors
Method and device embodiments are described for fabricating MOSFET transistors in a semiconductor also containing non-volatile floating gate transistors. MOSFET...
Apparatus having a dielectric containing scandium and gadolinium
Apparatus having a dielectric containing scandium and gadolinium can provide a reliable structure with a high dielectric constant (high k). In an embodiment,...
Bottom electrode geometry for phase change memory
A PCRAM cell has a gradated or layered resistivity bottom electrode with higher resistivity closer to a phase change material, to provide partial heating near...
Multiple spacer steps for pitch multiplication
Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers...
Methods of forming variable resistance memory cells, and methods of
etching germanium, antimony, and...
A method of etching a material that includes comprising germanium, antimony, and tellurium encompasses exposing said material to a plasma-enhanced etching...
Low resistance metal silicide local interconnects and a method of making
A process for forming a local interconnect includes applying a layer of metal over a semiconductor layer. A layer of metal silicide is formed over the layer of...
Devices, methods, and systems for semiconductor processing are described herein. A number of method embodiments of semiconductor processing can include forming...
Methods of processing semiconductor substrates in forming scribe line
A method of processing a semiconductor substrate in forming scribe line alignment marks includes forming pitch multiplied non-circuitry features within scribe...
Masking techniques and templates for dense semiconductor fabrication
A template comprising pitch multiplied and non-pitch multiplied features is configured for use in imprint lithography. On a first substrate, a first pattern is...
Plasma processing, deposition and ALD methods
A plasma processing method includes providing a substrate in a processing chamber, the substrate having a surface, and generating a plasma in the processing...