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Patent # Description
US-8,026,966 Method, apparatus and system providing a storage gate pixel with high dynamic range
A method, apparatus and system are described providing a high dynamic range pixel. An integration period has multiple sub-integration periods during which...
US-8,026,750 Delay locked loop circuit and method
Delay locked loop circuits and methods are disclosed. In the embodiments, a delay locked loop may include a phase detector to detect a phase difference between...
US-8,026,747 Apparatus and method for multi-phase clock generation
An apparatus and method for multi-phase clock generation are disclosed. One embodiment of the apparatus includes a module generating first and second...
US-8,026,740 Multi-level signaling for low power, short channel applications
Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits....
US-8,026,702 Voltage regulator system
The present disclosure includes circuits, systems and methods for regulating voltage. One voltage regulator system embodiment includes a voltage regulator...
US-8,026,579 Silicon pillars for vertical transistors
In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used....
US-8,026,542 Low resistance peripheral local interconnect contacts with selective wet strip of titanium
Methods for forming memory devices and integrated circuitry, for example, DRAM circuitry, structures and devices resulting from such methods, and systems that...
US-8,026,501 Method of removing or deposting material on a surface including material selected to decorate a particle on the...
A method that may be applied to imaging and identifying defects and contamination on the surface of an integrated circuit is described. An energetic beam, such...
US-8,026,180 Methods of modifying oxide spacers
Methods for reducing line roughness of spacers and other features utilizing a non-plasma and non-wet etch fluoride processing technology are provided....
US-8,026,161 Highly reliable amorphous high-K gate oxide ZrO2
A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO.sub.2 gate oxides...
US-8,026,148 Methods of utilizing silicon dioxide-containing masking structures
Some embodiments include methods of forming capacitors. Storage nodes are formed within a material. The storage nodes have sidewalls along the material. Some of...
US-8,025,809 Polishing methods
A chemical-mechanical polishing (CMP) method includes applying a solid abrasive material to a substrate, polishing the substrate, flocculating at least a...
US-8,024,629 Input/output compression and pin reduction in an integrated circuit
An I/O compression apparatus, for testing a memory array and/or a logic circuit, is comprised of a selectable compression circuit that outputs compressed test...
US-8,024,533 Host memory interface for a parallel processor
A memory interface for a parallel processor which has an array of processing elements and can receive a memory address and supply the memory address to a memory...
US-8,024,388 DVI link with parallel test data
An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random...
US-8,023,350 Memory malfunction prediction system and method
A memory malfunction prediction system and method, such as those that sequentially stress each row of memory cells in an array by decreasing the refresh rate of...
US-8,023,344 Data retention kill function
Various data protection techniques are provided. In one embodiment, a memory device is provided. The memory device may initiate a security measure upon...
US-8,023,343 Systems and methods for issuing address and data signals to a memory array
Embodiments of the present invention include circuitry for issuing address and data signals to a memory array using a system clock and a write clock. A locked...
US-8,023,340 Signal transfer apparatus and methods
Some embodiments include a number of nodes configured to receive a number of signals. The signals may represent information stored in a number of memory cells...
US-8,023,334 Program window adjust for memory cell signal line delay
A memory device and programming and/or reading process is described that compensates for memory cell signal line propagation delays, such as to increase the...
US-8,023,332 Cell deterioration warning apparatus and method
Memory devices and methods adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate...
US-8,023,329 Reducing effects of program disturb in a memory device
A selected word line that is coupled to cells for programming is biased with an initial programming voltage. The unselected word lines that are adjacent to the...
US-8,023,324 Memory controller self-calibration for removing systemic influence
Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After...
US-8,023,293 On-die anti-resonance structure for integrated circuit
A structure and method for reducing the effects of chip-package resonance in an integrated circuit assembly is described. A series RLC circuit is employed to...
US-8,022,729 Signal driver circuit having adjustable output voltage for a high logic level output signal
A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured...
US-8,022,536 Semiconductor substrate for build-up packages
The present invention provides techniques to fabricate build-up single or multichip modules. In one embodiment, this is accomplished by dispensing die-attach...
US-8,022,473 Semiconductor device having reduced sub-threshold leakage
A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed...
US-8,022,385 Memory devices with buried lines
A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically...
US-8,022,147 Zwitterionic block copolymers and methods
Zwitterionic block copolymers having oppositely charged or chargeable terminal groups, and methods of making and using the same, are disclosed. The zwitterionic...
US-8,021,981 Redistribution layers for microfeature workpieces, and associated systems and methods
Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system...
US-8,021,908 Method and apparatus for dark current and blooming suppression in 4T CMOS imager pixel
A method and apparatus for operating an imager pixel that includes the act of applying a relatively small first polarity voltage and a plurality of pulses of a...
US-8,021,897 Methods of fabricating a cross point memory array
Some embodiments include cross-point memory structures. The structures may include a line of first electrode material extending along a first horizontal...
US-8,019,967 Robust index storage for non-volatile memory
A non-volatile memory data address translation scheme is described that utilizes a hierarchal address translation system that is stored in the non-volatile...
US-8,019,932 Block management for mass storage
An embodiment of the present invention includes a nonvolatile memory system comprising nonvolatile memory for storing sector information, the nonvolatile memory...
US-8,018,791 Circuit, system and method for controlling read latency
A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit...
US-8,018,778 Memory read methods, apparatus, and systems
Some embodiments include first memory cells and a first line used to access the first memory cells, second memory cells and at least one second line used to...
US-8,018,770 Program and sense operations in a non-volatile memory device
Methods for programming and sensing in a memory device, a data cache, and a memory device are disclosed. In one such method, all of the bit lines of a memory...
US-8,018,752 Configurable bandwidth memory devices and methods
Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for...
US-8,018,261 Clock generator and methods using closed loop duty cycle correction
Closed-loop duty-cycle correctors (DCCs), clock generators, memory devices, systems, and methods for generating an output clock signal having a particular duty...
US-8,018,258 Periodic signal synchronization apparatus, systems, and methods
Apparatus, systems, and methods are disclosed that operate to generate a periodic output signal from a periodic input signal, obtain a plurality of samples of a...
US-8,018,015 Buried conductor for imagers
A pixel cell having a photo-conversion device at a surface of a substrate and at least one contact area from which charge or a signal is output or received. A...
US-8,017,988 High density stepped, non-planar flash memory
A first plurality of memory cells is in a first plane in a first column of the array. A second plurality of memory cells is in a second plane in the same...
US-8,017,985 Concentric or nested container capacitor structure for integrated circuits
Disclosed are embodiments for a container capacitor structure in which at least two container capacitors, e.g., an inner and outer container capacitor, are made...
US-8,017,982 Imagers with contact plugs extending through the substrates thereof and imager fabrication methods
Methods for fabricating photoimagers, such as complementary metal-oxide-semiconductor (CMOS) imagers, include fabricating image sensing elements, transistors,...
US-8,017,481 Methods of forming nanoscale floating gate
A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first...
US-8,017,184 .beta.-diketiminate ligand sources and metal-containing compounds thereof, and systems and methods including same
The present invention provides metal-containing compounds that include at least one .beta.-diketiminate ligand, and methods of making and using the same. In...
US-8,015,460 Test mode for parallel load of address dependent data to enable loading of desired data backgrounds
One or more embodiments of the invention enable a memory device to load its memory array with desired background data, such as to reduce total test time and...
US-8,015,384 Memory hub architecture having programmable lane widths
A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input...
US-8,014,222 Control of inputs to a memory device
A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with...
US-8,014,220 Current mode data sensing and propagation using voltage amplifier
A method and a circuit for current mode data sensing and propagation by using voltage amplifier are provided. Example embodiments may include providing an...
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