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Patent # Description
US-8,001,513 Integrated circuit apparatus, systems, and methods
High density circuit modules are formed by stacking integrated circuit (IC) chips one above another. Unused input/output (I/O) locations on some of the chips...
US-8,001,410 Efficient clocking scheme for ultra high-speed systems
There is provided a system for comparing the phase characteristics of three generated clock signals, each having a unique phase relationship with an original...
US-8,000,152 Charge pump operation in a non-volatile memory device
A charge pump in a memory device is activated to produce a programming voltage prior to data loading during a programming operation. During an initial...
US-8,000,151 Semiconductor memory column decoder device and method
Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in...
US-8,000,136 Non-volatile memory with both single and multiple level cells
Memory arrays and methods of operating such memory arrays are described as having a memory cell operated as a single level cell interposed between and coupled...
US-7,999,589 Circuits and methods for clock signal duty-cycle correction
Duty-cycle correction circuits, clock distribution networks, and methods for correcting duty-cycle distortion are disclosed, including methods and apparatus for...
US-7,999,334 Hafnium tantalum titanium oxide films
Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed...
US-7,999,330 Dynamic random access memory device and electronic systems
The invention includes methods of utilizing compositions containing iridium and tantalum in semiconductor constructions, and includes semiconductor...
US-7,999,328 Isolation trench having first and second trench areas of different widths
A method of forming and resulting isolation region, which allows for densification of an oxide layer in the isolation region. One exemplary embodiment of the...
US-7,998,860 Method for fabricating semiconductor components using maskless back side alignment to conductive vias
A method for fabricating semiconductor components includes the steps of: providing a semiconductor substrate having a circuit side, a back side and conductive...
US-7,998,813 Methods of fabricating an access transistor having a polysilicon-comprising plug on individual of opposing...
Fabrication methods for gate transistors in integrated circuit devices enable the formation of recessed access device structures or FinFET structures having...
US-7,998,809 Method for forming a floating gate using chemical mechanical planarization
An improved process forming a floating gate region of a semiconductor memory device. The process includes using a ceria slurry for chemical mechanical...
US-7,998,305 Electrical interconnect using locally conductive adhesive
An anisotropic electrically conducting interconnect is disclosed in which an adhesive comprising particles having a breakable coating of at least one...
US-7,997,958 Apparatuses and methods for conditioning polishing pads used in polishing micro-device workpieces
Apparatuses and methods for conditioning polishing pads used in polishing micro-device workpieces are disclosed herein. In one embodiment, an end effector for...
US-7,997,954 Centerless grinding method
To provide a centerless grinding method which facilitates a tooling change and enables automation. A blade 11 is disposed slidable along a first straight line...
US-7,996,727 Error correction for memory
Methods and devices operate to apply and provide differing levels of error correction within a multi-level, non-volatile memory. In an example, the differing...
US-7,995,415 System and method for reducing power consumption during extended refresh periods of dynamic random access...
A dynamic random access memory ("DRAM") device is operable in either a normal refresh mode or a static refresh mode, such as a self-refresh mode. A cell plate...
US-7,995,412 Analog-to-digital and digital-to-analog conversion window adjustment based on reference cells in a memory device
An analog-to-digital conversion window is defined by reference voltages stored in reference memory cells of a memory device. A first reference voltage is read...
US-7,995,402 Method for erasing a semiconductor magnetic memory integrating a magnetic tunneling junction above a...
A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating...
US-7,995,400 Reducing effects of program disturb in a memory device
The programming disturb effects in a semiconductor non-volatile memory device are reduced by biasing unselected word lines of a memory block with a negative...
US-7,995,399 NAND memory device and programming methods
A NAND Flash memory device reduces circuitry noise during program operations. The memory includes bit lines that are electrically coupled together to charge...
US-7,995,395 Charge loss compensation during programming of a memory device
A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a...
US-7,995,391 Multiple select gates with non-volatile memory cells
Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and...
US-7,995,365 Method and apparatuses for managing double data rate in non-volatile memory
Described herein are a method and apparatuses for providing DDR memory access. In one embodiment, an apparatus includes a data storage unit to store and...
US-7,994,849 Devices, systems, and methods for generating a reference voltage
Methods, devices, and systems are disclosed for a voltage reference generator. A voltage reference generator may comprise a bandgap voltage reference circuit...
US-7,994,595 Strained semiconductor by full wafer bonding
One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined...
US-7,994,566 Stacked non-volatile memory with silicon carbide-based amorphous silicon finFETs
A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a...
US-7,994,547 Semiconductor devices and assemblies including back side redistribution layers in association with through...
Low temperature processed back side redistribution lines (RDLs) are disclosed. Low temperature processed back side RDLs may be electrically connected to the...
US-7,994,491 PCRAM device with switching glass layer
A method of forming a memory device, such as a PCRAM, including selecting a chalcogenide glass backbone material for a resistance variable memory function and...
US-7,994,464 Dual conversion gain gate and capacitor combination
A pixel cell array architecture having a dual conversion gain. A dual conversion gain element is coupled between a floating diffusion region and a respective...
US-7,993,988 Techniques for fabricating a non-planar transistor
Methods for fabricating a non-planar transistor. Fin field effect transistors (finFETs) are often built around a fin (e.g., a tall, thin semiconductive member)....
US-7,993,977 Method of forming molded standoff structures on integrated circuit devices
A method of forming molding standoff structures on integrated circuit devices is disclosed which includes forming a plurality of standoff structures on a...
US-7,993,957 Phase change memory cell and manufacturing method thereof using minitrenches
A process forms a phase change memory cell using a resistive element and a memory region of a phase change material. The resistive element has a first thin...
US-7,993,944 Microelectronic imagers with optical devices having integral reference features and methods for manufacturing...
Microelectronic imager assemblies with optical devices having integral reference features and methods for assembling such microelectronic imagers is disclosed...
US-7,993,539 Methods of etching nanodots, methods of removing nanodots from substrates, methods of fabricating integrated...
Embodiments of the invention include methods of etching nanodots, to methods of removing nanodots from substrates, and to methods of fabricating integrated...
US-7,992,297 Method for forming a circuit board via structure for high speed signaling
One embodiment of the invention comprises an improved method for making a via structure for use in a printed circuit board (PCB). The via allows for the passage...
US-7,992,060 Apparatus, methods, and system of NAND defect management
Various embodiments comprise apparatus, methods, and systems including method comprising searching for a group address among a plurality of group addresses in a...
US-7,991,947 Multi-priority encoder
A multi-priority encoder includes a plurality of interconnected, single-priority encoders arranged in descending priority order. The multi-priority encoder...
US-7,991,098 Method and apparatus for training the reference voltage level and data sample timing in a receiver
Methods and apparatuses for calculating the location of an optimal sampling point for a receiver system are disclosed. In brief, a first method comprises...
US-7,990,802 Selective edge phase mixing
Electronic apparatus, systems, and methods to implement selective edge phase mixing are disclosed. A selective edge phase mixing system includes a processor and...
US-7,990,792 Hybrid sense amplifier and method, and memory device using same
Sense circuits, devices and methods are disclosed, including a sense amplifier circuit that has first and second complementary data lines and a sensing circuit....
US-7,990,775 Methods of operating memory devices including different sets of logical erase blocks
Methods of operating memory devices include storing data of a first type in a first set of logical erase blocks and storing data of a second type in a second...
US-7,990,772 Memory device having improved programming operation
Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and...
US-7,990,763 Memory with weighted multi-page read
A memory device provides increased output data to help evaluate data errors arising from bit line coupling and floating gate coupling during a read operation....
US-7,990,427 Method and apparatus for applying tonal correction to images
A method and apparatus for applying tonal correction to images to obtain a more pleasing photographic image by redistributing low-key, mid-tone and high-key...
US-7,990,391 Memory system having multiple address allocation formats and method for use thereof
A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of...
US-7,990,163 Systems and methods for defect testing of externally accessible integrated circuit interconnects
Apparatus and methods provide built-in testing enhancements in integrated circuits. These testing enhancements permit, for example, continuity testing to pads...
US-7,989,957 Self-aligned, integrated circuit contact
Embodiments concern contacts for use in integrated circuits, which have a reduced likelihood of shorting to unrelated portions of an overlying conductive layer...
US-7,989,870 Use of dilute steam ambient for improvement of flash devices
A flash memory integrated circuit and a method for fabricating the same. A gate stack includes an initial oxide layer directly in contact with a silicon layer,...
US-7,989,866 DRAM layout with vertical FETS and method of formation
DRAM cell arrays having a cell area of about 4 F.sup.2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The...
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