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Patent # Description
US-9,559,194 Transistors and methods of forming transistors
Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. First channel...
US-9,559,163 Memory arrays
The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom...
US-9,559,118 Vertical ferroelectric field effect transistor constructions, constructions comprising a pair of vertical...
A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating...
US-9,559,109 Memory including blocking dielectric in etch stop tier
Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to...
US-9,559,087 Techniques for packaging multiple device components
Techniques for fabricating multiple device components. Specifically, techniques for fabricating a stacked package comprising at least one I/C module and a...
US-9,559,086 Semiconductor device with modified current distribution
Semiconductor devices having modified current distribution and methods of forming the same are described herein. As an example, a memory die in contact with a...
US-9,559,080 Integrated circuit device packages and methods for manufacturing integrated circuit device packages
An integrated circuit device package may include a flexible substrate having a first wiring, an integrated circuit device having a second wiring, a flexible...
US-9,558,851 Soft post package repair of memory devices
Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store...
US-9,558,844 Identifying stacked dice
Various embodiments comprise apparatuses to assign unique device identifier values to addressable devices in a stacked package. In one embodiment, an apparatus...
US-9,558,831 Non-volatile memory programming
Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying voltages to data lines...
US-9,558,803 Fixed voltage sensing in a memory device
Methods for sensing ferroelectric memory devices and apparatuses using the same have been disclosed. One such apparatus includes a ferroelectric memory cell...
US-9,558,799 Timing violation handling in a synchronous interface memory
A memory device includes an operation having a phase to provide an upper row address from a row address buffer, a phase to combine the upper row address with a...
US-9,558,143 Interconnect systems and methods using hybrid memory cube links to send packetized data over different...
System on a Chip (SoC) devices include two packetized memory buses for conveying local memory packets and system interconnect packets. In an in-situ...
US-9,558,064 Estimating an error rate associated with memory
The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored...
US-9,558,063 Semiconductor device and error correction method
A device is provided with: memory cell array including plurality of first and second memory cells and one or more third memory cells; judging circuit that...
US-9,557,926 Integrity of an address bus
A memory device has a controller, an address integrity feature, and an address register. The controller is configured to store error correction data in the...
US-9,557,800 Sequence power control
The present disclosure includes apparatuses and methods for sequence power control. A number of embodiments include executing a number of sequences associated...
US-9,557,376 Apparatuses and methods for die seal crack detection
Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around...
US-9,555,416 Jet mill
Disposed is a jet mill that has a cylindrical pulverization chamber (10) and a classification chamber (6) that connects to the pulverization chamber (10). A...
US-9,554,071 Method and apparatus providing pixel storage gate charge sensing for electronic stabilization in imagers
An imaging device that stores charge from a photosensor under at least one storage gate. A driver used to operate the at least one storage gate, senses how much...
US-9,553,264 Memory cells and semiconductor structures including electrodes comprising a metal, and related methods
Memory cells (e.g., CBRAM cells) include an ion source material over an active material and an electrode comprising metal silicide over the ion source material....
US-9,553,263 Resistive memory elements including buffer materials, and related memory cells, memory devices, electronic systems
A resistive memory element comprises a first electrode, an active material over the first electrode, a buffer material over the active material and comprising...
US-9,553,262 Arrays of memory cells and methods of forming an array of memory cells
An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced...
US-9,553,259 Magnetic tunnel junctions
A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material. A conductive second magnetic electrode is...
US-9,553,193 Double gated fin transistors and methods of fabricating and operating the same
A semiconductor device is provided that includes a fin having a first upper gate on a sidewall of the fin in a first trench and a second upper gate formed on...
US-9,553,177 Vertically base-connected bipolar transistor
Methods, devices, and systems for using and forming vertically base-connected bipolar transistors have been shown. The vertically base-connected bipolar...
US-9,553,103 Memory cell profiles
Examples of the present disclosure provide devices and methods for processing a memory cell. A method embodiment includes removing a key-hole shaped column from...
US-9,553,082 Process for improving critical dimension uniformity of integrated circuit arrays
Methods for patterning integrated circuit (IC) device arrays employing an additional mask process for improving center-to-edge CD uniformity are disclosed. In...
US-9,552,986 Forming a memory device using sputtering to deposit silver-selenide film
A method of sputter depositing silver selenide and controlling the stoichiometry and nodular defect formations of a sputter deposited silver-selenide film. The...
US-9,552,895 Autorecovery after manufacturing/system integration
Memory devices storing particular data, systems containing such memory devices and methods of testing such memory devices. The memory devices include an array...
US-9,552,888 Methods, devices, and systems for data sensing
Methods and devices for data sensing are disclosed. One such method includes performing a number of successive sense operations on a number of memory cells...
US-9,552,876 Descending set verify for phase change memory
Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.
US-9,552,875 Apparatuses and methods for sensing using an integration component
The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include circuitry to provide a...
US-9,552,866 Semiconductor device including subword driver circuit
The present invention is provided with: subword drivers SWD for driving subword lines SWL, a selection circuit for supplying either negative potential VKK1 or...
US-9,552,864 Offset compensation for ferroelectric memory cell sensing
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Offsets in the threshold voltage of switching components (e.g.,...
US-9,552,858 STT-MRAM cell structure incorporating piezoelectric stress material
A magnetic memory cell including a piezoelectric material, and methods of operating the memory cell are provided. The memory cell includes a stack, and the...
US-9,552,856 Memory timing self-calibration
Methods for memory input timing self-calibration, apparatuses for input timing self-calibration, and systems are disclosed. One such method includes...
US-9,552,311 Method for assigning addresses to memory devices
A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an...
US-9,552,257 Memory cell coupling compensation
Methods for memory cell coupling compensation and apparatuses configured to perform the same are described. One or more methods for memory cell coupling...
US-9,548,450 Devices containing metal chalcogenides
Some embodiments include a device having a conductive material, a metal chalcogenide-containing material, and a region between the metal chalcogenide-containing...
US-9,548,447 Integrated memory and methods of forming repeating structures
Some embodiments include integrated memory having an array of repeating plates across a plurality of nodes. The array includes rows and columns. The plates...
US-9,548,444 Magnetic memory cells and methods of formation
Memory cells including cell cores having free regions are disclosed. The free regions exhibit a strain that affects a magnetization orientation within the cell...
US-9,548,335 Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines
The present disclosure includes methods and apparatuses that include resistive memory. A number of embodiments include a first memory cell coupled to a data...
US-9,548,286 Solid state lights with thermal control elements
A solid state light ("SSL"), a solid state emitter ("SSE"), and methods of manufacturing SSLs and SSEs. In one embodiment, an SSL comprises a packaging...
US-9,546,099 Systems and methods for water purification
An evaporator assembly includes an inlet member and a diffuser, and receives a mixture of a gas and a solution to vaporize a portion of a solvent from the...
US-9,544,164 Computerized apparatus with a high speed data bus
A computerized apparatus configured for high-speed data transactions between components thereof. In one embodiment, the computerized apparatus includes a...
US-9,543,930 Apparatuses and methods for duty cycle adjustment
Apparatuses and methods for duty cycle adjustment are disclosed herein. An example apparatus may include a node, a phase mixer, and a duty cycle adjuster...
US-9,543,503 Magnetic memory cells and methods of fabrication
A magnetic cell includes a magnetic tunnel junction that comprises magnetic and nonmagnetic materials exhibiting hexagonal crystal structures. The hexagonal...
US-9,543,433 Dual work function recessed access device and methods of forming
A recessed access device having a gate electrode formed of two or more gate materials having different work functions may reduce the gate-induced drain leakage...
US-9,543,274 Semiconductor device packages with improved thermal management and related methods
Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. The stack...
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