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Patent # Description
US-9,954,075 Thyristor random access memory device and method
Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased...
US-9,953,842 Methods of forming a portion of a memory array having a conductor having a variable concentration of germanium
An embodiment of a method of forming a portion of a memory array includes forming a conductor with a concentration of germanium that decreases with an...
US-9,953,724 Memory devices and methods for managing error regions
Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for...
US-9,953,718 Programming memory cells to be programmed to different levels to an intermediate level from a lowest level
First memory cells are programmed to an intermediate level from a lowest level, corresponding to a lowest data state, where the first memory cells are to be...
US-9,953,711 Methods of operating memory under erase conditions
Methods of operating a memory include applying a first voltage level to a first semiconductor material of a first conductivity type forming a channel region for...
US-9,953,710 Memory devices with a connecting region having a band gap lower than a band gap of a body region
Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region....
US-9,952,925 Error code calculation on sensing circuitry
Examples of the present disclosure provide apparatuses and methods for error code calculation. The apparatus can include an array of memory cells that are...
US-9,952,077 Self-aligning brace bar
A brace bar, a flow conduit assembly including a brace bar, and a method for assembling a vibrating flowmeter including a brace bar are provided. The brace bar...
US-9,950,464 Forming a carbon nano-tube dispersion
Various embodiments disclose a molding compound comprising a resin, a filler, and a carbon nano-tube dispersion and methods of forming a package using the...
US-9,948,300 Apparatuses and methods for partial bit de-emphasis
Apparatuses and methods for partial bit de-emphasis are provided. An example apparatus includes an output driver and control circuit. The output driver includes...
US-9,947,721 Thermal insulation for three-dimensional memory arrays
Methods, systems, and devices for a three-dimensional memory array are described. Memory cells may transform when exposed to elevated temperatures, including...
US-9,947,720 Three-dimensional memory apparatuses and methods of use
A three dimensional (3D) memory array may include a plurality of memory cells. An example 3D memory array may include an electrode plane and a memory material...
US-9,947,719 Memory including a selector switch on a variable resistance memory cell
Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a...
US-9,947,687 Memory cells comprising a programmable field effect transistor having a reversibly programmable gate insulator
A memory cell comprises an elevationally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two...
US-9,947,666 Semiconductor device structures including buried digit lines and related methods
Methods of forming semiconductor device structures include forming trenches in an array region and in a buried digit line end region, forming a metal material...
US-9,947,418 Boosted channel programming of memory
Methods of operating a memory include generating a programming pulse for a programming operation having a plurality of steps prior to a program voltage level of...
US-9,947,376 Vertical bit vector shift in memory
Examples of the present disclosure provide apparatuses and methods for vertical bit vector shift in a memory. An example method comprises storing a vertical bit...
US-9,947,375 Methods and apparatuses for providing a program voltage responsive to a voltage determination
Apparatuses and methods for providing a program voltage responsive to a voltage determination are described. An example apparatus includes a memory array...
US-9,946,612 Data encoding using spare channels
Implementations of encoding techniques are disclosed. In one embodiment, an encoding system includes a codec device, a switching network, a rerouting circuit, a...
US-9,942,074 Wireless devices and systems including examples of mixing coefficient data specific to a processing mode selection
Examples described herein include systems and methods which include wireless devices and systems with examples of mixing input data with coefficient data...
US-9,941,870 Adjustable delay circuit for optimizing timing margin
The present invention relates to timing margin adjustment circuits using adjustable delay circuits. An example adjustable delay circuit may include a signal...
US-9,941,466 Magnetic tunnel junctions, methods used while forming magnetic tunnel junctions, and methods of forming...
A method used while forming a magnetic tunnel junction comprises forming non-magnetic tunnel insulator material over magnetic electrode material. The tunnel...
US-9,941,298 Methods of forming integrated structures comprising vertical channel material and having conductively-doped...
Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower...
US-9,941,238 Wiring with external terminal
Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a connection wiring of a ring-shape having...
US-9,941,155 Methods for isolating portions of a loop of pitch-multiplied material and related structures
Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is...
US-9,941,053 Structure and methods of forming the structure
Capacitors, apparatus including a capacitor, and methods for forming a capacitor are provided. One such capacitor may include a first conductor a second...
US-9,941,022 Setting a default read signal based on error correction
A number of methods can include reading a page of data from a group of memory cells with a first discrete read signal and error correcting at least one codeword...
US-9,941,021 Plate defect mitigation techniques
Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways...
US-9,940,990 Data shift apparatuses and methods
The present disclosure includes data shift apparatuses and methods. An example apparatus includes a memory device. The example memory device includes an array...
US-9,940,989 STT-MRAM cell structures
A magnetic cell structure including a nonmagnetic bridge, and methods of fabricating the structure are provided. The magnetic cell structure includes a free...
US-9,940,985 Comparison operations in memory
The present disclosure includes apparatuses and methods related to performing comparison operations in memory. An example apparatus can include a first group of...
US-9,940,981 Division operations in memory
Examples of the present disclosure provide apparatuses and methods related to performing division operations in memory. An example apparatus might include a...
US-9,940,193 Chunk definition for partial-page read
The present disclosure is related to chunk definition for partial-page read. A number of methods can include setting a chunk size for a partial-page read of a...
US-9,940,052 Memory device configuration commands
Apparatuses and methods for configuring a memory device using configuration commands are provided. A method can include executing a first command while the...
US-9,940,026 Multidimensional contiguous memory allocation
The present disclosure is related to multidimensional contiguous memory allocation. Multidimensional contiguous memory allocation can include receiving an...
US-9,938,571 Compositions and methods for dehydrated storage of on-board reagents in microfluidic devices
Manufacturing methods and compositions are described for production of self-contained microfluidic cartridge devices with on-board reagents for molecular...
US-9,935,632 Methods and systems for averaging impedance calibration
A semiconductor device includes a power management integrated circuit that supplies a periodic supply voltage signal. The semiconductor device also includes...
US-9,935,264 Memory cells and methods of fabrication
Memory cells are disclosed, which cells include a cell material and an ion-source material over the cell material. A discontinuous interfacial material is...
US-9,935,237 Solid state lighting devices with dielectric insulation and methods of manufacturing
Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a first...
US-9,935,171 Vertical memory cell string with dielectric in a portion of the body
Some embodiments include a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to the...
US-9,935,154 Resistive memory cell structures and methods
Resistive memory cell structures and methods are described herein. One or more memory cell structures comprise a first resistive memory cell comprising a first...
US-9,935,120 Methods of fabricating integrated structures
Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and...
US-9,935,114 Methods of forming an array comprising pairs of vertically opposed capacitors and arrays comprising pairs of...
A method of forming an array comprising pairs of vertically opposed capacitors comprises forming a conductive lining in individual capacitor openings in support...
US-9,935,085 Semiconductor substrates with unitary vias and via terminals, and associated systems and methods
Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative system in accordance with a...
US-9,935,082 Stacked semiconductor dies with selective capillary under fill
Stacked semiconductor dies are provided with selective capillary under fill to avoid wafer warpage during curing. In one embodiment, a method of manufacturing a...
US-9,934,870 Apparatuses and methods for memory testing and repair
Some embodiments include apparatuses and methods having a first interface to communicate with a processing unit, a second interface to communicate with a memory...
US-9,934,869 Apparatuses and methods for flexible fuse transmission
Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each...
US-9,934,856 Apparatuses and methods for comparing data patterns in memory
Apparatuses and methods related to comparing data patterns in memory. An example method can include comparing a number of data patterns stored in a memory array...
US-9,934,850 Accessing memory cells in parallel in a cross-point array
Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first...
US-9,934,839 Dynamic adjustment of memory cell digit line capacitance
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be used to store a logic state....
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