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Patent # Description
US-1,004,9054 Virtual register file
The present disclosure is related to a virtual register file. Source code can be compiled to include references to a virtual register file for data subject to a...
US-1,004,9038 Memory devices with register banks storing actuators that cause operations to be performed on a memory core
A bus controller has a displacer, an arithmetic logic unit coupled to the displacer, and a replacer selectively coupled to the displacer and the arithmetic...
US-1,004,8888 Apparatuses and methods for partitioned parallel data movement
The present disclosure includes apparatuses and methods for partitioned parallel data movement. An example apparatus includes a memory device that includes a...
US-1,004,8887 Apparatuses and methods for single level cell caching
Methods and apparatuses for single level cell caching are described. According to one example, a method includes receiving, at a memory device, a first set of...
US-1,004,8882 Non-volatile memory with LPDRAM
Low power DRAM (LPDRAM) memory devices for communication with a non-volatile memory coupled to the LPDRAM memory device, and systems containing such LPDRAM and...
US-1,004,5452 Electronic device structures and methods of making
Electronic device structures may include a sleeve member including a cavity extending from a first end of a body toward a second, opposite end, and an opening...
US-1,004,3769 Semiconductor devices including dummy chips
A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first...
US-1,004,3688 Method for mount tape die release system for thin die ejection
An apparatus, system, and a method of using the apparatus or system that includes a bladder positioned between tape and an adhesive layer configured to...
US-1,004,3587 Apparatuses and methods including nested mode registers
Apparatuses and methods for nested mode registers to extend mode register functionality are disclosed. An example apparatus comprises a mode register configured...
US-1,004,3574 Programming memories with multi-level pass signal
Methods of operating a memory include applying a first voltage level to control gates of a plurality of memory cells selected to be programmed while applying a...
US-1,004,3570 Signed element compare in memory
Examples of the present disclosure provide apparatuses and methods for performing signed element compare operations. An apparatus can include a first group of...
US-1,004,3566 Array data bit inversion
Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge...
US-1,004,3557 Apparatuses and methods for parallel I/O operations in a memory
Apparatuses and methods for a multi-level communication architectures are disclosed herein. An example apparatus may include an input/output (I/O) circuit...
US-1,004,3556 Data shifting
The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense...
US-1,004,3041 Multi-function, modular system for network security, secure communication, and malware protection
Representative embodiments are disclosed for providing network and system security. A representative apparatus includes an input-output connector coupleable to...
US-1,004,2789 Programming interruption management
The present disclosure is related to programming interruption management. An apparatus can be configured to detect an interruption during a programming...
US-1,004,2755 3D vertical NAND memory device including multiple select lines and control lines having different vertical spacing
Some embodiments include apparatuses, and methods of forming and operating the apparatuses. Some of the apparatuses include a pillar including a length, a...
US-1,004,2750 Apparatuses and methods for adaptive control of memory using an adaptive memory controller with a memory...
Apparatuses and methods for adaptive control of memory are disclosed. One example apparatus includes a processing unit configured to run an operating system,...
US-1,004,2608 Signed division in memory
Examples of the present disclosure provide apparatuses and methods for performing signed division operations. An apparatus can include a first group of memory...
US-1,003,8861 Method, apparatus, and system providing an imager with pixels having extended dynamic range
The dynamic range of a pixel is increased by using selective photosensor resets during a frame time of image capture at a timing depending on the light...
US-1,003,8523 Apparatuses and methods to change information values
Some embodiments include apparatuses and methods having a component to change a value of a bit among a number of M bits of information when the M bits have the...
US-1,003,8008 Integrated structures and NAND memory arrays
Some embodiments include an integrated structure having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include...
US-1,003,8002 Semiconductor devices and methods of fabrication
Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a...
US-1,003,7983 Semiconductor device with modified current distribution
Semiconductor devices having modified current distribution and methods of forming the same are described herein. As an example, a memory die in contact with a...
US-1,003,7926 Apparatus and methods for through substrate via test
A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side...
US-1,003,7818 Switched interface stacked-die memory architecture
Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request...
US-1,003,7809 Memory devices for reading memory cells of different memory planes
Memory devices may include digital-to-analog converters configured to convert digital values to analog read voltages and to apply the analog read voltages to...
US-1,003,7807 Boosting channels of memory cells
A method for programming a non-volatile memory device includes concurrently boosting channels of memory cells in a selected memory string and an unselected...
US-1,003,7806 Memory cell programming using VgVt value
Methods of operating a memory include applying a programming pulse having a particular voltage level to a selected access line connected to selected memory...
US-1,003,7797 Programming memories with stepped programming pulses including inhibiting a memory cell for a portion of a...
Methods of operating a memory device include applying a programming pulse to a plurality of memory cells selected for programming having an initial portion...
US-1,003,7791 Apparatuses and methods for setting a signal in variable resistance memory
An example of a method reads a spin torque transfer (STT) memory cell, and writes the STT memory cell using information obtained during the reading of the STT...
US-1,003,7786 Apparatuses and methods for converting a mask to an index
The present disclosure includes apparatuses and methods related to converting a mask to an index. An example apparatus comprises an array of memory cells and...
US-1,003,7785 Scan chain operation in sensing circuitry
Examples include apparatuses and methods related to scan chain operation in sensing circuitry. A number of embodiments include an apparatus comprising an array...
US-1,003,7153 Memory device, electronic system, and methods associated with modifying data and a file of a memory device
A memory device, system and method of editing a file in a non-volatile memory device is described. The memory device includes a controller and a memory array...
US-1,003,7045 Systems and apparatuses for a configurable temperature dependent reference voltage generator
Systems and apparatuses for a configurable, temperature dependent reference voltage generator are provided. An example apparatus includes control logic...
US-1,003,6780 Evaluation apparatus and evaluation method of sheet type cell
An electrode probe is brought into contact with a measurement part on an outer surface of at least one of the positive electrode and the negative electrode of a...
US-1,003,3268 Apparatuses and methods for charge pump regulation
Certain embodiments of the present invention include an apparatus comprising a charge pump, configured to provide an output voltage at an output node of the...
US-1,003,2903 Threshold voltage adjustment of a transistor
A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor...
US-1,003,2719 Semiconductor device structures
A method of forming a semiconductor structure comprises forming pools of acidic or basic material in a substrate structure. A resist is formed over the pools of...
US-1,003,2703 Package-on-package semiconductor assemblies and methods of manufacturing the same
Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device...
US-1,003,2501 Semiconductor device
A semiconductor device according to an aspect of the present invention has: a plurality of memory cells MC; a plurality of word lines WL each coupled to a...
US-1,003,2496 Variable filter capacitance
Methods, systems, and devices for variable filter capacitance are described. Within a memory device, voltages may be applied to access lines associated with two...
US-1,003,2493 Longest element length determination in memory
Examples of the present disclosure provide apparatuses and methods for determining a length of a longest element in a memory. An example method comprises...
US-1,003,2491 Apparatuses and methods for storing a data value in multiple columns
An example apparatus comprises an array of memory cells coupled to sensing circuitry. The apparatus can include a control component configured to cause...
US-1,003,1879 Memory device for a hierarchical memory architecture
In various embodiments, a hierarchical memory device having multiple interfaces with different memory formats includes a Phase Change Memory (PCM). An input...
US-1,002,7741 Adaptive communication interface
Embodiments of the invention include a communication interface and protocol for allowing communication between devices, circuits, integrated circuits, and other...
US-1,002,7523 Wireless devices and systems including examples of mixing input data with coefficient data
Examples described herein include systems and methods which include wireless devices and systems with examples of mixing input data with coefficient data. For...
US-1,002,7381 Method and apparatus for inductive coupling signal transmission
Method and Apparatuses for of transmitting data between semiconductor chips are described. An example apparatus includes a first semiconductor chip and a second...
US-1,002,6889 Semiconductor structures and devices and methods of forming semiconductor structures and magnetic memory cells
A magnetic cell includes a magnetic region formed from a precursor magnetic material comprising a diffusive species and at least one other species. An amorphous...
US-1,002,6836 Recessed transistors containing ferroelectric material
Some embodiments include transistor constructions having a first insulative structure lining a recess within a base. A first conductive structure lines an...
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