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Patent # Description
US-9,786,349 Cell performance recovery using cycling techniques
Methods, systems, and devices for memory array operation are described. A series of pulses may be applied to a fatigued memory cell to improve performance of...
US-9,786,348 Dynamic adjustment of memory cell digit line capacitance
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be used to store a logic state....
US-9,786,347 Cell-specific reference generation and sensing
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A portion of charge of a memory cell may be captured and, for...
US-9,786,346 Virtual ground sensing circuitry and related devices, systems, and methods for crosspoint ferroelectric memory
Virtual ground sensing circuits, electrical systems, computing devices, and related methods are disclosed. A virtual ground sensing circuit includes a sense...
US-9,786,345 Compensation for threshold voltage variation of memory cell components
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Before reading a memory cell, the voltage on an access line of...
US-9,786,335 Apparatuses and methods for performing logical operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an...
US-9,786,334 Interconnections for 3D memory
Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs...
US-9,786,332 Semiconductor device package with mirror mode
Semiconductor device assemblies with semiconductor device packages configured to operate in mirror mode are disclosed herein. In one embodiment a semiconductor...
US-9,785,847 Analyzing data using a hierarchical structure
Apparatus, systems, and methods for analyzing data are described. The data can be analyzed using a hierarchical structure. One such hierarchical structure can...
US-9,785,603 Devices, systems, and methods of reducing chip select
Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a...
US-9,785,588 Methods and systems for devices with self-selecting bus decoder
Disclosed are methods and devices, among which is a device including a self-selecting bus decoder. In some embodiments, the device may be coupled to a...
US-9,785,171 Apparatuses and related methods for staggering power-up of a stack of semiconductor dies
An apparatus including semiconductor dies in a stack. The semiconductor dies are configured to power-up in a staggered manner. Methods for powering up an...
US-9,784,788 Fault isolation system and method for detecting faults in a circuit
The present invention provides a method and a fault isolation system for detecting errors in an integrated circuit. One feature of the present invention is...
US-9,781,365 Method, apparatus and system providing adjustment of pixel defect map
A method, apparatus and system that allows for the identification of defective pixels, for example, defective pixel clusters, in an imager device. The method,...
US-9,780,786 Apparatus and method for standby current control of signal path
Apparatuses and methods for standby current control of a signal path in a semiconductor device are described. An example apparatus includes: first and second...
US-9,780,654 Analog assisted digital switch regulator
A device includes a digital switch regulator to supply an output voltage and a first current to a load based on a reference voltage. The device also includes an...
US-9,780,184 Electronic device with asymmetric gate strain
The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced...
US-9,780,115 Three dimensional memory and methods of forming the same
Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the...
US-9,780,110 Memory having memory cell string and coupling components
Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the...
US-9,780,107 Methods of forming integrated circuit devices
Methods of forming integrated circuit devices containing memory cells over a first region of a semiconductor substrate and gate structures over a second region...
US-9,780,103 Methods of forming integrated structures
Some embodiments include an integrated structure having semiconductor material within a region between two parallel surfaces. The semiconductor material has...
US-9,780,102 Memory cell pillar including source junction plug
Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the...
US-9,780,079 Semiconductor die assembly and methods of forming thermal paths
Semiconductor die assemblies and methods of forming the same are described herein. As an example, a semiconductor die assembly may include a thermally...
US-9,780,052 Collars for under-bump metal structures and associated systems and methods
The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and...
US-9,780,029 Semiconductor constructions having conductive lines which merge with one another
Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the...
US-9,779,839 Methods for providing redundancy in a memory array comprising mapping portions of data associated with a...
Methods for providing redundancy in a memory include mapping a portion of first data associated with an address of the memory determined to indicate a defective...
US-9,779,829 Erasing memory segments in a memory block of memory cells using select gate control line voltages
A method includes applying erase voltages to data lines and source lines of a memory block of memory cells in a non-volatile NAND architecture memory device...
US-9,779,828 Inferring threshold voltage distributions associated with memory cells via interpolation
Apparatuses and methods for inferring threshold voltage distributions associated with memory cells via interpolation are described herein. An example includes...
US-9,779,826 Memory devices for reading memory cells of different memory planes
Memory devices may include digital-to-analog converters configured to convert digital values to analog read voltages and to apply the analog read voltages to...
US-9,779,822 Memory devices and methods of their operation during a programming operation
Methods of operating a memory device during a programming operation, and memory devices so configured, including increasing a voltage applied to a selected...
US-9,779,821 Fast programming memory device
In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one...
US-9,779,819 Connecting memory cells to a data line sequentially while applying a program voltage to the memory cells
In an example, a programming method includes applying a program voltage to a selected access line commonly connected to a first memory cell of a first string of...
US-9,779,817 Boosting channels of memory cells to reduce program disturb
A method for programming a non-volatile memory device includes concurrently boosting channels of memory cells in a selected memory string and an unselected...
US-9,779,816 Apparatus and methods including source gates
Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor...
US-9,779,806 Resistive memory sensing methods and devices
Resistive memory sensing methods and devices are described. One such method includes performing a voltage based multiple pass sensing operation on a group of...
US-9,779,805 Phase change memory device
A phase change memory device with memory cells (2) formed by a phase change memory element (3) and a selection switch (4). A reference cell (2a) formed by an...
US-9,779,800 Timing control circuit shared by a plurality of banks
Apparatuses and methods for providing activation timings of sense amplifiers in a semiconductor device are described. An example apparatus includes: a first...
US-9,779,796 Redundancy array column decoder for memory
Methods, systems, and apparatuses for redundancy in a memory array are described. A memory array may include some memory cells that are redundant to other...
US-9,779,791 Apparatuses and methods involving accessing distributed sub-blocks of memory cells
Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in...
US-9,779,789 Comparison operations in memory
The present disclosure includes apparatuses and methods related to performing comparison operations in memory. An example apparatus can include a first group of...
US-9,779,784 Apparatuses and methods for performing logical operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an...
US-9,779,138 Methods and systems for autonomous memory searching
Methods and systems operate to receive a plurality of search requests for searching a database in a memory system. The search requests can be stored in a FIFO...
US-9,779,057 Autonomous memory architecture
An autonomous memory device in a distributed memory sub-system can receive a database downloaded from a host controller. The autonomous memory device can pass...
US-9,779,039 Impedance adjustment in a memory device
Methods and apparatus for impedance adjustment operations in memory devices are disclosed. One such method includes adjusting an impedance of a particular...
US-9,779,025 Cache architecture for comparing data
The present disclosure includes apparatuses and methods for a cache architecture. An example apparatus that includes a cache architecture according to the...
US-9,779,019 Data storage layout
Examples of the present disclosure provide apparatuses and methods for determining a data storage layout. An example apparatus comprising a first address space...
US-9,778,903 Apparatuses and methods for timing domain crossing
Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain,...
US-9,778,875 Multi-partitioning of memories
Various embodiments comprise devices to manage multiple memory types and reconfigure partitions in a memory device as directed by a host. In one embodiment, the...
US-9,778,874 Data deduplication
The present disclosure includes devices and methods for data deduplication. One such method includes receiving a write command, transforming data associated...
US-9,778,846 Sequential memory access operations
Methods of operating a memory include performing a memory access operation, obtaining an address corresponding to a subsequent memory access operation prior to...
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