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Patent # Description
US-1,015,7661 Mitigating line-to-line capacitive coupling in a memory die
Methods, systems, and devices for mitigating line-to-line capacitive coupling in a memory die are described. A device may include multiple drivers configured to...
US-1,015,7650 Program operations in memory
The present disclosure includes apparatuses and methods related to program operations in memory. An example apparatus can perform a program operation on an...
US-1,015,7648 Data output for high frequency domain
A system includes memory banks that store data and a data path coupled to the memory banks that transfers the data. The system also includes a latch that gates...
US-1,015,7647 Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters
Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating...
US-1,015,7644 Methods and apparatus for generation of voltages
Methods of operating a voltage generation circuit, and apparatus configured to perform such methods, include applying a clock signal to an input of a voltage...
US-1,015,7643 Active boundary quilt architecture memory
Methods, systems, and apparatus that increase available memory or storage using active boundary areas in quilt architecture are described. A memory array may...
US-1,015,7208 Methods and apparatuses for reducing power consumption in a pattern recognition processor
Apparatuses and methods are provided for reducing power consumption in a pattern-recognition processor. A power control circuit may be coupled to a block of...
US-1,015,7165 Methods and devices for reducing array size and complexity in automata processors
A method includes calculating a first position encoded pattern based on a first data pattern, and using an automata processor to compare the first position...
US-1,015,7126 Swap operations in memory
Examples of the present disclosure provide apparatuses and methods related to performing swap operations in a memory. An example apparatus might include a first...
US-1,015,7019 Apparatuses and methods for data transfer from sensing circuitry to a controller
The present disclosure describes data transfer in a memory device from sensing circuitry to controller. An example apparatus includes a controller coupled to a...
US-1,015,6990 Data storage management
A method of managing a plurality of storage devices. The method comprises at a first device connected to the plurality of storage devices via a switch,...
US-1,015,6893 Wiring with external terminal
Apparatuses in data input/output circuits of a semiconductor device are described. An example apparatus includes an output driver and a pre-output driver. The...
US-1,015,3922 Analog multiplexing scheme for decision feedback equalizers
A device includes a voltage generator that generates a reference signal, a multi-level bias generator coupled to the voltage generator to receive the reference...
US-1,015,3775 Phase interpolator
Apparatuses and methods for phase interpolators are provided. An example apparatus comprises a phase interpolator and a controller coupled to the phase...
US-1,015,3433 Methods of forming memory cells
Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed...
US-1,015,3431 Resistive memory having confined filament formation
Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon...
US-1,015,3428 Structures incorporating and methods of forming metal lines including carbon
Disclosed technology relates generally to integrated circuits, and more particularly, to structures incorporating and methods of forming metal lines including...
US-1,015,3381 Memory cells having an access gate and a control gate and dielectric stacks above and below the access gate
In an example, a memory cell may have an access gate, a control gate coupled to the access gate, a first dielectric stack below an upper surface of a...
US-1,015,3348 Memory configurations
In an example, a memory may have a group of series-coupled memory cells, where a memory cell of the series-coupled memory cells has an access gate, a control...
US-1,015,3299 Vertical ferroelectric field effect transistor constructions, constructions comprising a pair of vertical...
A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating...
US-1,015,3298 Integrated structures and methods of forming vertically-stacked memory cells
Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within...
US-1,015,3281 Memory cells and memory arrays
Some embodiments include a memory cell having first and second transistors and first and second capacitors. The first capacitor is vertically displaced relative...
US-1,015,3254 Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing...
A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second ...
US-1,015,3251 Apparatuses and methods for scalable memory
Apparatuses and methods are provided for scalable memory. An example apparatus comprises a logic component, a plurality of memory components adjacent to and...
US-1,015,3221 Face down dual sided chip scale memory package
A semiconductor die that includes a first die located on a first side of an interposer and a second die located on a second side of the interposer. Active sides...
US-1,015,3200 Methods of forming a nanostructured polymer material including block copolymer materials
Methods for fabricating sub-lithographic, nanoscale microstructures utilizing self-assembling block copolymers, and films and devices formed from these methods...
US-1,015,3197 Methods of forming one or more covered voids in a semiconductor substrate
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
US-1,015,3196 Arrays of cross-point memory structures
Some embodiments include a memory array having a first set of lines extending along a first direction, and a second set of lines over the first set of lines and...
US-1,015,3195 Semiconductor constructions comprising dielectric material
Some embodiments include a semiconductor construction which has one or more openings extending into a substrate. The openings are at least partially filled with...
US-1,015,3194 Array of gated devices and methods of forming an array of gated devices
An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid...
US-1,015,3190 Devices, systems and methods for electrostatic force enhanced semiconductor bonding
Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for enhancing wafer bonding...
US-1,015,3178 Semiconductor die assemblies with heat sink and associated systems and methods
Semiconductor die assemblies with heat sinks are disclosed herein. In one embodiment, a semiconductor die assembly includes a stack of semiconductor dies and a...
US-1,015,3054 Ferroelectric memory cell recovery
Methods, systems, and devices for recovering fatigued ferroelectric memory cells are described. Recovery voltages may be applied to a ferroelectric memory cell...
US-1,015,3049 Erasing memory segments in a memory block of memory cells using select gate control line voltages
A method includes applying erase voltages to data lines and source lines of a memory block of memory cells in a non-volatile NAND architecture memory device...
US-1,015,3047 Nonconsecutive sensing of multilevel memory cells
Apparatuses and methods for nonconsecutive sensing of multilevel memory cells include methods of sensing a unit of information from a multilevel memory cell...
US-1,015,3043 Methods of programming and sensing in a memory device
Methods of programming and sensing in a memory device including connecting first and second data lines in series before programming or sensing, respectively.
US-1,015,3040 Apparatuses and methods for current limitation in threshold switching memories
Apparatuses and methods for limiting current in threshold switching memories are disclosed. An example apparatus may include a plurality of first decoder...
US-1,015,3039 Memory cells programmed via multi-mechanism charge transports
The present disclosure includes memory cells programmed via multi-mechanism charge transports. An example apparatus includes a semiconductor material, a...
US-1,015,3031 Apparatuses and methods for controlling refresh operations
An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit...
US-1,015,3030 Apparatuses and methods for configurable command and data input circuits for semiconductor memories
Apparatuses and methods for configurable command and data input circuits for semiconductor memories are described. Example apparatuses include input signal...
US-1,015,3027 Memory arrays, and methods of forming memory arrays
Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has...
US-1,015,3026 Writing to cross-point non-volatile memory
Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a...
US-1,015,3024 Dynamic adjustment of memory cell digit line capacitance
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be used to store a logic state....
US-1,015,3023 Cell-based reference voltage generation
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be initialized to a first...
US-1,015,3022 Time-based access of a memory cell
Techniques, systems, and devices for time-resolved access of memory cells in a memory array are described herein. During a sense portion of a read operation, a...
US-1,015,3021 Time-based access of a memory cell
Methods, systems, and devices for time-based access of memory cells in a memory array are described herein. During a sense portion of a read operation, a...
US-1,015,3020 Dual mode ferroelectric memory cell operation
Methods, systems, and devices for dual mode ferroelectric memory cell operation are described. A memory array or portions of the array may be variously operated...
US-1,015,3019 Compensation for threshold voltage variation of memory cell components
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Before reading a memory cell, the voltage on an access line of...
US-1,015,3018 Ferroelectric memory cells
Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors....
US-1,015,3016 Apparatus of offset voltage adjustment in input buffer
Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes an input pad, an input buffer including a...
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