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Patent # Description
US-7,978,411 Tetraform microlenses and method of forming the same
A lens is formed to support and tilt at least one microlens formed on the lens. The degree and direction of slope of the microlens can be controlled based on...
US-7,978,000 Semiconductor temperature sensor using bandgap generator circuit
A combined bandgap generator and temperature sensor for an integrated circuit is disclosed. Embodiments of the invention recognize that bandgap generators...
US-7,977,997 Generating a full rail signal
Apparatus, systems, and methods are disclosed, such as those that comprise a center-swing signal generator that includes a push-pull center-swing driver coupled...
US-7,977,962 Apparatus and methods for through substrate via test
A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side...
US-7,977,765 Antifuse circuit with well bias transistor
An antifuse circuit includes a terminal, an antifuse transistor, and a bias transistor. The antifuse transistor is formed on a substrate. The antifuse...
US-7,977,727 Semiconductor constructions
Some embodiments include methods of reflecting ions off of vertical regions of photoresist mask sidewalls such that the ions impact foot regions along the...
US-7,977,597 Wire bonders and methods of wire-bonding
Wire bonders and methods of wire-bonding are disclosed herein. In one embodiment, a method includes attaching a wire to a terminal of a microelectronic...
US-7,977,236 Method of forming a transistor gate of a recessed access device, method of forming a recessed transistor gate...
Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the...
US-7,977,190 Memory devices having reduced interference between floating gates and methods of fabricating such devices
A floating gate memory array comprising transistors having isolated inter-gate dielectric regions with respect to one another and methods of fabricating the...
US-7,977,157 Methods of forming integrated circuit packages, and methods of assembling integrated circuit packages
Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region...
US-7,977,037 Photoresist processing methods
A photoresist processing method includes treating a substrate with a sulfur-containing substance. A positive-tone photoresist is applied on and in contact with...
US-7,977,017 Method to recover the exposure sensitivity of chemically amplified resins from post coat delay effect
Methods of fabricating a photomask, methods of treating a chemically amplified resist-coated photomask blank, a photomask blank resulting from the methods, and...
US-7,976,897 Thermal chemical vapor deposition methods, and thermal chemical vapor deposition systems
One embodiment thermal chemical vapor deposition method includes exposing a substrate within a chamber to first and second deposition precursors effective to...
US-7,975,083 Alignment of instructions and replies across multiple devices in a cascaded system, using buffers of...
Buffers of programmable depths are used in the instruction and reply paths of cascaded devices to account for possible differences in latencies between the...
US-7,974,146 Wordline temperature compensation
A nonvolatile memory includes a temperature dependent read window. One or more temperature compensated wordline voltage supply circuits provide temperature...
US-7,974,129 Method and apparatus for programming flash memory
A method and apparatus that provides the ability to control programming pulses having different widths and/or voltages in a flash memory device. The widths...
US-7,973,577 Control of a variable delay line using line entry point to modify line power supply voltage
Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input...
US-7,973,411 Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and...
Microfeature workpieces having conductive vias formed by chemically reactive processes, and associated systems and methods are disclosed. A method in accordance...
US-7,973,388 Semiconductor structures including square cuts in single crystal silicon
A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a...
US-7,973,370 Fully depleted silicon-on-insulator CMOS logic
A extractor implanted region is used in a silicon-on-insulator CMOS memory device. The extractor region is reversed biased to remove minority carriers from the...
US-7,972,974 Gallium lanthanide oxide films
Electronic apparatus and methods of forming the electronic apparatus include a gallium lanthanide oxide film for use in a variety of electronic systems. The...
US-7,972,940 Wafer processing
Methods, devices, and systems for wafer processing are described herein. One method of wafer processing includes modifying a peripheral edge of a wafer to...
US-7,972,926 Methods of forming memory cells; and methods of forming vertical structures
Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end...
US-7,972,753 Masks for microlithography and methods of making and using such masks
Masks for microlithography apparatus, methods for making such masks, and methods for exposing photosensitive materials to form arrays of microfeatures on...
US-7,970,964 Methods and systems to accomplish variable width data input
Disclosed are methods and systems for variable width data input to a pattern-recognition processor. A variable width data input method may include receiving...
US-7,970,958 Peripheral interface alert message for downstream device
According to some embodiments, a message generated by a downstream device is received at upstream device. The message may, for example, be received via a...
US-7,969,815 System and method for controlling timing of output signals
The timing of output signals can be controlled by coupling a digital signal through a signal distribution tree having a plurality of branches extending from an...
US-7,969,813 Write command and write data timing circuit and methods for timing the same
Circuits, memories, and methods for latching a write command and later provided write data including write command and write data timing circuits. One such...
US-7,969,788 Charge loss compensation methods and apparatus
Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss...
US-7,969,783 Memory with correlated resistance
A system or device including a memory device, as well as a method of operating the memory device. Such a method includes writing a plurality of data values to a...
US-7,969,782 Determining memory page status
The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. One method embodiment includes determining a status...
US-7,969,779 Integrated circuit including memory array having a segmented bit line architecture and method of controlling...
An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of bit lines (e.g., first and second bit...
US-7,969,776 Data cells with drivers and methods of making and operating the same
Disclosed are methods and devices, among which is a device that includes a first semiconductor fin having a first gate, a second semiconductor fin adjacent the...
US-7,969,774 Electronic devices formed of two or more substrates bonded together, electronic systems comprising electronic...
Electronic devices comprise a first substrate and a second substrate. The first substrate comprises circuitry including a plurality of conductive traces at...
US-7,969,490 Method, apparatus, and system providing an imager with pixels having extended dynamic range
The dynamic range of a pixel is increased by using selective photosensor resets during a frame time of image capture at a timing depending on the light...
US-7,969,488 Correction of cluster defects in imagers
A method and apparatus that allows for the correction of multiple defective pixels in an imager device. In one exemplary embodiment, the method includes the...
US-7,969,252 System and method for reducing lock time in a phase-locked loop
Increasing loop gain is a common practice for reducing lock time of phase locked loops. Very high loop gains, however, often result in increasing the lock time...
US-7,968,969 Electrical components for microelectronic devices
Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing...
US-7,968,962 Semiconductor fabrication method and system
A semiconductor device is disclosed. In one embodiment, a device includes a substrate having one or more vias and a carrier coupled to the substrate to form a...
US-7,968,960 Methods of forming strained semiconductor channels
In various method embodiments, a device region in a semiconductor substrate and isolation regions adjacent to the device region are defined. The device region...
US-7,968,954 Intermediate semiconductor device having nitrogen concentration profile
A method for reducing the effective thickness of a gate oxide using nitrogen implantation and anneal subsequent to dopant implantation and activation is...
US-7,968,951 Interconnecting bit lines in memory devices for multiplexing
An embodiment of a memory device has a plurality of conductive plugs formed on a semiconductor substrate and a pair of successively adjacent first and second...
US-7,968,930 Finned memory cells
For an embodiment, a memory array has a plurality fins protruding from a substrate. A tunnel dielectric layer overlies the fins. A plurality floating gates...
US-7,968,928 DRAM layout with vertical FETs and method of formation
DRAM cell arrays having a cell area of less than about 4 F.sup.2 comprise an array of vertical transistors with buried bit lines and vertical double gate...
US-7,968,927 Memory array for increased bit density and method of forming the same
A memory array having a plurality of resistance variable memory units and method for forming the same are provided. Each memory unit includes a first electrode,...
US-7,968,916 Circuit and method for interconnecting stacked integrated circuit dies
Signals are routed to and from identical stacked integrated circuit dies by selectively coupling first and second bonding pads on each of the dies to respective...
US-7,968,862 Phase change memory elements using self-aligned phase change material layers
A phase change memory element and method of forming the same. The memory element includes a substrate supporting a first electrode. An insulating material...
US-7,968,460 Semiconductor with through-substrate interconnect
Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor...
US-7,968,425 Isolation regions
Methods and apparatus are provided. An isolation region is formed by lining a trench formed in a substrate with a first dielectric layer by forming the first...
US-7,968,411 Threshold voltage adjustment for long-channel transistors
A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor...
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