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Patent # Description
US-8,049,514 Integrated circuit inspection system
Methods and systems that include a nanotube used as an emitter in the testing and fabrication of integrated circuits. The nanotube emits a signal to a...
US-8,049,331 Structure and method for forming a capacitively coupled chip-to-chip signaling interface
A system and method for providing capacitively-coupled signaling in a system-in-package (SiP) device is disclosed. In one embodiment, the system includes a...
US-8,049,298 Isolation trenches for memory devices
A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric...
US-8,049,258 Disposable pillars for contact formation
Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various...
US-8,049,200 Bottom electrode for memory device and method of forming the same
Contacts having use in an integrated circuit and exemplary methods of forming the contacts are disclosed. The methods involve forming a conductive cap over a...
US-8,048,756 Method for removing metal layers formed outside an aperture of a BPSG layer utilizing multiple etching...
A microelectronic substrate and method for removing adjacent conductive and nonconductive materials from a microelectronic substrate. In one embodiment, the...
US-8,048,755 Resistive memory and methods of processing resistive memory
Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include...
US-8,048,708 Method and apparatus providing an imager module with a permanent carrier
Method and apparatus providing a wafer level fabrication of imager modules in which a permanent carrier protects imager devices on an imager wafer and is used...
US-8,046,646 Defective memory block identification in a memory device
During manufacture and testing of a memory device, a memory test is performed to determine which, if any, memory blocks are defective. A memory map of the...
US-8,046,628 Failure recovery memory devices and methods
Memory devices and methods are described that include serially chained memory devices. In one or more of the configurations shown, a serial chain of memory...
US-8,046,542 Fault-tolerant non-volatile integrated circuit memory
Apparatus and methods are disclosed, such as those that store data in a plurality of non-volatile integrated circuit memory devices, such as NAND flash, with...
US-8,045,416 Method and memory device providing reduced quantity of interconnections
Methods, devices and systems for reducing the quantity of external interconnections of a memory device are disclosed. Implementation of one such method, device...
US-8,045,395 Circuits, systems and methods for driving high and low voltages on bit lines in non-volatile memory
An integrated circuit bit line driver system includes a plurality of bit line drivers coupled to respective bit lines of an array of non-volatile memory cells....
US-8,045,386 Methods and apparatus for programming a memory cell using one or more blocking memory cells
Methods and apparatus for programming a memory cell using one or more blocking memory cells facilitate mitigation of capacitive voltage coupling. The methods...
US-8,045,356 Memory modules having daisy chain wiring configurations and filters
Examples described include memory units coupled to a controller using a daisy chain wiring configuration. A filter located between a first memory unit and the...
US-8,045,040 Correction of non-uniform sensitivity in an image array
An improved non-uniform sensitivity correction algorithm for use in an imager device (e.g., a CMOS APS). The algorithm provides zones having flexible boundaries...
US-8,044,479 Transistors, semiconductor devices, assemblies and constructions
Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another...
US-8,043,975 Silicon dioxide deposition methods using at least ozone and TEOS as deposition precursors
Embodiments disclosed herein pertain to silicon dioxide deposition methods using at least ozone and tetraethylorthosilicate (TEOS) as deposition precursors. In...
US-8,043,964 Method for providing electrical connections to spaced conductive lines
An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an...
US-8,043,961 Method of forming a bond pad
A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an...
US-8,043,944 Process for enhancing solubility and reaction rates in supercritical fluids
Processes for enhancing solubility and the reaction rates in supercritical fluids are provided. In preferred embodiments, such processes provide for the uniform...
US-8,043,915 Pitch multiplied mask patterns for isolated features
Crisscrossing spacers formed by pitch multiplication are used as a mask to form isolated features, such as contacts vias. A first plurality of mandrels are...
US-8,043,911 Methods of forming semiconductor constructions
The invention includes methods of forming semiconductor constructions in which a single etch is utilized to penetrate through a titanium-containing layer and...
US-8,042,022 Method, system, and apparatus for distributed decoding during prolonged refresh
Methods, apparatuses and systems are disclosed for preserving, verifying, and correcting data in DRAM device during a power-saving mode. In the power-saving...
US-8,042,012 Systems and devices including memory with built-in self test and methods of making and using the same
Disclosed are methods, systems and devices, such as a device including a data location, a quantizing circuit coupled to the data location, and a test module...
US-8,040,753 System and method for capturing data signals using a data strobe signal
A signal capture system and method is used to capture a data signal using a data strobe signal having a preamble of strobe signal transitions. The system...
US-8,040,732 NAND memory device column charging
Embodiments of NAND Flash memory devices and methods recognize that effective column coupling capacitance can be reduced by maintaining a sourced voltage on...
US-8,039,882 High gain, low noise photodiode for image sensors and method of formation
Embodiments of the present invention provide a pixel cell for an image sensor that includes a photodiode, which provides high gain, low noise, and low dark...
US-8,039,881 Deuterated structures for image sensors and methods for forming the same
A pixel cell with a photo-conversion device and at least one structure includes a deuterated material adjacent the photo-conversion device.
US-8,039,399 Methods of forming patterns utilizing lithography and spacers
Some embodiments include methods of forming patterns. A first set of features is photolithographically formed over a substrate, and then a second set of...
US-8,039,377 Semiconductor constructions
Some embodiments include methods of forming capacitors. A first section of a capacitor may be formed to include a first storage node, a first dielectric...
US-8,039,357 Integrated circuitry and methods of forming a semiconductor-on-insulator substrate
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
US-8,039,348 Vertical gated access transistor
According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches and a plurality of shallow...
US-8,039,340 Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors,...
A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall...
US-8,039,327 Transistor forming methods
A transistor forming method includes forming a dielectric spacer in a trench surrounding an active area island, forming line openings through the spacer, and...
US-8,039,300 Reproducible resistance variable insulating memory devices and methods for forming same
The present invention relates to the use of a shaped bottom electrode in a resistance variable memory device. The shaped bottom electrode ensures that the...
US-8,039,287 Method of forming high gain, low noise, photodiode sensor for image sensors
Embodiments of the present invention provide a pixel cell for an image sensor that includes a photodiode, which provides high gain, low noise, and low dark...
US-8,037,446 Methods for defining evaluation points for optical proximity correction and optical proximity correction...
Methods are disclosed for defining evaluation points for use in optical proximity correction of a rectangular target geometry. A method for defining evaluation...
US-8,037,381 Error detection, documentation, and correction in a flash memory device
A memory device has an error documentation memory array that is separate from the primary memory array. The error documentation memory array stores data...
US-8,037,378 Automatic test entry termination in a memory device
A memory device has a control register comprising a test mode disable bit. The test mode is initially enabled. If the device does not receive an appropriate key...
US-8,036,334 Delay lock loop phase glitch error filter
A method and apparatus is provided for providing a phase glitch error filter for a delay lock loop. The device comprises a delay lock loop to provide an output...
US-8,036,058 Symmetrically operating single-ended input buffer devices and methods
Embodiments are described including those pertaining to an input buffer having first and second complementary input terminals. One such input buffer has a...
US-8,036,035 Erase cycle counter usage in a memory device
Memory devices and methods are disclosed to facilitate adjustment of program voltages applied during a program operation based upon erase operation cycle...
US-8,036,019 Resistive memory
The present disclosure includes resistive memory devices and systems having resistive memory cells, as well as methods for operating the resistive memory cells....
US-8,036,016 Maintenance process to enhance memory endurance
Subject matter disclosed herein relates to enhancing an operational lifespan of non-volatile memory.
US-8,035,433 Process insensitive delay line
A delay line including a phase detector having two inputs and one output. The first input of the phase detector is connected to an input of the delay line. The...
US-8,035,189 Semiconductor constructions
The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can...
US-8,035,179 Packaged microelectronic imagers and methods of packaging microelectronic imagers
Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in...
US-8,035,160 Recessed access device for a memory
Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming...
US-8,035,142 Deuterated structures for image sensors and methods for forming the same
A pixel cell with a photo-conversion device and at least one structure includes a deuterated material adjacent the photo-conversion device.
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