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Packaged microelectronic devices and methods for manufacturing packaged
Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged...
Microelectronic devices and microelectronic support devices, and
associated assemblies and methods
Microelectronic devices, associated assemblies, and associated methods are disclosed herein. For example, certain aspects of the invention are directed toward a...
Systems and pads for planarizing microelectronic workpieces and associated
methods of use and manufacture
Planarizing systems and methods of planarizing microelectronic workpieces using mechanical and/or chemical-mechanical planarization are disclosed herein. In one...
Methods, devices, and systems for experiencing reduced unequal testing
One or more embodiments of the present invention reduce uneven degradation during testing by providing for a toggling signal to be applied to remaining input...
Non-volatile hard disk drive cache system and method
A non-volatile hard disk drive cache system is coupled between a processor and a hard disk drive. The cache system includes a control circuit, a non-volatile...
Method and apparatus for reducing oscillation in synchronous circuits
Control signal oscillation filtering circuits, delay-locked loops, clock synchronization methods and devices and systems incorporating control signal...
Precharge control circuits and methods for memory having buffered write
Memories, precharge control circuits, methods of controlling, and methods of utilizing are disclosed, including precharge control circuits for a memory having...
Row selector occupying a reduced device area for semiconductor memory
A memory device having a plurality of memory cells grouped in at least two memory sectors is disclosed. A first decoding circuit operable to receive address...
Systems and devices including memory resistant to program disturb and
methods of using, making, and operating...
Disclosed are methods, systems and devices, one such device being a memory device configured to concurrently assert a first pulse pattern through a plurality of...
Enhanced performance memory systems and methods
Digital memory devices and systems, including memory systems and methods for operating such memory systems are disclosed. In the embodiments, a memory system...
Method and apparatus to improve filter characteristics of optical filters
An optical filter structure for an imager which has customized sub-wavelength elements used to maintain the filter characteristics accordingly across a...
Method and apparatus providing pixel storage gate charge sensing for
electronic stabilization in imagers
An imaging device that stores charge from a photosensor under at least one storage gate. A driver used to operate the at least one storage gate, senses how much...
Input buffer with optimal biasing and method thereof
A method and circuit of a biased input buffer is described to maximize the quality in the output signals. The input buffer includes a first stage for receiving...
Flexible column die interconnects and structures including same
A flexible column interconnect for a microelectronic substrate includes a plurality of conductive columns extending from a bond pad or other conductive terminal...
Semiconductor package having discrete components and system containing the
A semiconductor package includes a substrate having contacts, and a discrete component on the substrate in electrical communication with the contacts. The...
Scalable high density non-volatile memory cells in a contactless memory
A plurality of mesas are formed in the substrate. Each pair of mesas forms a trench. A plurality of diffusion areas are formed in the substrate. A mesa...
Methods of patterning photoresist, and methods of forming semiconductor
The invention includes semiconductor constructions containing optically saturable absorption layers. An optically saturable absorption layer can be between...
Methods of forming capacitors
A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and...
Formation of carbon-containing material
A method includes forming ionic clusters of carbon-containing molecules, which molecules have carbon-carbon sp.sup.2 bonds, and accelerating the clusters. A...
Method of forming cellular material
Systems, devices and methods are provided that are related to cellular materials that have a precisely-determined arrangement of voids formed using surface...
Method of cleaning a surface of a cobalt-containing material, method of
forming an opening to a...
The invention includes methods of cleaning a surface of a cobalt-containing material, methods of forming an opening to a cobalt-containing material,...
Methods using block copolymer self-assembly for sub-lithographic
Block copolymers can be self-assembled and used in methods as described herein for sub-lithographic patterning, for example. The block copolymers can be diblock...
Repairable block redundancy scheme
A scheme for block substitution within a flash memory device is disclosed which uses a programmable look-up table to store new addresses for block selection...
Methods for determining resistance of phase change memory elements
Methods for measuring the resistance of multiple memory elements are disclosed. The memory elements may be multi-bit memory and through precise measurement of...
Power saving sensing scheme for solid state memory
Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a...
Method and system for minimizing number of programming pulses used to
program rows of non-volatile memory cells
A flash memory device programs cells in each row in a manner that minimizes the number of programming pulses that must be applied to the cells during...
Programming rate identification and control in a solid state memory
Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer...
Program and read trim setting
A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device...
Non-volatile memory with resistive access component
Some embodiments include apparatus and methods having a memory element configured to store information and an access component configured to allow conduction of...
Multiple memory cells with rectifying device
Memory devices and methods described are shown that provide improvements, including improved cell isolation for operations such as read and write. Further,...
Method for modifying data more than once in a multi-level cell memory
location within a memory array
A method and apparatus for programming one or more bits in an upper page twice depending on the value in a corresponding bit in a corresponding lower page in a...
Print system, print data supplying device, and method for supplying print
data to printer
A print system includes: a printer; and a print data supplying device. The print data supplying device includes: a print data supplying unit that supplies the...
Sub-resolution assist devices and methods
Photolithographic apparatus, systems, and methods that make use of sub-resolution assist devices are disclosed. In the various embodiments, an imaging mask...
Variable gain stage having same input capacitance regardless of the stage
A programmable gain amplifier (PGA) includes a sample-and-hold (S&H) stage which provides an input capacitance value for storing a charge. The PGA also includes...
Delay-lock loop and method adapting itself to operate over a wide
A delay-lock loop receives an input clock signal from the output of a programmable divider that receives a reference clock signal. The delay-lock loop includes...
Contactor for electrical test, electrical connecting apparatus using the
same, and method for manufacturing...
An electrical test contactor comprises a contactor main body including a plate-shaped attachment portion extending in the up-down direction, a plate-shaped arm...
Support structure for use in thinning semiconductor substrates and for
supporting thinned semiconductor substrates
A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the...
Programmable resistance memory devices and systems using the same and
methods of forming the same
A programmable resistance memory element and method of forming the same. The memory element includes a first electrode, a dielectric layer over the first...
Electronic device having a hafnium nitride and hafnium oxide film
The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium nitride (Hf.sub.3N.sub.4) and hafnium oxide (HfO.sub.2) and a method of...
Semiconductor devices including fine pitch arrays with staggered contacts
A semiconductor device structure includes staggered contacts to facilitate small pitches between active-device regions and conductive lines while minimizing one...
Porous organosilicate layers, and vapor deposition systems and methods for
The present invention provides porous organosilicate layers, and vapor deposition systems and methods for preparing such layers on substrates. The porous...
Methods of patterning a substrate
A method of patterning a substrate is disclosed. An ink material is chemisorbed to at least one region of a stamp and the chemisorbed ink material is...
Command line output redirection
In one embodiment the invention provides a method to provide command line utility output to an application without the need of temporary files. The method...
Defective memory block remapping method and system, and memory device and
processor-based system using same
A non-volatile memory device includes a block remapping system that offsets an input block address by the addresses of non-functional blocks to provide an...
Method and apparatus for generating temperature-compensated read and
verify operations in flash memories
Methods and an apparatuses for generating a word-line voltage are disclosed. A word-line voltage generator includes a first current source, an adjustable...
Adjustable voltage regulator for providing a regulated output voltage
Voltage regulators, memories, and methods for providing a regulated output voltage are disclosed. For example, one such voltage regulator includes a comparator...
Read circuitry for an integrated circuit having memory cells and/or a
memory cell array, and method of...
An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each...
Verifying an erase threshold in a memory device
In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory...
Method of programming memory cells of series strings of memory cells
Method of programming memory cells of series strings of memory cells include programming a target memory cell of a series string of memory cells after...
Memory cell having nonmagnetic filament contact and methods of operating
and fabricating the same
A magnetic cell structure including a nonmagnetic filament contact, and methods of fabricating the structure are provided. The magnetic cell structure includes...