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Patent # Description
US-7,989,022 Methods of processing substrates, electrostatic carriers for retaining substrates for processing, and...
A method of processing a substrate includes physically contacting an exposed conductive electrode of an electrostatic carrier with a conductor to...
US-7,988,529 Methods and tools for controlling the removal of material from microfeature workpieces
Methods and apparatus for controlling the removal of material from microfeature workpieces in abrasive removal processes. An embodiment of such a method...
US-7,986,578 Low voltage sense amplifier and sensing method
Systems and methods of sensing a data state coupled to a digit line and for coupling a digit line to a sense amplifier. In sensing the data state coupled to the...
US-7,986,576 Digit line equilibration using access devices at the edge of sub-arrays
A method of equilibrating digit lines, a memory array, device, system and wafer for digit lines configured in an open digit line architecture. The digit lines...
US-7,986,563 NAND flash memory programming
A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a...
US-7,986,555 Method for programming and erasing an NROM cell
A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain...
US-7,986,553 Programming of a solid state memory utilizing analog communication of bit patterns
Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer...
US-7,986,549 Apparatus and method for refreshing or toggling a phase-change memory cell
An apparatus and a method for refreshing or toggling a phase-change memory cell are described. The apparatus includes a voltage ramp element coupled to the...
US-7,986,363 High dynamic range imager with a rolling shutter
A high dynamic range imager operates pixels utilizing at least a short integration period and a long integration period. The pixel reading circuits of the...
US-7,985,995 Zr-substituted BaTiO.sub.3 films
The use of atomic layer deposition (ALD) to form a zirconium substituted layer of barium titanium oxide (BaTiO.sub.3), produces a reliable ferroelectric...
US-7,985,698 Methods of forming patterned photoresist layers over semiconductor substrates
This invention comprises methods of forming patterned photoresist layers over semiconductor substrates. In one implementation, a semiconductor substrate is...
US-7,985,692 Method to reduce charge buildup during high aspect ratio contact etch
A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide...
US-7,985,681 Method for selectively forming symmetrical or asymmetrical features using a symmetrical photomask during...
A method for patterning a material during fabrication of a semiconductor device provides for the selective formation of either asymmetrical features or...
US-7,985,679 Atomic layer deposition methods
An atomic layer deposition method includes providing a semiconductor substrate within a deposition chamber. A first metal halide-comprising precursor gas is...
US-7,985,617 Methods utilizing microwave radiation during formation of semiconductor constructions
Some embodiments include methods in which microwave radiation is used to activate dopant and/or increase crystallinity of semiconductor material during...
US-7,983,516 Zinc oxide diodes for optical interconnections
The present disclosure includes methods, devices, and systems for zinc oxide diodes for optical interconnections. One system includes a ZnO emitter confined...
US-7,983,108 Row mask addressing
Electronic apparatus, systems, and methods may operate structures to access a portion of a row of a memory array without accessing the entire row. Additional...
US-7,983,090 Memory voltage cycle adjustment
The present disclosure includes various method, device, system, and module embodiments for memory cycle voltage adjustment. One such method embodiment includes...
US-7,983,088 Programming in a memory device
Methods for programming a memory device, memory devices, and a memory systems are provided. According to at least one such method, a selected memory cell is...
US-7,983,085 Memory array with inverted data-line pairs
At least one data-line pair has a first data line aligned with a first column of memory cells and a second data line aligned with a second column of memory...
US-7,983,070 DRAM tunneling access transistor
In one embodiment, a first transistor is comprised of a first p+ source region doped in an n-well in the substrate and a first n+ drain region doped on one side...
US-7,982,494 Systems and methods for detecting terminal state and setting output driver impedance
Embodiments of the present invention include systems for calibrating an output circuit. A comparator is coupled to a calibration terminal and configured to...
US-7,982,255 Flash memory with recessed floating gate
A flash memory device wherein the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a...
US-7,981,736 Systems and devices including multi-gate transistors and methods of using, making, and operating the same
Disclosed are methods of forming transistors. In one embodiment, the transistors are formed by forming a plurality of elliptical bases in a substrate and...
US-7,981,303 Method of manufacturing monocrystalline silicon micromirrors
A novel silicon micromirror structure for improving image fidelity in laser pattern generators is presented. In some embodiments, the micromirror is formed from...
US-7,981,221 Rheological fluids for particle removal
Methods and apparatus for cleaning a substrate (e.g., wafer) in the fabrication of semiconductor devices utilizing electrorheological (ER) and...
US-7,979,757 Method and apparatus for testing high capacity/high bandwidth memory devices
A plurality of stacked memory device die and a logic circuit are connected to each other through a plurality of conductors. The stacked memory device die are...
US-7,978,721 Multi-serial interface stacked-die memory architecture
Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding...
US-7,978,556 On-chip temperature sensor
A temperature invariant reference voltage and a temperature variant physical quantity, such as a voltage or current, are generated. The temperature variant...
US-7,978,529 Rewritable single-bit-per-cell flash memory
Subject matter disclosed herein relates to multilevel flash memory, and more particularly to a method of changing a logic level of a single-bit-per-cell flash...
US-7,978,511 Data line management in a memory device
Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device...
US-7,978,500 Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance
The invention relates to a method and apparatus providing a memory cell array in which each resistance memory cell is connected in series to a capacitive...
US-7,978,491 Stacked memory cell structure and method of forming such a structure
This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell...
US-7,978,411 Tetraform microlenses and method of forming the same
A lens is formed to support and tilt at least one microlens formed on the lens. The degree and direction of slope of the microlens can be controlled based on...
US-7,978,000 Semiconductor temperature sensor using bandgap generator circuit
A combined bandgap generator and temperature sensor for an integrated circuit is disclosed. Embodiments of the invention recognize that bandgap generators...
US-7,977,997 Generating a full rail signal
Apparatus, systems, and methods are disclosed, such as those that comprise a center-swing signal generator that includes a push-pull center-swing driver coupled...
US-7,977,962 Apparatus and methods for through substrate via test
A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side...
US-7,977,765 Antifuse circuit with well bias transistor
An antifuse circuit includes a terminal, an antifuse transistor, and a bias transistor. The antifuse transistor is formed on a substrate. The antifuse...
US-7,977,727 Semiconductor constructions
Some embodiments include methods of reflecting ions off of vertical regions of photoresist mask sidewalls such that the ions impact foot regions along the...
US-7,977,597 Wire bonders and methods of wire-bonding
Wire bonders and methods of wire-bonding are disclosed herein. In one embodiment, a method includes attaching a wire to a terminal of a microelectronic...
US-7,977,236 Method of forming a transistor gate of a recessed access device, method of forming a recessed transistor gate...
Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the...
US-7,977,190 Memory devices having reduced interference between floating gates and methods of fabricating such devices
A floating gate memory array comprising transistors having isolated inter-gate dielectric regions with respect to one another and methods of fabricating the...
US-7,977,157 Methods of forming integrated circuit packages, and methods of assembling integrated circuit packages
Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region...
US-7,977,037 Photoresist processing methods
A photoresist processing method includes treating a substrate with a sulfur-containing substance. A positive-tone photoresist is applied on and in contact with...
US-7,977,017 Method to recover the exposure sensitivity of chemically amplified resins from post coat delay effect
Methods of fabricating a photomask, methods of treating a chemically amplified resist-coated photomask blank, a photomask blank resulting from the methods, and...
US-7,976,897 Thermal chemical vapor deposition methods, and thermal chemical vapor deposition systems
One embodiment thermal chemical vapor deposition method includes exposing a substrate within a chamber to first and second deposition precursors effective to...
US-7,975,083 Alignment of instructions and replies across multiple devices in a cascaded system, using buffers of...
Buffers of programmable depths are used in the instruction and reply paths of cascaded devices to account for possible differences in latencies between the...
US-7,974,146 Wordline temperature compensation
A nonvolatile memory includes a temperature dependent read window. One or more temperature compensated wordline voltage supply circuits provide temperature...
US-7,974,129 Method and apparatus for programming flash memory
A method and apparatus that provides the ability to control programming pulses having different widths and/or voltages in a flash memory device. The widths...
US-7,973,577 Control of a variable delay line using line entry point to modify line power supply voltage
Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input...
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