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Patent # Description
US-7,973,411 Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and...
Microfeature workpieces having conductive vias formed by chemically reactive processes, and associated systems and methods are disclosed. A method in accordance...
US-7,973,388 Semiconductor structures including square cuts in single crystal silicon
A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a...
US-7,973,370 Fully depleted silicon-on-insulator CMOS logic
A extractor implanted region is used in a silicon-on-insulator CMOS memory device. The extractor region is reversed biased to remove minority carriers from the...
US-7,972,974 Gallium lanthanide oxide films
Electronic apparatus and methods of forming the electronic apparatus include a gallium lanthanide oxide film for use in a variety of electronic systems. The...
US-7,972,940 Wafer processing
Methods, devices, and systems for wafer processing are described herein. One method of wafer processing includes modifying a peripheral edge of a wafer to...
US-7,972,926 Methods of forming memory cells; and methods of forming vertical structures
Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end...
US-7,972,753 Masks for microlithography and methods of making and using such masks
Masks for microlithography apparatus, methods for making such masks, and methods for exposing photosensitive materials to form arrays of microfeatures on...
US-7,970,964 Methods and systems to accomplish variable width data input
Disclosed are methods and systems for variable width data input to a pattern-recognition processor. A variable width data input method may include receiving...
US-7,970,958 Peripheral interface alert message for downstream device
According to some embodiments, a message generated by a downstream device is received at upstream device. The message may, for example, be received via a...
US-7,969,815 System and method for controlling timing of output signals
The timing of output signals can be controlled by coupling a digital signal through a signal distribution tree having a plurality of branches extending from an...
US-7,969,813 Write command and write data timing circuit and methods for timing the same
Circuits, memories, and methods for latching a write command and later provided write data including write command and write data timing circuits. One such...
US-7,969,788 Charge loss compensation methods and apparatus
Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss...
US-7,969,783 Memory with correlated resistance
A system or device including a memory device, as well as a method of operating the memory device. Such a method includes writing a plurality of data values to a...
US-7,969,782 Determining memory page status
The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. One method embodiment includes determining a status...
US-7,969,779 Integrated circuit including memory array having a segmented bit line architecture and method of controlling...
An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of bit lines (e.g., first and second bit...
US-7,969,776 Data cells with drivers and methods of making and operating the same
Disclosed are methods and devices, among which is a device that includes a first semiconductor fin having a first gate, a second semiconductor fin adjacent the...
US-7,969,774 Electronic devices formed of two or more substrates bonded together, electronic systems comprising electronic...
Electronic devices comprise a first substrate and a second substrate. The first substrate comprises circuitry including a plurality of conductive traces at...
US-7,969,490 Method, apparatus, and system providing an imager with pixels having extended dynamic range
The dynamic range of a pixel is increased by using selective photosensor resets during a frame time of image capture at a timing depending on the light...
US-7,969,488 Correction of cluster defects in imagers
A method and apparatus that allows for the correction of multiple defective pixels in an imager device. In one exemplary embodiment, the method includes the...
US-7,969,252 System and method for reducing lock time in a phase-locked loop
Increasing loop gain is a common practice for reducing lock time of phase locked loops. Very high loop gains, however, often result in increasing the lock time...
US-7,968,969 Electrical components for microelectronic devices
Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing...
US-7,968,962 Semiconductor fabrication method and system
A semiconductor device is disclosed. In one embodiment, a device includes a substrate having one or more vias and a carrier coupled to the substrate to form a...
US-7,968,960 Methods of forming strained semiconductor channels
In various method embodiments, a device region in a semiconductor substrate and isolation regions adjacent to the device region are defined. The device region...
US-7,968,954 Intermediate semiconductor device having nitrogen concentration profile
A method for reducing the effective thickness of a gate oxide using nitrogen implantation and anneal subsequent to dopant implantation and activation is...
US-7,968,951 Interconnecting bit lines in memory devices for multiplexing
An embodiment of a memory device has a plurality of conductive plugs formed on a semiconductor substrate and a pair of successively adjacent first and second...
US-7,968,930 Finned memory cells
For an embodiment, a memory array has a plurality fins protruding from a substrate. A tunnel dielectric layer overlies the fins. A plurality floating gates...
US-7,968,928 DRAM layout with vertical FETs and method of formation
DRAM cell arrays having a cell area of less than about 4 F.sup.2 comprise an array of vertical transistors with buried bit lines and vertical double gate...
US-7,968,927 Memory array for increased bit density and method of forming the same
A memory array having a plurality of resistance variable memory units and method for forming the same are provided. Each memory unit includes a first electrode,...
US-7,968,916 Circuit and method for interconnecting stacked integrated circuit dies
Signals are routed to and from identical stacked integrated circuit dies by selectively coupling first and second bonding pads on each of the dies to respective...
US-7,968,862 Phase change memory elements using self-aligned phase change material layers
A phase change memory element and method of forming the same. The memory element includes a substrate supporting a first electrode. An insulating material...
US-7,968,460 Semiconductor with through-substrate interconnect
Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor...
US-7,968,425 Isolation regions
Methods and apparatus are provided. An isolation region is formed by lining a trench formed in a substrate with a first dielectric layer by forming the first...
US-7,968,411 Threshold voltage adjustment for long-channel transistors
A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor...
US-7,968,406 Memory cells, methods of forming dielectric materials, and methods of forming memory cells
Some embodiments include memory cells. The memory cells may include a tunnel dielectric material, a charge-retaining region over the tunnel dielectric material,...
US-7,968,403 Method of fabricating a sleeve insulator for a contact structure
A method and structure are disclosed that are advantageous for aligning a contact plug within a bit line contact corridor (BLCC) to an active area of a DRAM...
US-7,968,402 Method for forming a high-performance one-transistor memory cell
One aspect of this disclosure relates to a memory cell. In various embodiments, the memory cell includes an access transistor having a floating node, and a...
US-7,968,376 Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged...
US-7,968,369 Microelectronic devices and microelectronic support devices, and associated assemblies and methods
Microelectronic devices, associated assemblies, and associated methods are disclosed herein. For example, certain aspects of the invention are directed toward a...
US-7,967,661 Systems and pads for planarizing microelectronic workpieces and associated methods of use and manufacture
Planarizing systems and methods of planarizing microelectronic workpieces using mechanical and/or chemical-mechanical planarization are disclosed herein. In one...
US-7,966,530 Methods, devices, and systems for experiencing reduced unequal testing degradation
One or more embodiments of the present invention reduce uneven degradation during testing by providing for a toggling signal to be applied to remaining input...
US-7,966,450 Non-volatile hard disk drive cache system and method
A non-volatile hard disk drive cache system is coupled between a processor and a hard disk drive. The cache system includes a control circuit, a non-volatile...
US-7,965,580 Method and apparatus for reducing oscillation in synchronous circuits
Control signal oscillation filtering circuits, delay-locked loops, clock synchronization methods and devices and systems incorporating control signal...
US-7,965,570 Precharge control circuits and methods for memory having buffered write commands
Memories, precharge control circuits, methods of controlling, and methods of utilizing are disclosed, including precharge control circuits for a memory having...
US-7,965,561 Row selector occupying a reduced device area for semiconductor memory devices
A memory device having a plurality of memory cells grouped in at least two memory sectors is disclosed. A first decoding circuit operable to receive address...
US-7,965,548 Systems and devices including memory resistant to program disturb and methods of using, making, and operating...
Disclosed are methods, systems and devices, one such device being a memory device configured to concurrently assert a first pulse pattern through a plurality of...
US-7,965,532 Enhanced performance memory systems and methods
Digital memory devices and systems, including memory systems and methods for operating such memory systems are disclosed. In the embodiments, a memory system...
US-7,965,444 Method and apparatus to improve filter characteristics of optical filters
An optical filter structure for an imager which has customized sub-wavelength elements used to maintain the filter characteristics accordingly across a...
US-7,965,330 Method and apparatus providing pixel storage gate charge sensing for electronic stabilization in imagers
An imaging device that stores charge from a photosensor under at least one storage gate. A driver used to operate the at least one storage gate, senses how much...
US-7,965,105 Input buffer with optimal biasing and method thereof
A method and circuit of a biased input buffer is described to maximize the quality in the output signals. The input buffer includes a first stage for receiving...
US-7,964,971 Flexible column die interconnects and structures including same
A flexible column interconnect for a microelectronic substrate includes a plurality of conductive columns extending from a bond pad or other conductive terminal...
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