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Patent # Description
US-8,006,166 Programming error correction code into a solid state memory device with varying bits per cell
Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to...
US-8,006,072 Reducing data hazards in pipelined processors to provide high processor utilization
A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of...
US-8,006,067 Flexible results pipeline for processing element
A flexible results pipeline for a processing element of a parallel processor is described. A plurality of result registers are selectively connected to each...
US-8,005,995 Command interface systems and methods
Apparatus, systems, and methods are disclosed that operate within a memory to execute internal commands, to suspend the execution of commands during a transfer...
US-8,004,920 Power saving memory apparatus, systems, and methods
Some embodiments include a voltage generator to generate a voltage to apply to a line used to access a memory cell of a memory device in which the voltage is...
US-8,004,909 Data bus power-reduced semiconductor storage apparatus
In one or more of the disclosed embodiments, the number of times toggle operations of a data bus are performed at the time of a data transmission in a...
US-8,004,892 Single latch data circuit in a multiple level cell non-volatile memory device
A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a...
US-8,004,887 Configurable digital and analog input/output interface in a memory device
Methods and memory devices are disclosed, for example a memory device that has both an analog path and a digital path that both share the same input/output pad....
US-8,004,882 Spintronic devices with integrated transistors
The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a...
US-8,004,313 Methods, devices, and systems for a high voltage tolerant buffer
Methods, devices, and systems are disclosed, including those for a buffer having pre-driver circuitry configured to provide voltages to thin-gate dielectric...
US-8,004,297 Isolation circuit
The present disclosure includes various method, device, and system embodiments for isolation circuits. One such isolation circuit embodiment includes: a first...
US-8,004,055 Electromagnetic radiation conduits
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
US-8,004,031 Memory device transistors
Method and device embodiments are described for fabricating MOSFET transistors in a semiconductor also containing non-volatile floating gate transistors. MOSFET...
US-8,003,985 Apparatus having a dielectric containing scandium and gadolinium
Apparatus having a dielectric containing scandium and gadolinium can provide a reliable structure with a high dielectric constant (high k). In an embodiment,...
US-8,003,972 Bottom electrode geometry for phase change memory
A PCRAM cell has a gradated or layered resistivity bottom electrode with higher resistivity closer to a phase change material, to provide partial heating near...
US-8,003,542 Multiple spacer steps for pitch multiplication
Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers...
US-8,003,541 Methods of forming variable resistance memory cells, and methods of etching germanium, antimony, and...
A method of etching a material that includes comprising germanium, antimony, and tellurium encompasses exposing said material to a plasma-enhanced etching...
US-8,003,526 Low resistance metal silicide local interconnects and a method of making
A process for forming a local interconnect includes applying a layer of metal over a semiconductor layer. A layer of metal silicide is formed over the layer of...
US-8,003,521 Semiconductor processing
Devices, methods, and systems for semiconductor processing are described herein. A number of method embodiments of semiconductor processing can include forming...
US-8,003,482 Methods of processing semiconductor substrates in forming scribe line alignment marks
A method of processing a semiconductor substrate in forming scribe line alignment marks includes forming pitch multiplied non-circuitry features within scribe...
US-8,003,310 Masking techniques and templates for dense semiconductor fabrication
A template comprising pitch multiplied and non-pitch multiplied features is configured for use in imprint lithography. On a first substrate, a first pattern is...
US-8,003,000 Plasma processing, deposition and ALD methods
A plasma processing method includes providing a substrate in a processing chamber, the substrate having a surface, and generating a plasma in the processing...
US-8,001,513 Integrated circuit apparatus, systems, and methods
High density circuit modules are formed by stacking integrated circuit (IC) chips one above another. Unused input/output (I/O) locations on some of the chips...
US-8,001,410 Efficient clocking scheme for ultra high-speed systems
There is provided a system for comparing the phase characteristics of three generated clock signals, each having a unique phase relationship with an original...
US-8,000,152 Charge pump operation in a non-volatile memory device
A charge pump in a memory device is activated to produce a programming voltage prior to data loading during a programming operation. During an initial...
US-8,000,151 Semiconductor memory column decoder device and method
Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in...
US-8,000,136 Non-volatile memory with both single and multiple level cells
Memory arrays and methods of operating such memory arrays are described as having a memory cell operated as a single level cell interposed between and coupled...
US-7,999,589 Circuits and methods for clock signal duty-cycle correction
Duty-cycle correction circuits, clock distribution networks, and methods for correcting duty-cycle distortion are disclosed, including methods and apparatus for...
US-7,999,334 Hafnium tantalum titanium oxide films
Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed...
US-7,999,330 Dynamic random access memory device and electronic systems
The invention includes methods of utilizing compositions containing iridium and tantalum in semiconductor constructions, and includes semiconductor...
US-7,999,328 Isolation trench having first and second trench areas of different widths
A method of forming and resulting isolation region, which allows for densification of an oxide layer in the isolation region. One exemplary embodiment of the...
US-7,998,860 Method for fabricating semiconductor components using maskless back side alignment to conductive vias
A method for fabricating semiconductor components includes the steps of: providing a semiconductor substrate having a circuit side, a back side and conductive...
US-7,998,813 Methods of fabricating an access transistor having a polysilicon-comprising plug on individual of opposing...
Fabrication methods for gate transistors in integrated circuit devices enable the formation of recessed access device structures or FinFET structures having...
US-7,998,809 Method for forming a floating gate using chemical mechanical planarization
An improved process forming a floating gate region of a semiconductor memory device. The process includes using a ceria slurry for chemical mechanical...
US-7,998,305 Electrical interconnect using locally conductive adhesive
An anisotropic electrically conducting interconnect is disclosed in which an adhesive comprising particles having a breakable coating of at least one...
US-7,997,958 Apparatuses and methods for conditioning polishing pads used in polishing micro-device workpieces
Apparatuses and methods for conditioning polishing pads used in polishing micro-device workpieces are disclosed herein. In one embodiment, an end effector for...
US-7,997,954 Centerless grinding method
To provide a centerless grinding method which facilitates a tooling change and enables automation. A blade 11 is disposed slidable along a first straight line...
US-7,996,727 Error correction for memory
Methods and devices operate to apply and provide differing levels of error correction within a multi-level, non-volatile memory. In an example, the differing...
US-7,995,415 System and method for reducing power consumption during extended refresh periods of dynamic random access...
A dynamic random access memory ("DRAM") device is operable in either a normal refresh mode or a static refresh mode, such as a self-refresh mode. A cell plate...
US-7,995,412 Analog-to-digital and digital-to-analog conversion window adjustment based on reference cells in a memory device
An analog-to-digital conversion window is defined by reference voltages stored in reference memory cells of a memory device. A first reference voltage is read...
US-7,995,402 Method for erasing a semiconductor magnetic memory integrating a magnetic tunneling junction above a...
A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating...
US-7,995,400 Reducing effects of program disturb in a memory device
The programming disturb effects in a semiconductor non-volatile memory device are reduced by biasing unselected word lines of a memory block with a negative...
US-7,995,399 NAND memory device and programming methods
A NAND Flash memory device reduces circuitry noise during program operations. The memory includes bit lines that are electrically coupled together to charge...
US-7,995,395 Charge loss compensation during programming of a memory device
A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a...
US-7,995,391 Multiple select gates with non-volatile memory cells
Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and...
US-7,995,365 Method and apparatuses for managing double data rate in non-volatile memory
Described herein are a method and apparatuses for providing DDR memory access. In one embodiment, an apparatus includes a data storage unit to store and...
US-7,994,849 Devices, systems, and methods for generating a reference voltage
Methods, devices, and systems are disclosed for a voltage reference generator. A voltage reference generator may comprise a bandgap voltage reference circuit...
US-7,994,595 Strained semiconductor by full wafer bonding
One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined...
US-7,994,566 Stacked non-volatile memory with silicon carbide-based amorphous silicon finFETs
A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a...
US-7,994,547 Semiconductor devices and assemblies including back side redistribution layers in association with through...
Low temperature processed back side redistribution lines (RDLs) are disclosed. Low temperature processed back side RDLs may be electrically connected to the...
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