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Patent # Description
US-8,107,296 Mitigation of data corruption from back pattern and program disturb in a non-volatile memory device
In one of the disclosed embodiments, a write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program...
US-8,107,218 Capacitors
Some embodiments include methods of forming capacitors. A metal oxide mixture may be formed over a first capacitor electrode. The metal oxide mixture may have a...
US-8,106,644 Reference circuit with start-up control, generator, device, system and method including same
A reference generator circuit generates a reference signal for use by a regulator in generating operational power for circuits and devices. A start-up circuit...
US-8,106,520 Signal delivery in stacked device
Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a...
US-8,106,491 Methods of forming stacked semiconductor devices with a leadframe and associated assemblies
A device is disclosed which includes a first packaged integrated circuit device, a second packaged integrated circuit device positioned above the first packaged...
US-8,106,488 Wafer level packaging
Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of...
US-8,106,438 Stud capacitor device and fabrication method
The present teachings relate to a method of forming a container capacitor structure on a substrate. In one embodiment, the method comprises etching a recess in...
US-8,105,956 Methods of forming silicon oxides and methods of forming interlevel dielectrics
A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an...
US-8,105,896 Methods of forming capacitors
A method of forming a capacitor includes forming a conductive first capacitor electrode material comprising TiN over a substrate. TiN of the TiN-comprising...
US-8,105,862 Imager with tuned color filter
An optimized color filter array is formed in, above or below one or more damascene layers. The color filter array includes filter regions which are configured...
US-8,105,858 CMOS imager having a nitride dielectric
An imaging device formed as a CMOS semiconductor integrated circuit includes a nitrogen containing insulating material beneath a photogate. The nitrogen...
US-8,105,131 Method and apparatus for removing material from microfeature workpieces
Methods and apparatus for removing materials from microfeature workpieces. One embodiment of a subpad in accordance with the invention comprises a matrix having...
US-8,103,940 Programming error correction code into a solid state memory device with varying bits per cell
Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to...
US-8,103,936 System and method for data read of a synchronous serial interface NAND
A method and system is disclosed for operating a NAND memory device. The NAND memory device is operated by transmitting serial peripheral interface signals from...
US-8,103,928 Multiple device apparatus, systems, and methods
Data digits and correction digits are received in each of a number of integrated circuit (IC) devices. Apparatus, systems, and methods are disclosed that...
US-8,103,898 Explicit skew interface for mitigating crosstalk and simultaneous switching noise
Methods and apparatus are disclosed, such as those involving an inter-chip interface configured to receive and process electronic data. One such interface...
US-8,103,805 Configuration finalization on first valid NAND command
A startup method and circuit to allow high current consumption for startup processes of a low operating voltage memory device such as a NAND device until the...
US-8,102,906 Fractional-rate decision feedback equalization useful in a data transmission system
Decision feedback equalization (DFE) circuits are disclosed for use with fractional-rate clocks of lesser frequency than the data signal. For example, a...
US-8,102,723 Memory device bit line sensing system and method that compensates for bit line resistance variations
Systems, devices and methods are disclosed, such as a system and method of sensing the voltage on bit lines that, when respective memory cells coupled to the...
US-8,102,715 Power-off apparatus, systems, and methods
Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as...
US-8,102,710 System and method for setting access and modification for synchronous serial interface NAND
The invention includes a system and method of modifying a setting of a NAND flash memory device using serial peripheral interface (SPI) communication from a...
US-8,102,709 Transistor having peripheral channel
Transistors for use in semiconductor integrated circuit devices including a first source/drain region of the transistor is formed around a perimeter of a...
US-8,102,707 Non-volatile multilevel memory cells
The present disclosure includes methods, devices, modules, and systems for operating non-volatile multilevel memory cells. One method embodiment includes...
US-8,102,706 Programming a memory with varying bits per cell
Memory devices adapted to receive and transmit analog data signals representative of two or more bits, such as to facilitate increases in data transfer rates...
US-8,102,700 Unidirectional spin torque transfer magnetic memory cell structure
Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices...
US-8,102,410 Writing apparatuses and methods
Patterns are written on workpieces, such as, glass sheets and/or plastic sheets used in, for example, electronic display devices such as LCDs. The workpiece may...
US-8,102,295 Integrators for delta-sigma modulators
Methods, systems and devices are disclosed. Among the disclosed devices is an electronic device that, in certain embodiments, includes a plurality of memory...
US-8,102,013 Lanthanide doped TiO.sub.x films
The use of atomic layer deposition (ALD) to form an amorphous dielectric layer of titanium oxide (TiO.sub.X) doped with lanthanide elements, such as samarium,...
US-8,102,008 Integrated circuit with buried digit line
A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a...
US-8,102,006 Different gate oxides thicknesses for different transistors in an integrated circuit
An integrated circuit and gate oxide forming process are disclosed which provide a gate structure that is simple to integrate with conventional fabrication...
US-8,101,992 Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines
A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access...
US-8,101,936 SnSe-based limited reprogrammable cell
Methods and apparatus for providing a memory device that can be programmed a limited number of times. According to exemplary embodiments, a memory device and...
US-8,101,903 Method, apparatus and system providing holographic layer as micro-lens and color filter array in an imager
A method, apparatus, and system that provides a holographic layer as a micro-lens array and/or a color filter array in an imager. The method of writing the...
US-8,101,497 Self-aligned trench formation
Methods for forming a semiconductor device include forming self-aligned trenches, in which a first set of trenches is used to align a second set trenches....
US-8,101,464 Microelectronic devices and methods for manufacturing microelectronic devices
Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. One such method includes forming a plurality of apertures in...
US-8,101,459 Methods for assembling semiconductor devices in stacked arrangements by positioning spacers therebetween
A method for assembling semiconductor devices includes providing a first semiconductor device, securing spacers to noncircuit bond pads of the first...
US-8,101,454 Method of forming pixel cell having a grated interface
A pixel cell having a photosensor within a silicon substrate; and an oxide layer provided over the photosensor, the oxide layer having a grated interface with...
US-8,101,261 One-dimensional arrays of block copolymer cylinders and applications thereof
Methods for fabricating sublithographic, nanoscale microstructures in one-dimensional arrays utilizing self-assembling block copolymers, and films and devices...
US-8,099,543 Methods of operarting memory devices within a communication protocol standard timeout requirement
The present disclosure includes methods and devices for logical memory blocks. One method for operating a memory device includes receiving a command to operate...
US-8,099,366 Software distribution method and apparatus
The present invention provides for a method and apparatus for distributing digital information, such as software applications, to application users. By...
US-8,098,530 Systems and methods for erasing a memory
Methods of erasing a memory, methods of operating a memory, memory devices, and systems. In one such method, an erase block is erased to an intermediate erase...
US-8,098,529 Memory device having buried boosting plate and methods of operating the same
Memory devices are disclosed, such as those that include a semiconductor-on-insulator (SOI) NAND memory array having a boosting plate. The boosting plate may be...
US-8,098,180 Devices including analog-to-digital converters for internal data storage locations
A device that includes an internal data storage location coupled to an electrical conductor and an analog-to-digital converter coupled to the internal data...
US-8,097,947 Conductive systems and devices including wires coupled to anisotropic conductive film, and methods of forming...
Methods and apparatus for eliminating wire sweep and shorting while avoiding the use of under-bump metallization and high cost attendant to the use of...
US-8,097,910 Vertical transistors
The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain...
US-8,097,908 Antiblooming imaging apparatus, systems, and methods
Apparatus, systems, and methods are described to assist in reducing dark current in an active pixel sensor. In various embodiments, a potential barrier...
US-8,097,537 Phase change memory cell structures and methods
Phase change memory cell structures and methods are described herein. A number of methods of forming a phase change memory cell structure include forming a...
US-8,097,506 Shallow trench isolation for a memory
In some embodiments, a gate structure with a spacer on its side may be used as a mask to form self-aligned trenches in a microelectronic memory, such as a flash...
US-8,097,175 Method for selectively permeating a self-assembled block copolymer, method for forming metal oxide structures,...
Methods of forming metal oxide structures and methods of forming metal oxide patterns on a substrate using a block copolymer system formulated for...
US-8,095,835 Error scanning in flash memory
Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is...
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