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The present invention relates to an apparatus for creating a pattern on a workpiece sensitive to radiation, such as a photomask a display panel or a...
Imager methods, apparatuses, and systems providing a skip mode with a wide
dynamic range operation
Methods, apparatuses and systems provide a high dynamic range mode of operation for an image sensor when operating in a skip mode where certain pixels of an...
Active pixel sensor with mixed analog and digital signal integration
An active pixel sensor includes mixed analog and digital signal integration on the same substrate. The analog part of the array forms the active pixel sensor,...
Adaptive operational transconductance amplifier load compensation
A buffer varies the size of its output stage in response to a varying capacitive load. The capacitive load may vary in a predictable or a random manner. The...
Variable stage charge pump and method for providing boosted output voltage
An embodiment of a variable stage charge pump includes a plurality of pump stages. Each stage is configured to generate an intermediate boosted output voltage....
Output driver robust to data dependent noise
Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may...
Through-wafer interconnects for photoimager and memory wafers
A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making...
Lanthanide dielectric with controlled interfaces
Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer...
Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material...
Double-doped polysilicon floating gate
The present invention provides a method and apparatus for forming a double-doped polysilicon floating gate in a semiconductor memory element. The method...
Methods of forming semiconductor structures
The present invention relates to methods of forming semiconductor structures. The methods may include disposing electrically conductive material within an...
Methods of determining x-y spatial orientation of a semiconductor
substrate comprising an integrated circuit,...
The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a...
Non-volatile memory cell devices and methods
A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming an intergate dielectric layer over the nanodots,...
Fabrication of self-aligned gallium arsenide MOSFETS using damascene gate
A method for fabricating a gallium arsenide MOSFET device is presented. A dummy gate is formed over a gallium arsenide substrate. Source-drain extensions are...
Packaged microelectronic devices and methods for manufacturing packaged
Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a method for forming a...
Microfluidic mixing and analytical apparatus
Disclosed herein is a device comprising a pair of bellows pumps configured for efficient mixing at a microfluidic scale. By moving a fluid sample and particles...
Methods to make sidewall light shields for color filter array
Methods of forming color filters having a light blocking material therebetween. A color filter is formed such that a trench is defined between a color filter...
System, apparatus, and method for memory built-in self testing using
Apparatuses, systems, and methods are disclosed for performing Built-In Self Tests (BIST) on memories. One such BIST includes loading microcode instructions...
Systems and methods for retrieving data
Apparatus and methods, such as those that read data from non-volatile integrated circuit memory devices, such as NAND flash. For example, disclosed techniques...
Flash storage partial page caching
Methods and apparatus may operate to receive allocation requests from a processor configured to manage memory comprising a non-volatile memory device...
Jittery signal generation with discrete-time filtering
The computer-implementable method allows for the fast creation of a multi-unit interval data signal suitable for simulation. The created signal represents the...
Reduction of fusible links and associated circuitry on memory dies
The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among...
Methods and devices are disclosed, some such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory...
Adjusting program and erase voltages in a memory device
A method and apparatus for adjusting threshold program and erase voltages in a memory array, such as a floating gate memory array, for example. A method...
NAND memory device and programming methods
A NAND Flash memory device is described that can reduce bit line coupling and floating gate coupling during program and verify operations. Consecutive bit lines...
Method for programming a non-volatile memory device to reduce
floating-gate-to-floating-gate coupling effect
A method for programming a non-volatile memory array comprising a plurality of memory cells. Each cell is adapted to store a lower and an upper page of data....
Phase change memory structure with multiple resistance states and methods
of programming and sensing same
A phase change memory structure with multiple resistance states and methods of forming, programming, and sensing the same. The memory structure includes two or...
Back gated SRAM cell
One method for operating an SRAM cell includes applying a potential to a back gate of a pair of cross coupled p-type pull up transistors in the SRAM during a...
CMOS imager with integrated circuitry
A CMOS imager is integrated on a single substrate along with logic and support circuitry for decoding and processing optical information received by the CMOS...
Distributed semiconductor device methods, apparatus, and systems
Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be...
Method and apparatus providing air-gap insulation between adjacent
conductors using nanoparticles
A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is...
Die stacking with an annular via having a recessed socket
A die stack including a die having an annular via with a recessed conductive socket and methods of forming the die stack provide a structure for use in a...
System including semiconductor components having through interconnects and
back side redistribution conductors
A system includes a supporting substrate and at least one semiconductor substrate. The semiconductor component includes a semiconductor substrate having a...
An isolation circuit, comprising a first transistor having a gate, a first source/drain terminal, and a second source/drain terminal, a first pad coupled to the...
Elevated pocket pixels, imaging devices and systems including the same and
method of forming the same
An elevated photosensor for image sensors and methods of forming the photosensor. The photosensor may have light sensors having indentation features including,...
Reduced edge effect from recesses in imagers
Methods for making a recessed color filter array for a semiconductor imager employing a sidewall spacer for reducing an edge effect from the array are...
Method and apparatus providing integrated circuit having redistribution
layer with recessed connectors
A method of making a semiconductor die includes forming a trench around a conductive stud extending from the first side to a second side of a substrate to...
Methods for fabricating semiconductor components with conductive
interconnects having planar surfaces
A backside method for fabricating a semiconductor component with a conductive interconnect includes the step of providing a semiconductor substrate having a...
Diodes, and methods of forming diodes
Some embodiments include methods of forming diodes. The methods may include oxidation of an upper surface of a conductive electrode to form an oxide layer over...
Methods of forming electrically conductive structures
Some embodiments include methods of forming conductive material within high aspect ratio openings and low aspect ratio openings. Initially, the high aspect...
Pipelined burst memory access
A memory device for multichannel continuous or fixed burst mode operation includes multiple burst address counter circuits and associated control logic to...
Storage capacity status
In one embodiment of the present invention, a memory device is disclosed to include memory organized into blocks, each block having a status associated...
Method of storing data on a flash memory device
Methods and apparatus are disclosed, such as those involving a flash memory device. One such method includes storing data on memory cells on a memory block...
System and method for transmitting data packets in a computer system
having a memory hub architecture
A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled...
Reduced signal interface memory device, system, and method
A memory has a serial interface. The serial interface is programmable to either use separate dedicated input and output pads, or to use one bidirectional pad....
Sensing memory cells
The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to...
Temperature compensation in memory devices and systems
Devices, methods, and systems for temperature compensation in memory devices, such as resistance variable memory, among other types of memory are included. A...
Rank select using a global select pin
Methods, memory devices, and systems are disclosed, such as those for accessing a memory circuit through the use of reduced external pins. With one such system,...
There is provided a true single phase logic clock divider that is configured to selectively divide a clock signal by increments of two, three, four, or six....
Semiconductor constructions of memory devices with different sizes of
Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C.sub.4F.sub.6 and C.sub.4F.sub.3. The recessed...