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Floating body field-effect transistors, and methods of forming floating
body field-effect transistors
In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween....
Semiconductor devices and methods for forming patterned radiation blocking
on a semiconductor device
Several embodiments for semiconductor devices and methods for forming semiconductor devices are disclosed herein. One embodiment is directed to a method for...
Methods of titanium deposition
Some embodiments include methods of titanium deposition in which a silicon-containing surface and an electrically insulative surface are both exposed to...
Recessed gate silicon-on-insulator floating body device with self-aligned
Embodiments of a manufacturing process for recessed gate devices on silicon-on-insulator (SOI) substrate with self-aligned lateral isolation are described. This...
Microelectronic die packages with leadframes, including leadframe-based
interposer for stacked die packages,...
Microelectronic die packages, stacked systems of die packages, and methods of manufacturing thereof are disclosed herein. In one embodiment, a method of...
Reduced lens heating methods, apparatus, and systems
In one embodiment, a system is disclosed that includes an illuminator having a source that produces light waves having a first wavelength, and a mask. The mask...
Contact and electrical connecting apparatus
A contact type electrical connector includes a first plunger in contact with one member; a second plunger in contact with another member and electrically...
Memory array error correction apparatus, systems, and methods
Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being...
Synchronous command-based write recovery time auto-precharge control
Methods of operating a memory device and memory devices are provided. For example, a method of operating a memory array is provided that includes a synchronous...
Software refreshed memory device and method
A software refreshed memory device comprises a plurality of memory cells that must be periodically refreshed to avoid losing data. Preferably, the memory cells...
Writing to non-volatile memory during a volatile memory refresh cycle
Writing to non-volatile memory during a volatile memory refresh cycle is described. In one example, a write command is received and data is received to write...
Non-volatile memory control
Methods and apparatus for use in a memory system having a non-volatile memory and a controller for limiting the number of non-volatile memory arrays from a...
Memory device having strobe terminals with multiple functions
A memory device has data transceivers, write strobe transceivers, and read strobe transceivers. The data transceivers transfer input data to the memory device...
Non-volatile multilevel memory cell programming
Embodiments of the present disclosure provide methods, devices, modules, and systems for programming multilevel non-volatile multilevel memory cells. One method...
Erase verify in memory devices
In one or more embodiments, methods for erasing memory devices, and a memory system are disclosed, one such method comprising determining which cells of a...
Erase block data splitting
A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data...
Methods of making a semiconductor memory device
One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base...
Spin torque transfer cell structure utilizing field-induced
antiferromagnetic or ferromagnetic coupling
A magnetic memory cell including a soft magnetic layer and a coupling layer, and methods of operating the memory cell are provided. The memory cell includes a...
Method, apparatus and system for dynamic range estimation of imaged scenes
A method, apparatus, and system for dynamic range estimation of imaged scenes for automatic exposure control. For a given exposure time setting, certain areas...
Bias circuit and amplifier providing constant output current for a range
of common mode inputs
Bias circuits, amplifiers and methods are provided, such as those for providing bias signals over a range of common mode inputs for an amplifier to output a...
Programmable on-chip logic analyzer apparatus, systems, and methods
Apparatus, systems, and methods disclosed herein may cause an event trigger state machine associated with a programmable on-chip logic analyzer (POCLA) to...
The invention includes a process whereby a solvent is utilized to remove soluble portions of a resist, and subsequently the solvent can be removed with a...
Voltage-controlled semiconductor inductor and method
A voltage-controlled semiconductor inductor and method is provided. According to various embodiments, the voltage-controlled inductor includes a conductor...
Phase change current density control structure
A phase change memory element and method of forming the same. The memory element includes first and second electrodes. A first layer of phase change material is...
Advanced VLSI metallization
A four layer interconnect structure is disclosed which includes a bottom conductive reactive layer such as titanium, a conductive barrier layer, such as...
Trench interconnect structure and formation method
Embodiments concern vertical interconnect structures having sub-micron widths for use in integrated circuits, and methods of their manufacture, which result in...
Systems and methods of forming tantalum silicide layers
A method of forming (and apparatus for forming) tantalum silicide layers (including tantalum silicon nitride layers), which are typically useful as diffusion...
Methods of semiconductor processing involving forming doped polysilicon on
A number of methods are provided for semiconductor processing. One such method includes depositing a first precursor material on a surface at a particular...
Wafer level pre-packaged flip chip
Methods for producing a flip chip package by prepackaging one or more dice on a semiconductor wafer are provided. An embodiment of the method includes applying...
Method for error test, recordation and repair
In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test....
Optical interconnect in high-speed memory systems
A optical link for achieving electrical isolation between a controller and a memory device is disclosed. The optical link increases the noise immunity of...
Power off apparatus, systems, and methods
Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as...
Dynamic polarization for reducing stress induced leakage current
Subject matter disclosed herein relates to non-volatile flash memory, and more particularly to a method of reducing stress induced leakage current.
Memory array having a programmable word length, and method of operating
A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or...
Resistance variable memory device with sputtered metal-chalcogenide region
and method of fabrication
A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a chalcogenide glass region is provided with a plurality of...
Duty cycle correction systems and methods
Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a...
Method and apparatus for output driver calibration, and memory devices and
system embodying same
A method, system, and output driver calibration circuit determine calibration values for configuring adjustable impedance output drivers. The calibration...
Semiconductor device with copper wirebond sites and methods of making same
Semiconductor devices with external wirebond sites that include copper and methods for fabricating such semiconductor devices are disclosed. One embodiment of a...
Interconnect structures with bond-pads and methods of forming bump sites
Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example,...
DRAM unit cells, capacitors, methods of forming DRAM unit cells, and
methods of forming capacitors
Some embodiments include methods of forming capacitors. A first capacitor storage node may be formed within a first opening in a first sacrificial material. A...
Methods of forming hybrid conductive vias including small dimension active
surface ends and larger dimension...
A conductive via of a semiconductor device includes a relatively small diameter portion extending into an active surface of a fabrication substrate and a...
Strontium ruthenium oxide interface
Strontium ruthenium oxide provides an effective interface between a ruthenium conductor and a strontium titanium oxide dielectric. Formation of the strontium...
Peripheral gate stacks and recessed array gates
Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic...
Methods of forming a field effect transistors, pluralities of field effect
transistors, and DRAM circuitry...
A method of forming a field effect transistor includes forming trench isolation material within a semiconductor substrate and on opposing sides of a...
Multiple-depth STI trenches in integrated circuit fabrication
Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths....
Configuration of a multi-level flash memory device
A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the...
Waveguide for thermo optic device
A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the...
Fractional-rate decision feedback equalization useful in a data
Decision feedback equalization (DFE) circuits are disclosed for use with fractional-rate clocks of lesser frequency than the data signal. For example, a...
System and method for processing signals in high speed DRAM
A method is disclosed for operating a memory device, including providing a timing signal comprising a plurality of clock cycles, providing an activate signal,...
System and method for synchronizing asynchronous signals without external
One or more techniques are provided for the synchronization of asynchronous signals without the use of an external system clock. In one embodiment, an...