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Patent # Description
US-7,969,252 System and method for reducing lock time in a phase-locked loop
Increasing loop gain is a common practice for reducing lock time of phase locked loops. Very high loop gains, however, often result in increasing the lock time...
US-7,968,969 Electrical components for microelectronic devices
Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing...
US-7,968,962 Semiconductor fabrication method and system
A semiconductor device is disclosed. In one embodiment, a device includes a substrate having one or more vias and a carrier coupled to the substrate to form a...
US-7,968,960 Methods of forming strained semiconductor channels
In various method embodiments, a device region in a semiconductor substrate and isolation regions adjacent to the device region are defined. The device region...
US-7,968,954 Intermediate semiconductor device having nitrogen concentration profile
A method for reducing the effective thickness of a gate oxide using nitrogen implantation and anneal subsequent to dopant implantation and activation is...
US-7,968,951 Interconnecting bit lines in memory devices for multiplexing
An embodiment of a memory device has a plurality of conductive plugs formed on a semiconductor substrate and a pair of successively adjacent first and second...
US-7,968,930 Finned memory cells
For an embodiment, a memory array has a plurality fins protruding from a substrate. A tunnel dielectric layer overlies the fins. A plurality floating gates...
US-7,968,928 DRAM layout with vertical FETs and method of formation
DRAM cell arrays having a cell area of less than about 4 F.sup.2 comprise an array of vertical transistors with buried bit lines and vertical double gate...
US-7,968,927 Memory array for increased bit density and method of forming the same
A memory array having a plurality of resistance variable memory units and method for forming the same are provided. Each memory unit includes a first electrode,...
US-7,968,916 Circuit and method for interconnecting stacked integrated circuit dies
Signals are routed to and from identical stacked integrated circuit dies by selectively coupling first and second bonding pads on each of the dies to respective...
US-7,968,862 Phase change memory elements using self-aligned phase change material layers
A phase change memory element and method of forming the same. The memory element includes a substrate supporting a first electrode. An insulating material...
US-7,968,460 Semiconductor with through-substrate interconnect
Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor...
US-7,968,425 Isolation regions
Methods and apparatus are provided. An isolation region is formed by lining a trench formed in a substrate with a first dielectric layer by forming the first...
US-7,968,411 Threshold voltage adjustment for long-channel transistors
A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor...
US-7,968,406 Memory cells, methods of forming dielectric materials, and methods of forming memory cells
Some embodiments include memory cells. The memory cells may include a tunnel dielectric material, a charge-retaining region over the tunnel dielectric material,...
US-7,968,403 Method of fabricating a sleeve insulator for a contact structure
A method and structure are disclosed that are advantageous for aligning a contact plug within a bit line contact corridor (BLCC) to an active area of a DRAM...
US-7,968,402 Method for forming a high-performance one-transistor memory cell
One aspect of this disclosure relates to a memory cell. In various embodiments, the memory cell includes an access transistor having a floating node, and a...
US-7,968,376 Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged...
US-7,968,369 Microelectronic devices and microelectronic support devices, and associated assemblies and methods
Microelectronic devices, associated assemblies, and associated methods are disclosed herein. For example, certain aspects of the invention are directed toward a...
US-7,967,661 Systems and pads for planarizing microelectronic workpieces and associated methods of use and manufacture
Planarizing systems and methods of planarizing microelectronic workpieces using mechanical and/or chemical-mechanical planarization are disclosed herein. In one...
US-7,966,530 Methods, devices, and systems for experiencing reduced unequal testing degradation
One or more embodiments of the present invention reduce uneven degradation during testing by providing for a toggling signal to be applied to remaining input...
US-7,966,450 Non-volatile hard disk drive cache system and method
A non-volatile hard disk drive cache system is coupled between a processor and a hard disk drive. The cache system includes a control circuit, a non-volatile...
US-7,965,580 Method and apparatus for reducing oscillation in synchronous circuits
Control signal oscillation filtering circuits, delay-locked loops, clock synchronization methods and devices and systems incorporating control signal...
US-7,965,570 Precharge control circuits and methods for memory having buffered write commands
Memories, precharge control circuits, methods of controlling, and methods of utilizing are disclosed, including precharge control circuits for a memory having...
US-7,965,561 Row selector occupying a reduced device area for semiconductor memory devices
A memory device having a plurality of memory cells grouped in at least two memory sectors is disclosed. A first decoding circuit operable to receive address...
US-7,965,548 Systems and devices including memory resistant to program disturb and methods of using, making, and operating...
Disclosed are methods, systems and devices, one such device being a memory device configured to concurrently assert a first pulse pattern through a plurality of...
US-7,965,532 Enhanced performance memory systems and methods
Digital memory devices and systems, including memory systems and methods for operating such memory systems are disclosed. In the embodiments, a memory system...
US-7,965,444 Method and apparatus to improve filter characteristics of optical filters
An optical filter structure for an imager which has customized sub-wavelength elements used to maintain the filter characteristics accordingly across a...
US-7,965,330 Method and apparatus providing pixel storage gate charge sensing for electronic stabilization in imagers
An imaging device that stores charge from a photosensor under at least one storage gate. A driver used to operate the at least one storage gate, senses how much...
US-7,965,105 Input buffer with optimal biasing and method thereof
A method and circuit of a biased input buffer is described to maximize the quality in the output signals. The input buffer includes a first stage for receiving...
US-7,964,971 Flexible column die interconnects and structures including same
A flexible column interconnect for a microelectronic substrate includes a plurality of conductive columns extending from a bond pad or other conductive terminal...
US-7,964,946 Semiconductor package having discrete components and system containing the package
A semiconductor package includes a substrate having contacts, and a discrete component on the substrate in electrical communication with the contacts. The...
US-7,964,909 Scalable high density non-volatile memory cells in a contactless memory array
A plurality of mesas are formed in the substrate. Each pair of mesas forms a trench. A plurality of diffusion areas are formed in the substrate. A mesa...
US-7,964,503 Methods of patterning photoresist, and methods of forming semiconductor constructions
The invention includes semiconductor constructions containing optically saturable absorption layers. An optically saturable absorption layer can be between...
US-7,964,471 Methods of forming capacitors
A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and...
US-7,964,242 Formation of carbon-containing material
A method includes forming ionic clusters of carbon-containing molecules, which molecules have carbon-carbon sp.sup.2 bonds, and accelerating the clusters. A...
US-7,964,124 Method of forming cellular material
Systems, devices and methods are provided that are related to cellular materials that have a precisely-determined arrangement of voids formed using surface...
US-7,964,109 Method of cleaning a surface of a cobalt-containing material, method of forming an opening to a...
The invention includes methods of cleaning a surface of a cobalt-containing material, methods of forming an opening to a cobalt-containing material,...
US-7,964,107 Methods using block copolymer self-assembly for sub-lithographic patterning
Block copolymers can be self-assembled and used in methods as described herein for sub-lithographic patterning, for example. The block copolymers can be diblock...
US-7,962,784 Repairable block redundancy scheme
A scheme for block substitution within a flash memory device is disclosed which uses a programmable look-up table to store new addresses for block selection...
US-7,961,538 Methods for determining resistance of phase change memory elements
Methods for measuring the resistance of multiple memory elements are disclosed. The memory elements may be multi-bit memory and through precise measurement of...
US-7,961,526 Power saving sensing scheme for solid state memory
Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a...
US-7,961,522 Method and system for minimizing number of programming pulses used to program rows of non-volatile memory cells
A flash memory device programs cells in each row in a manner that minimizes the number of programming pulses that must be applied to the cells during...
US-7,961,518 Programming rate identification and control in a solid state memory
Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer...
US-7,961,517 Program and read trim setting
A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device...
US-7,961,507 Non-volatile memory with resistive access component
Some embodiments include apparatus and methods having a memory element configured to store information and an access component configured to allow conduction of...
US-7,961,506 Multiple memory cells with rectifying device
Memory devices and methods described are shown that provide improvements, including improved cell isolation for operations such as read and write. Further,...
US-7,961,488 Method for modifying data more than once in a multi-level cell memory location within a memory array
A method and apparatus for programming one or more bits in an upper page twice depending on the value in a corresponding bit in a corresponding lower page in a...
US-7,961,341 Print system, print data supplying device, and method for supplying print data to printer
A print system includes: a printer; and a print data supplying device. The print data supplying device includes: a print data supplying unit that supplies the...
US-7,961,292 Sub-resolution assist devices and methods
Photolithographic apparatus, systems, and methods that make use of sub-resolution assist devices are disclosed. In the various embodiments, an imaging mask...
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