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Patent # Description
US-8,014,216 Devices, systems, and methods for a power generator system
Methods, devices, and systems are provided for a power generator system. The power generator system may include at least one control device including control...
US-8,014,208 Erase verification for flash memory
Example embodiments for verifying an erase operation for a flash memory device may comprise, for one or more embodiments, utilizing program operation...
US-8,014,195 Single transistor memory cell
A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one...
US-8,013,915 Anti-eclipsing circuit for image sensors
An anti-eclipse circuit of an image pixel includes a clamping circuit for pulling up a voltage of a reset signal output by the pixel and an eclipse detection...
US-8,013,579 Voltage trimming
Embodiments are provided that include a memory die, memory devices, and methods, such as those comprising a voltage generator, including an output voltage and...
US-8,013,411 Method and structure to reduce optical crosstalk in a solid state imager
Methods and structures to reduce optical crosstalk in solid state imager arrays. Sections of pixel material layers that previously would have been etched away...
US-8,013,376 Memory arrays, semiconductor constructions and electronic systems with transistor gates extending partially...
Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within...
US-8,013,371 Ultra thin TCS (SiCl.sub.4) cell nitride for DRAM capacitor with DCS (SiH.sub.2Cl.sub.2) interface seeding layer
A method for forming silicon nitride films on semiconductor devices is provided. In one embodiment of the method, a silicon-comprising substrate is first...
US-8,012,847 Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating...
First and second isolation trenches are formed into semiconductive material of a semiconductor substrate. The first isolation trench has a narrowest outermost...
US-8,012,776 Methods of manufacturing imaging device packages
Methods of manufacturing an imaging device package are provided. In accordance with an embodiment a sensor die may be coupled to bond pads on a transparent...
US-8,012,674 Efficient pitch multiplication process
Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated...
US-8,012,532 Methods of making crystalline tantalum pentoxide
There is disclosed a method of forming crystalline tantalum pentoxide on a ruthenium-containing material having an oxygen-containing surface wherein the...
US-8,011,513 Semiconductor workpiece carriers and methods for processing semiconductor workpieces
Semiconductor workpiece carriers and methods for processing semiconductor workpieces are disclosed herein. In one embodiment, a semiconductor workpiece carrier...
US-8,011,296 Supercritical fluid-assisted direct write for printing integrated circuits
High resolution patterns provided on a surface of a semiconductor substrate and methods of direct printing of such high resolution patterns are disclosed. The...
US-8,011,092 Methods of providing semiconductor components within sockets
The invention includes methods of utilizing removable mechanical precising mechanisms and/or optical-based precising mechanisms to align chips within sockets....
US-8,011,090 Method for forming and planarizing adjacent regions of an integrated circuit
Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction...
US-8,010,866 Memory system and method using stacked memory device dice, and system using the memory system
A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that...
US-8,009,487 System and method for mitigating reverse bias leakage
The present disclosure includes devices, methods, and systems for programming memory, such as resistance variable memory. One embodiment can include an array of...
US-8,009,478 Non-volatile memory apparatus and methods
Some embodiments include apparatus and methods having memory cells coupled in series and a module to cause an application of voltages with at least three...
US-8,009,460 Device and method for using dynamic cell plate sensing in a DRAM memory cell
A memory cell, device, system and method for operating a memory cell utilize an isolated dynamic cell plate. The memory cell includes a first and second pass...
US-8,009,006 Open pattern inductor
Various embodiments includes a stacked open pattern inductor fabricated above a semiconductor substrate. The stacked open pattern inductor includes a plurality...
US-8,008,954 Multi-phase signal generator and method
Multi-phase signal generators and methods for generating multi-phase signals are described. In one embodiment, the clock generator generates quadrature clock...
US-8,008,947 Balanced phase detector
Methods and apparatus are disclosed, such as those involving a digital phase detector that includes a phase detection circuit configured to detect which one of...
US-8,008,196 Method to create a metal pattern using a damascene-like process
A method of forming a metal pattern on a dielectric layer that comprises forming at least one trench in a dielectric layer formed from a photosensitive,...
US-8,008,192 Conductive interconnect structures and formation methods using supercritical fluids
Conductive interconnect structures and formation methods using supercritical fluids are disclosed. A method in accordance with one embodiment of the invention...
US-8,008,162 Select devices including an open volume, memory devices and systems including same, and methods for forming same
Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a...
US-8,008,144 Dual work function recessed access device and methods of forming
A recessed access device having a gate electrode formed of two or more gate materials having different work functions may reduce the gate-induced drain leakage...
US-8,008,126 Castellation wafer level packaging of integrated circuit chips
Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled...
US-8,007,275 Methods and apparatuses for heating semiconductor wafers
Methods and apparatuses for heat treatment of semiconductor wafers are disclosed herein. A method of heating a semiconductor wafer in accordance with one...
US-8,006,166 Programming error correction code into a solid state memory device with varying bits per cell
Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to...
US-8,006,072 Reducing data hazards in pipelined processors to provide high processor utilization
A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of...
US-8,006,067 Flexible results pipeline for processing element
A flexible results pipeline for a processing element of a parallel processor is described. A plurality of result registers are selectively connected to each...
US-8,005,995 Command interface systems and methods
Apparatus, systems, and methods are disclosed that operate within a memory to execute internal commands, to suspend the execution of commands during a transfer...
US-8,004,920 Power saving memory apparatus, systems, and methods
Some embodiments include a voltage generator to generate a voltage to apply to a line used to access a memory cell of a memory device in which the voltage is...
US-8,004,909 Data bus power-reduced semiconductor storage apparatus
In one or more of the disclosed embodiments, the number of times toggle operations of a data bus are performed at the time of a data transmission in a...
US-8,004,892 Single latch data circuit in a multiple level cell non-volatile memory device
A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a...
US-8,004,887 Configurable digital and analog input/output interface in a memory device
Methods and memory devices are disclosed, for example a memory device that has both an analog path and a digital path that both share the same input/output pad....
US-8,004,882 Spintronic devices with integrated transistors
The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a...
US-8,004,313 Methods, devices, and systems for a high voltage tolerant buffer
Methods, devices, and systems are disclosed, including those for a buffer having pre-driver circuitry configured to provide voltages to thin-gate dielectric...
US-8,004,297 Isolation circuit
The present disclosure includes various method, device, and system embodiments for isolation circuits. One such isolation circuit embodiment includes: a first...
US-8,004,055 Electromagnetic radiation conduits
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
US-8,004,031 Memory device transistors
Method and device embodiments are described for fabricating MOSFET transistors in a semiconductor also containing non-volatile floating gate transistors. MOSFET...
US-8,003,985 Apparatus having a dielectric containing scandium and gadolinium
Apparatus having a dielectric containing scandium and gadolinium can provide a reliable structure with a high dielectric constant (high k). In an embodiment,...
US-8,003,972 Bottom electrode geometry for phase change memory
A PCRAM cell has a gradated or layered resistivity bottom electrode with higher resistivity closer to a phase change material, to provide partial heating near...
US-8,003,542 Multiple spacer steps for pitch multiplication
Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers...
US-8,003,541 Methods of forming variable resistance memory cells, and methods of etching germanium, antimony, and...
A method of etching a material that includes comprising germanium, antimony, and tellurium encompasses exposing said material to a plasma-enhanced etching...
US-8,003,526 Low resistance metal silicide local interconnects and a method of making
A process for forming a local interconnect includes applying a layer of metal over a semiconductor layer. A layer of metal silicide is formed over the layer of...
US-8,003,521 Semiconductor processing
Devices, methods, and systems for semiconductor processing are described herein. A number of method embodiments of semiconductor processing can include forming...
US-8,003,482 Methods of processing semiconductor substrates in forming scribe line alignment marks
A method of processing a semiconductor substrate in forming scribe line alignment marks includes forming pitch multiplied non-circuitry features within scribe...
US-8,003,310 Masking techniques and templates for dense semiconductor fabrication
A template comprising pitch multiplied and non-pitch multiplied features is configured for use in imprint lithography. On a first substrate, a first pattern is...
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